International Telemetering Conference Proceedings / October 26-29, 1987 / Town and Country Hotel, San Diego, California / The Very Large Array (VLA) radio telescope, located in west-central New Mexico, obtains high-resolution radio images of astronomical objects by using Fourier aperture synthesis with 27 antennas. With the addition of X-band to its receiving capabilities by 1989, and when arrayed with the Goldstone Deep Space Communications Complex (GDSCC), the VLA will double the Deep Space Network (DSN) receiving aperture in the U. S. longitude for signals from Voyager 2 at Neptune. This paper describes the VLA and the installation of the X-band system, its operation and performance for Voyager data reception, and its capabilities for other science at X-band.

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level.

Nucleoside (S)-cEt-LNA a été synthétisé par trois voies différentes à partir de la 5- méthyluridine qui est commercialement disponible. Le chemin le plus court comprend une méthylation diastéréosélective d'un aldéhyde, et une cyclisation 5-exo-tet d'un éther par déplacement SN2. / (S)-cEt-LNA nucleoside was synthesized by three different routes starting from commercially available 5-methyluridine. The shortest route includes a diastereoselective methylation of an aldehyde, and a 5-exo-tet cylization of an ether via SN2 displacement.

In a radio frequency (RF) system, the front-end of a radio receiver consists of an active antenna arrangement with a conducting mode antenna along with an active circuit. This arrangement helps avoid losses and SNR degradation due to the use of a coaxial cable. The active circuit is essentially an impedance matching network and a low noise amplification (LNA) stage. The input impedance of the antenna is always different from the source impedance required to be presented at the LNA input for maximum power gain and this gives rise to undesired reflections at the antenna-LNA junction. This necessitates a matching network that provides the impedance matching between the antenna and the LNA at a central frequency (CF). From the Friis formula it is seen that the total noise figure (NF) of the system is dependent on the noise figure and gain of the first stage. So, by having an LNA that provides a high gain (typically >15 dB) which inserts minimum possible noise (desirably < 1 dB), the overall noise figure of the system can be maintained low. The LNA amplifies the signal to a suitable power level that will enable the subsequent demodulation and decoding stages to efficiently recover the original signal. The antenna and the LNA can be matched with each other in two possible ways. The first approach is the traditional method followed in RF engineering where in both the antenna and LNA are matched to 50 W terminations and connected to each other. In this classical method, the antenna and LNA are matched to 50 W at the CF and does not take into account the matching at other frequencies in the operation range. The second approach employs a co-design method to match the antenna and LNA without a matching network or with minimum possible components for matching. This is accomplished by varying one or more parameters of either the antenna or LNA to control the impedances and ultimately achieve a matching over a substantial range of frequencies instead at the CF alone. The co-design method is shown to provide higher gain and a lower NF with reduced number of components, cost and size as compared to the classical method. The thesis work presented here is a study, design and manufacturing of an antenna-LNA module for a wide frequency range of 1.7 GHz – 2.7 GHz to explore the gain and NF improvements in the co-design approach. Planar micro strip patch antennas and GaAs E-pHEMT transistor based LNA’s are designed and the matching and co-design are simulated to test the gain and NF improvements. Furthermore, fully functional prototypes are developed with Roger R04360 substrate and the results from simulations and actual measurements are compared and discussed.

Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHz. / This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz.

Silicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.

The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.

The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.

Le premier chapitre de ce mémoire intitulé "Amplificateurs faible bruit accordés pour systèmes intégrés CMOS" s'intéresse aux méthodes de conception permettant l'intégration complète de l'amplificateur faible bruit d'une (LNA) depuis la gamme des radiofréquences jusqu'à la gamme des fréquences millimétriques. Ces travaux ont été menés dans le cadre de la Thèse de Mathieu Egels et dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône. Le deuxième chapitre est intitulé "Amplificateurs bas niveau large bande pour systèmes intégrés CMOS". Ce chapitre présente les solutions que nous avons développées au laboratoire qui permettent de contrôler la bande passante des amplificateurs faible bruit pour systèmes intégrés destinés aux applications utilisant les normes UWB ainsi que des études plus prospectives sur l'amplification distribuée CMOS pour des applications à très grandes bandes passantes. Dans la dernière partie de ce chapitre nous décrivons nos travaux concernant la mise en boîtier des circuits et systèmes intégrés haute fréquence et large bande. Ces différents travaux ont été réalisés d'une part dans le cadre des Thèses de Mathieu Egels, et de Marc Battista, dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône, et d'autre part dans le cadre de la thèse de Romen Cubillo avec le soutien de la plateforme conception du Centre Intégré de Microélectronique de la région PACA (CIMPACA). Le troisième chapitre "Convertisseurs RF/DC pour la téléalimentation haute fréquence en RFID" décrit nos activités de recherche concernant les circuits et architectures pour la télé-alimentation des circuits intégrés au moyen d'une onde électromagnétique. Les applications ciblées concernent essentiellement les étiquettes électroniques sans contact dans le domaine des fréquences UHF pour lesquelles nous avons développé des circuits et des architectures pour les technologies CMOS standard. Ces travaux ont été réalisés dans le cadre de la Thèse de Emmanuel Bergeret dans le cadre d'une convention de recherche avec la société ST-Microélectronics soutenue par le Conseil Général des Bouches du Rhône. Dans ce mémoire nous nous attacherons à décrire l'état de l'art des différents thèmes de recherche abordés et à situer nos travaux vis-à-vis de cet état de l'art. Le détail de nos travaux de recherche étant disponible dans les différents articles et thèses référencés, nous donnerons dans ce mémoire uniquement les grandes lignes de nos études et les principaux résultats obtenus.

The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply.