A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise. / QC 20100928

No description available.

Les travaux de thèse, présentés dans ce manuscrit, portent sur la caractérisation et la modélisation des sources de bruit basse fréquence dans les transistors bipolaires à hétérojonction Si/SiGe:C issus des filières BiCMOS 130 et 55 nm utilisées pour la réalisation de circuits intégrés dédiés aux futures applications dans le domaine du THz. A partir des mesures réalisées en fonction de la polarisation, de paramètres géométriques (surface et périmètre d'émetteur principalement) et de la température, la composante de bruit en 1/f, associée aux fluctuations du courant de base, a été entièrement caractérisée et les sources de bruit associées localisées. Les paramètres du modèle compact SPICE ont été extraits et comparés avec ceux de la littérature. Pour la technologie BiCMOS 130 nm, la valeur obtenue pour la figure de mérite KB égale 6,8 10-11 µm² ce qui représente le meilleur résultat publié à ce jour, toutes filières de transistors bipolaires confondues. Réalisée sur une plaque entière, l'étude statistique de la dispersion du niveau de bruit en 1/f a permis d'étendre la modélisation compacte de type SPICE. Mesuré sur une large gamme de température, le niveau de bruit en 1/f n'a pas présenté de variation significative. Pour la première fois, une étude complète de la composante de bruit en 1/f associée aux fluctuations du courant de collecteur est présentée et les paramètres du modèle SPICE extraits. Concernant la caractérisation des composantes de génération-recombinaison (présence non systématique), une étude statistique a montré que les transistors de plus petites dimensions étaient les plus impactés. La comparaison entre les différentes technologies montre que ces composantes sont beaucoup plus présentes dans les technologies les moins matures. Quand ces composantes ont été associées à du bruit RTS, une méthode de caractérisation temporelle et fréquentielle a été mise en œuvre. Enfin, dans certains cas, une étude en basses températures a permis d'extraire les énergies d'activation des pièges responsables de ces composantes de génération-recombinaison. / The presented thesis work, in this manuscript, focuses on the characterization and modeling of the low frequency noise sources in heterojunction bipolar transistors Si/SiGe :C derived from 130 to 55 nm BiCMOS technology used in the production of integrated circuits dedicated for THz domain applications. From measurements versus bias, geometrical parameters (emitter area and perimeter) and temperature, the 1/f noise component, associated to the base current fluctuations, has been fully characterized and the associated sources have been localized. The SPICE compact model parameters have been extracted and compared with those of the literature. For the BiCMOS 130 nm technology, the obtained figure of merit value of 6,8 10-11 µm2 represents the best published result so far in all bipolar transistors. The dispersion study of the 1/f noise component, performed over a complete wafer, allowed us to extend the SPICE type compact modeling. Measured over a large temperature range, the 1/f noise did not show any variations. For the first time, a complete characterization of the 1/f component at the output of the transistors is presented as well as the extraction of SPICE parameters. Regarding the characterization of generation-recombination components (unsystematic presence), a statistical study has showed that transistors with small emitter areas (Ae < 1 µm2) are affected more than the transistors with large emitter areas by the presence of g-r components. Comparison between different technologies shows that these components are much more present in the less mature technologies. When these components have been associated to RTS, time and frequency domain method is implemented. Finally, in some cases, a study at low temperatures was used to extract the activation energy of the traps responsible for the generation-recombination components.

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

L'invention du premier transistor à Bell lab's, dans le groupe de W. Shockley, en 1947 a été suivie d'une ère de développement des circuits intégrés (IC). Depuis plusieurs dizaines d'années, la dimension critique des transistors métal/oxyde/semi-conducteurs (les transistors MOS), la longueur physique de la grille, a diminué à un rythme régulier. Cette évolution, motivée par des raisons économiques, a été anticipée par G. Moore, et est de ce fait connue sous le nom de "loi de Moore". La dimension de grille a d'ores et déjà été réduite de plus de 2 ordres de grandeur et, dans son édition2012, l'association ITRS prédit qu'elle décroîtra encore, de 22nm en 2011 à environ 6nm en 2026 [1].Toutefois, cette réduction des dimensions fait apparaître un certain nombre d'effets secondaires qui altèrent le fonctionnement idéal des transistors MOS [2]. / In this dissertation, the performance of junction less transistors (JLTs) as possible candidates for the continuation of Moore’s law was investigated experimentally based on an in-depth study of their electrical characteristics. Current-voltage I-V and capacitance-voltage C-V were analyzed in a wide rangeof temperatures (from 80 K to 350 K) in correlation with device operation mechanism. Lowfrequencynoise was also studied and compared to that of inversion-mode transistors. This study requirednew parameter extraction methods to be defined for JLTs. Their validity was confirmed by 2-dimensional (2D) simulation results. They will be detailed in this dissertation.

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

Ion sensing represents a grand research challenge. It finds a vast variety of applications in, e.g., gas sensing for domestic gases and ion detection in electrolytes for chemical-biological-medical monitoring. Semiconductor genome sequencing exemplifies a revolutionary application of the latter. For such sensing applications, the signal mostly spans in the low frequency regime. Therefore, low-frequency noise (LFN) present in the same frequency domain places a limit on the minimum detectable variation of the sensing signal and constitutes a major research and development objective of ion sensing devices. This thesis focuses on understanding LFN in ion sensing based on both experimental and theoretical studies. The thesis starts with demonstrating a novel device concept, i.e., ion-gated bipolar amplifier (IGBA), aiming at boosting the signal for mitigating the interference by external noise. An IGBA device consists of a modified ion-sensitive field-effect transistors (ISFET) intimately integrated with a bipolar junction transistor as the internal current amplifier with an achieved internal amplification of 70. The efficacy of IGBA in suppressing the external interference is clearly demonstrated by comparing its noise performance to that of the ISFET counterpart. Among the various noise sources of an ISFET, the solid/liquid interfacial noise is poorly studied. A differential microelectrode cell is developed for characterizing this noise component by employing potentiometry and electrochemical impedance spectroscopy. With the cell, the measured noise of the TiN/electrolyte interface is found to be of thermal nature. The interfacial noise is further found to be comparable or larger than that of the state-of-the-art MOSFETs. Therefore, its influence cannot be overlooked for design of future ion sensors. To understand the solid/liquid interfacial noise, an electrochemical impedance model is developed based on the dynamic site-binding reactions of surface hydrogen ions with surface OH groups. The model incorporates both thermodynamic and kinetic properties of the binding reactions. By considering the distributed nature of the reaction energy barriers, the model can interpret the interfacial impedance with a constant-phase-element behavior. Since the model directly correlates the interfacial noise to the properties of the sensing surface, the dependencies of noise on the reaction rate constants and binding site density are systematically investigated.

In dieser Arbeit wird das epitaktische Wachstum von GaP/Si Heterostrukturen zur Herstellung von rauscharmen GaP/Si Nanodiodenarrays untersucht, wobei eine top-down Ätztechnik zur Herstellung der verwendeten Nanodiodenarrays genutzt wurde. Zur Untersuchung der gewachsenen Schichten wurden Röntgenstreuung (XRD), Rasterelektronenmikroskopie sowie die elektrische Charakterisierung mittels Strom-Spannungs und Kapazität-Spannungsmessungen verwendet. Zudem wurde die Grenzfläche zwischen epitaktischer Schicht und Substrat mittels Niederfrequenter Rauschspektroskopie (LFN) untersucht. Die GaP-Schichten wurden auf p-dotierten Si (100) Substraten mittels eines Riber-32P Gasquellen-Molekularstrahlepitaxiesystems gewachsen. Die Abhängigkeit der Oberflächenbeschaffenheit und Kristallqualität von denWachstumsbedingungen, wie der Wachstumstemperatur, wurden intensiv untersucht, um die Defektdichte zu minimieren. Dafür wurden nominal 500 nm dicke Heterostrukturschichten beiWachstumstemperaturen von 550 °C, 400 °C und 250 °C gewachsen, wobei 400 °C als die optimale Wachstumstemperatur bestimmt wurde. Trotzdem waren die erhaltenen Schichten aufgrund der hohen Versetzungsdichte von schlechter Qualität. Eine nur sehr geringe Qualitätsverbesserung konnte durch einen in situ durchgeführten thermischen Annealingschritt bei 500 °C für 10 Minuten erreicht werden. Daher wurde eine neue Annealingmethode vorgeschlagen, die in dieser Arbeit step-graded annealing (SGA) genannt wird. Bei dieser Methode wurde die Temperatur schrittweise von 400 °C auf 480 °C innerhalb von 90 Minuten erhöht. Dabei wurde die Oberfläche die gesamte Zeit mittels Reflexion hochenergetischer Elektronen (RHEED) untersucht. Die Oberflächenrekonstruktion, die während des Annealens mittels RHEED beobachtet wurde, zeigte schließlich eine große Verbesserung der Kristallqualität. Die Gitterparameter von GaP wurden mittels asymmetrischer XRD gemessen, wobei festgestellt wurde, dass sie exakt denen von Volumen-GaP entsprechen. Zudem wurde festgestellt, dass die GaP-Schicht automatisch n-dotiert ist und diodentypisches Gleichrichtungsverhalten aufweist. Interessante Informationen über Fallenzustände in den Heterostrukturfilmen konnten mittels LFN-Messungen gefunden werden. In einer nicht annealten Probe wurden beispielsweise zwei Fallenzustände im Bereich der Bandlücke festgestellt. In den mittels der SGA-Methode annealten Proben wurde hingegen ein rauscharmes und fallenfreies System erhalten. Anschließend wurde Elektronenstrahllithografie (EBL) zum Erstellen von Nanomustern auf der Oberfläche genutzt, die zur Herstellung von Nanodrähten genutzt werden sollen. Zur Optimierung der Elektronenstrahllithografie wurden dabei GaPSubstrate aufgrund der im Vergleich zu den epitaktischen Schichten besseren und glatteren Oberflächenstruktur genutzt. Dabei konnten in einer Goldschicht 200 nm große Löcher in einem Gitter mit hoher Dichte auf GaP erstellt und in die GaPSchicht übertragen werden. Die metallunterstütztes chemisches Ätzen (MacEtch) genannte Technik wurde kürzlich vorgeschlagen und eignet sich für die Herstellung von Nanodrähten. Die Anwendung zur Herstellung von Nanodrähten aus GaP war herausfordernd aufgrund bisher begrenzter Anwendung für III-V Halbleiter. Zur Optimierung der MacEtch Technik wurde zunächst wieder GaP-Substrat verwendet, um den Einfluss von Kristalldefekten und der Oberflächenrauigkeit auf die Ergebnisse zu minimieren. Genutzt wurde ein Gemisch aus Lösungen von HF/KMnO4 mit verschiedenen Konzentrationen. Mit den so bestimmten Prozessbedingungen konnten erfolgreich GaP Nanodrähte aus GaP-Epilayern hergestellt werden. GaP/Si Heteroübergangsnanodioden wurden anschließend unter Nutzung von Au-Ge/Ni Kontakten zu GaP-Schicht und Al/Ni Kontakten zum rückseitigen Si hergestellt. Die Transporteigenschaften des Nanodiodenarrays bestätigen die Möglichkeit, diese Arrays als elektronische NiederLärmbauelemente einzusetzen. / An epitaxial growth of GaP/Si heterostructures for the fabrication of low-noise GaP/Si nanodiode array based on nanowires is reported. The grown films were characterized using X-ray diffraction, scanning-electron microscopy, atomic-force microscopy and electrical measurements. Besides that, the interface between the epilayer and the substrate was deeply studied using a low-frequency noise (LFN) spectroscopy. The GaP epilayers were grown on p-type Si (100)substrates using gas-source molecular-beam epitaxy system. The dependence of surface morphology and crystal quality on the growth conditions was intensively investigated for minimizing the defects. The heterostructure films were grown at an optimal growth temperature of 400 °C and a nominal thickness of 500 nm. In order to improve the crystalline quality of the heterostructures, a new thermal annealing method was proposed, and referred to as step-graded annealing (SGA). In this method, the temperature was increased gradually to the annealing temperature to reduce the strain relaxation in the epilayers. A highly improvement in the crystal quality was confirmed using the SGA method. In addition, the epilayers were found to be n-type autodoped, and exhibited diode rectification behavior. Furthermore, the trap levels in the band gap, which were revealed via LFN measurements, were found to be suppressed in the annealed films. Thereafter, gold-mesh nanopatterns on the GaP surfaces were fabricated using an electron-beam lithography, as a step for the fabrication of GaP nanowires. A metal-assisted chemical etching technique with a mixture of HF:KMnO4 was carried out to fabricate GaP nanowires. GaP/Si heterojunction nanodiodes were then fabricated using an Au-Ge/Ni contact on the top of the GaP nanowires as well as an Al/Ni contact on the backside of Si. Transport properties of the nanodiode array confirmed the possibility of using the array as a low-frequency electronic device.

Cette thèse porte sur l’étude de transistor à effet tunnel (TFET) en FDSOI à géométries planaire et triple grille/nanofils. Nous rapportons pour la première fois des TFETs fabriqués par un processus basse température (600°C), qui est identique à celui utilisé pour l’intégration monolithique 3D. La méthode “Dual IDVDS” confirme que ces TFETs fonctionnent par effet tunnel et non pas par effet Schottky. Les résultats des mesures électriques montrent que l’abaissement de la température de fabrication de 1050°C (HT) à 600°C (LT) ne dégrade pas les propriétés des TFETs. Néanmoins, les dispositifs réalisés à basse température montrent un courant de drain et de fuite plus élevés et une tension de seuil différente par rapport aux HT TFETs. Ces phénomènes ne peuvent pas être expliqués par le mécanisme d’effet tunnel. Le courant de pompage de charges révèle une densité d’états d’interface plus grande à l’interface oxide/Si pour les dispositifs LT que dans les TFETs HT pour les zones actives étroites. Par ailleurs, une analyse de bruit basse fréquence permet de mieux comprendre la nature des pièges dans les TFETs LT et HT. Dans les TFETs réalisés à basse température nous avons mis en évidence une concentration en défauts non uniforme à l’interface oxide/Si et à la jonction tunnel qui cause un effet tunnel assisté par piège (TAT). Ce courant TAT est responsable de la dégradation de la pente sous seuil. Ce résultat montre la direction à suivre pour optimiser ces structures, à savoir une épitaxie de très haute qualité et une optimisation fine des jonctions. Finalement, nous avons proposé de nouvelles architectures innovatrices de transistors à effet tunnel. L’étude de simulation TCAD montre que l’extension de la jonction tunnel dans le canal augmente la surface de la région qui engendre le courant BTBT. Une fine couche dopée avec une dose ultra-haute en bore pourrait permettre l’obtention à la fois d’une pente sous le seuil faible et un fort courant ON pour le TFET. / This thesis presents a study of FDSOI Tunnel FETs (TFETs) from planar to trigate/nanowire structures. For the first time we report functional “Low-Temperature” (LT) TFETs fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration. “Dual IDVDS” method confirms that these devices are real TFETs and not Schottky FETs. Electrical characterization shows that LT TFETs performance is comparable with “High-Temperature” (HT) TFETs (1050°C). However, LT TFETs exhibit ON-current enhancement, OFF-current degradation and VTH shift with respect to HT TFETs that cannot be explained via BTBT mechanism. Charge pumping measurements reveal a higher defect density at the top silicon/oxide interface for geometries with narrow widths in LT than HT TFETs. In addition, low-frequency noise analyses shed some light on the nature of these defects. In LT TFETs, we determined a non-uniform distribution of defects at the top surface and also at the tunneling junction that causes trap-assisted tunneling (TAT). TAT is responsible of the current generation that degrades the subthreshold swing. This indicates the tight requirements for quality epitaxy growth and junction optimization in TFETs. Finally, we proposed novel TFET architectures. TCAD study shows that the extension of the source into the body region provides vertical BTBT and a larger tunneling surface. Ultra-thin heavily doped boron layers could allow the possibility to obtain simultaneously a good ON-current and sub-thermal subthreshold slope in TFETs.

O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno, a condutância de saída, a tensão Early e o ganho de tensão intrínseco serão estudados tanto experimentalmente como através de simulações numéricas tridimensionais para diferentes concentrações de dopantes no canal. Os resultados indicam que a configuração DTMOS apresenta as características elétricas superiores (4 e 10 %) e maior eficiência dos transistores. Além disso, os dispositivos DTMOS com alta concentração de dopantes no canal apresentaram um desempenho analógico muito melhor quando comparados ao transistor de porta tripla de Corpo em modo de operação convencional. O ruído de baixa frequência (LF) é pela primeira vez experimentalmente analisado na região linear e saturação. A origem do ruído é analisada de maneira a compreender os mecanismos físicos envolvidos neste tipo de ruído. As medições mostraram que os espectros do sinal dos dispositivos de porta tripla de Corpo e DTMOS são compostos por flutuações referentes ao número de portadores devido ao ruído flicker e por ondas de ruído de geração e recombinação no dielétrico de porta que se torna maior com o aumento da tensão de porta. No entanto, o principal fato desta análise é que o dispositivo DTMOS apresentou praticamente a mesma magnitude do ruído LF na região linear e de saturação que o dispositivo de Corpo. A energia de 60 MeV na fluência de p/1012 cm-2 de radiações de prótons é também estudada experimentalmente em termos das características elétricas, desempenho do analógico e ruído LF nos dispositivos de porta tripla de Corpo e DTMOS. Os resultados indicam que combinado com as suas melhores características elétricas e um ótimo desempenho analógico do DTMOS, faz o transistor de porta tripla de Corpo um candidato muito competitivo para aplicações analógicas em ruído de baixa frequência antes e depois da irradiação. A vantagem da técnica DTMOS em transistores de porta tripla em ambientes onde os dispositivos têm de suportar alta radiação é devido à menor penetração do campo de dreno que reduz o efeito das cargas induzidas pelo óxido de isolação (STI). Finalmente, o transistor de Corpo de porta tripla de canal tipo-n é experimentalmente estudado como célula de memória, isto é, como 1T-DRAM (Memória de Acesso Aleatório Dinâmico com 1 transistor). Para escrever e ler 1 é utilizado um modo de programação que utiliza o efeito do transistor bipolar parasitário (BJT) enquanto a polarização direta da junção do corpo e do dreno é usada para escrever 0. As correntes de leitura e escrita aumentam com o aumento da tensão do corpo (VB) porque as cargas induzidas pelo efeito BJT é armazenada dentro da aleta. Quando o corpo do transistor está flutuante, o dispositivo retém mais cargas dentro da sua aleta. Além disso, transistor de Corpo pode ser utilizado como 1T-DRAM com eletrodo de porta e substrato flutuando. Neste caso, o dispositivo funciona como um biristor (sem porta). / The main goal of this work is to investigate the n-channel MuGFETs (triple-gate) Bulk transistors with and without the application of DTMOS operation. This work will be done through three-dimensional numerical simulation and by electrical characterizations. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DTMOS mode and the standard biasing configuration. Important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional numerical simulations for different channel doping concentrations. The results indicate that the DTMOS configuration has superior electrical characteristics (4 e 10 %) and higher transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode. Low-Frequency (LF) noise is for the first time experimentally investigated in linear and saturation region. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in this type of noise. Measurements showed that the signal spectra for Bulk and DTMOS are composed of number fluctuations related flicker noise with on top generation and recombination noise humps, which become more pronounced at higher gate voltage. However, the most important finding is the fact that DTMOS devices showed practically the same LF noise magnitude in linear and saturation region than standard Bulk device. Proton irradiation with energy of 60 MeV and fluence of p/1012 cm-2 is also experimentally studied in terms of electric characteristic, analog performance and the LF noise in Bulk and DTMOS triple gate devices. The results indicate that the combined of the better electrical characteristics and an excellent analog performance of DTMOS devices, makes it a very competitive candidate for low-noise RF analog applications before and after irradiation. The advantage of dynamic threshold voltage in triple gate transistors in environments where the devices have to withstand high-energy radiation is due to its lower drain electric field penetration that lowers the effect of the radiation-induced charges in the STI (shallow trench isolation) regions adjacent to the fin. Finally, the n-channel triple gate Bulk device is used for memory application, that is, 1T-DRAM (Dynamic Random Access Memory with 1 Transistor). Bipolar junction transistor (BJT) programming mode is used to write and read 1 while the forward biasing of the body-drain junction is used to write 0. The reading and writing current increases with increasing body bias (VB) because the load induced by the BJT effect is stored within the fin. When the body of the transistor is floating, the device retains more charge within its fin. In addition, transistor could also operate as 1T-DRAM with both gate and bulk contacts floating, which is similar to the biristor (gateless) behavior.