Made available in DSpace on 2014-06-11T19:32:45Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-03-25Bitstream added on 2014-06-13T19:22:18Z : No. of bitstreams: 1 stupiello_ena_dr_sjrp.pdf: 980318 bytes, checksum: 65f85d4d951959755414469d5e56e14d (MD5) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / As transformações experimentadas no mundo considerado globalizado têm gerado o crescimento do montante de informações e a urgência de disseminação das mesmas além fronteiras, promovendo o expressivo aumento da demanda por traduções elaboradas de maneira rápida e segundo padrões de produção específicos. Para atender a essas exigências e manterem-se competitivos, tradutores, cada vez mais, estão lançando mão das ferramentas tecnológicas atualmente disponíveis, em especial, sistemas de memórias de tradução. A aplicação dessas ferramentas requer que o tradutor siga determinadas regras que garantam o desempenho prometido, especialmente pela manipulação de termos e fraseologias utilizados na tradução a fim de garantir seu reaproveitamento em trabalhos futuros. A crescente adoção de ferramentas pelo tradutor contemporâneo suscita uma reflexão de cunho ético sobre a extensão de sua responsabilidade pelo material traduzido. Visando a esse fim, nesta tese, investigam-se os pressupostos teóricos que sustentam os projetos dessas ferramentas tecnológicas de tradução, analisando-se tanto as contribuições que elas têm proporcionado ao tradutor, como algumas das questões que procedem do modo como a profissão é concebida como resultado do uso dos recursos por elas disponibilizados. Para fomentar a análise proposta, foram examinados os recursos pressupostos como dinamizadores do trabalho do tradutor, principalmente pelas funções de segmentação do texto de origem, alinhamento de traduções e pelo processo de correspondência textual disponíveis em três sistemas de memória: o Wordfast, o Trados e o Transit. O estudo dos projetos e dos recursos disponibilizados por essas ferramentas auxiliou a análise sobre o envolvimento do tradutor com a tradução, quando esse profissional integra um processo maior de produção... / Transformations in the globalized world have generated the growth of the amount of information and the urgency of its dissemination beyond borders, promoting a significant increase in the demand for translations performed fast and according to specific production standards. In order to comply with these requirements and remain competitive, translators are more and more embracing the technological tools currently available, mainly, translation memory systems. The application of these tools requires the translator to follow certain rules that guarantee the promised performance, mainly by manipulating terms and phraseologies used in the translation so as to ascertain their reuse in future translations. The growing adoption of tools by the contemporary translator calls for an ethical consideration of the extension of the translator’s responsibility for the translated material. In this thesis, the theoretical assumptions supporting the projects of these translation technological tools are investigated through the analysis of both the contributions they have been providing for the translator and some issues that arise from the way the profession is conceived as a result of the use of the resources made available by these tools. To foment the proposed analysis, resources deemed to make the translator’s work more dynamic have been examined, mainly through the functions of source-text segmentation, translation alignment and textual matching available in three translation memory systems: Wordfast, Trados and Transit. The study of the projects and resources made available by these tools encouraged the analysis of the translator’s involvement with the translation when he/she is part of a larger process of production and distribution of information to audiences located in the most varied places in the world. From this analysis, a survey was carried out of issues... (Complete abstract click electronic access below)

Orientador: Peter Sussner / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Computação Cientifica / Made available in DSpace on 2018-08-05T07:48:58Z (GMT). No. of bitstreams: 1 Mesquita_MarcosEduardoRibeirodoValle_M.pdf: 893884 bytes, checksum: 9e4611642968683b375b78c5424ac19d (MD5) Previous issue date: 2005 / Resumo: Memórias associativas neurais são modelos do fenômeno biológico que permite o armazenamento de padrões e a recordação destes apos a apresentação de uma versão ruidosa ou incompleta de um padrão armazenado. Existem vários modelos de memórias associativas neurais na literatura, entretanto, existem poucos trabalhos comparando as varias propostas. Nesta dissertação comparamos sistematicamente o desempenho dos modelos mais influentes de memórias associativas neurais encontrados na literatura. Esta comparação está baseada nos seguintes critérios: capacidade de armazenamento, distribuição da informação nos pesos sinápticos, raio da bacia de atração, memórias espúrias e esforço computacional. Especial ênfase dado para as memórias associativas morfológicas cuja fundamentação matemática encontra-se na morfologia matemática e na álgebra de imagens / Abstract: Associative neural memories are models of biological phenomena that allow for the storage of pattern associations and the retrieval of the desired output pattern upon presentation of a possibly noisy or incomplete version of an input pattern. There are several models of neural associative memories in the literature, however, there are few works relating them. In this thesis, we present a systematic comparison of the performances of some of the most widely known models of neural associative memories. This comparison is based on the following criteria: storage capacity, distribution of the information over the synaptic weights, basin of attraction, number of spurious memories, and computational effort. The thesis places a special emphasis on morphological associative memories whose mathematical foundations lie in mathematical morphology and image algebra / Mestrado / Matematica Aplicada / Mestre em Matemática Aplicada

Le but de cette thèse est d'exploiter efficacement le parallélisme présent dans les applications informatiques séquentielles afin de bénéficier des performances fournies par les multiprocesseurs, en utilisant une nouvelle méthodologie pour la parallélisation automatique des tâches au sein des compilateurs. Les caractéristiques clés de notre approche sont la prise en compte des contraintes de ressources et le caractère statique de l'ordonnancement des tâches. Notre méthodologie contient les techniques nécessaires pour la décomposition des applications en tâches et la génération de code parallèle équivalent, en utilisant une approche générique qui vise différents langages et architectures parallèles. Nous implémentons cette méthodologie dans le compilateur source-à-source PIPS. Cette thèse répond principalement à trois questions. Primo, comme l'extraction du parallélisme de tâches des codes séquentiels est un problème d'ordonnancement, nous concevons et implémentons un algorithme d'ordonnancement efficace, que nous nommons BDSC, pour la détection du parallélisme ; le résultat est un SDG ordonnancé, qui est une nouvelle structure de données de graphe de tâches. Secondo, nous proposons une nouvelle extension générique des représentations intermédiaires séquentielles en des représentations intermédiaires parallèles que nous nommons SPIRE, pour la représentation des codes parallèles. Enfin, nous développons, en utilisant BDSC et SPIRE, un générateur de code que nous intégrons dans PIPS. Ce générateur de code cible les systèmes à mémoire partagée et à mémoire distribuée via des codes OpenMP et MPI générés automatiquement. / This thesis intends to show how to efficiently exploit the parallelism present in applications in order to enjoy the performance benefits that multiprocessors can provide, using a new automatic task parallelization methodology for compilers. The key characteristics we focus on are resource constraints and static scheduling. This methodology includes the techniques required to decompose applications into tasks and generate equivalent parallel code, using a generic approach that targets both different parallel languages and architectures. We apply this methodology in the existing tool PIPS, a comprehensive source-to-source compilation platform. This thesis mainly focuses on three issues. First, since extracting task parallelism from sequential codes is a scheduling problem, we design and implement an efficient, automatic scheduling algorithm called BDSC for parallelism detection; the result is a scheduled SDG, a new task graph data structure. In a second step, we design a new generic parallel intermediate representation extension called SPIRE, in which parallelized code may be expressed. Finally, we wrap up our goal of automatic parallelization in a new BDSC- and SPIRE-based parallel code generator, which is integrated within the PIPS compiler framework. It targets both shared and distributed memory systems using automatically generated OpenMP and MPI code.

No description available.

During team decision-making practices information is often shared among team members as part of the decision making process. Knowledge sharing involves one team member sharing information so that other team members can encode the knowledge to make their own mental representation of the new information (Huan & Jiang, 2012). Unfortunately, the literature has shown that new information is not always shared between team members during decision making processes (Stasser & Titus, 1985). When teams make decisions without considering all the information available poor decisions can result. This research study tests a team conceptual model derived by Turner (2013) addressing attitudes toward knowledge sharing. Structural equation modeling was conducted to test a portion of Turner’s (2013) team conceptual model. The tested model included the independent variables of psychological safety, team conflict, team cohesion, and transactive memory systems. The dependent variable for the dissertation was knowledge sharing.

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal.

The trends in virtualization as well as multi-core, multiprocessor environments have translated to a massive increase in the amount of main memory each individual system needs to be fitted with, so as to effectively utilize this growing compute capacity. The increasing demand on main memory implies that the main memory devices and their issues are as important a part of system design as the central processors. The primary issues of modern memory are power, energy, and scaling of capacity. Nearly a third of the system power and energy can be from the memory subsystem. At the same time, modern main memory devices are limited by technology in their future ability to scale and keep pace with the modern program demands thereby requiring exploration of alternatives to main memory storage technology. This dissertation exploits dynamic knowledge of memory state and memory data value to improve memory performance and reduce memory energy consumption. A cross-boundary approach to communicate information about dynamic memory management state (allocated and deallocated memory) between software and hardware viii memory subsystem through a combination of ISA support and hardware structures is proposed in this research. These mechanisms help identify memory operations to regions of memory that have no impact on the correct execution of the program because they were either freshly allocated or deallocated. This inference about the impact stems from the fact that, data in memory regions that have been deallocated are no longer useful to the actual program code and data present in freshly allocated memory is also not useful to the program because the dynamic memory has not been defined by the program. By being cognizant of this, such memory operations are avoided thereby saving energy and improving the usefulness of the main memory. Furthermore, when stores write zeros to memory, the number of stores to the memory is reduced in this research by capturing it as compressed information which is stored along with memory management state information. Using the methods outlined above, this dissertation harnesses memory management state and data value information to achieve significant savings in energy consumption while extending the endurance limit of memory technologies. / text

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal

The Chip Multi-Processor (CMP) paradigm has cemented itself as the archetypal philosophy of future microprocessor design. Rapidly diminishing technology feature sizes have enabled the integration of ever-increasing numbers of processing cores on a single chip die. This abundance of processing power has magnified the venerable processor-memory performance gap, which is known as the ”memory wall”. To bridge this performance gap, a high-performing memory structure is needed. An attractive solution to overcoming this processor-memory performance gap is using compression in the memory hierarchy. In this thesis, to use compression techniques more efficiently, compressed cacheline size information is studied, and size-aware cache management techniques and hot-cacheline prediction for dynamic early decompression technique are proposed. Also, the proposed works in this thesis attempt to mitigate the limitations of phase change memory (PCM) such as low write performance and limited long-term endurance. One promising solution is the deployment of hybridized memory architectures that fuse dynamic random access memory (DRAM) and PCM, to combine the best attributes of each technology by using the DRAM as an off-chip cache. A dual-phase compression technique is proposed for high-performing DRAM/PCM hybrid environments and a multi-faceted wear-leveling technique is proposed for the long-term endurance of compressed PCM. This thesis also includes a new compression-based hybrid multi-level cell (MLC)/single-level cell (SLC) PCM management technique that aims to combine the performance edge of SLCs with the higher capacity of MLCs in a hybrid environment.

[pt] A memória se apresenta em sistemas distintos e interligados. Ela permite a constituição do sujeito e sua interação com o meio em que vive. Durante o desenvolvimento, mudanças biológicas e comportamentais vão ocorrendo, algumas vezes de forma rápida e outras, lentamente, respeitando a maturação neuronal, a interação social e a cultura em que vive. Nesse contexto, a emoção tem um papel modulador das funções cognitivas, fortalecendo ou enfraquecendo o armazenamento de uma informação, ou seja, influenciando a memória. Seu armazenamento pode ser sensorial, de curto e de longo prazo e ela pode se dividir em estágios (codificação, armazenamento e recuperação) e em tipos (explícita ou declarativa e implícita ou não declarativa). A memória explícita se subdivide em episódica e semântica, a implícita inclui os hábitos e habilidades, e a memória de curto prazo inclui a memória de trabalho. As áreas cerebrais envolvidas são o hipocampo, lobos frontal e temporal e a amígdala. Há distinção dos sistemas de memória durante o desenvolvimento: bebês reproduzem ações, reconhecem faces e eventos familiares e apresentam memória implícita (que não se altera muito ao longo do desenvolvimento); crianças pré-escolares apresentam uma memória mais sofisticada, organizando melhor as informações; e na fase escolar a memória já se encontra mais desenvolvida. O estudo mostrou que a memória semântica melhora gradualmente com a idade, acompanhando a ampliação de vocabulário; a memória episódica se desenvolve de forma mais pontual; e a memória de trabalho apresenta maturação mais tardia, acompanhando o desenvolvimento das funções executivas. / [en] The memory is divided into different systems and interconnected. It allows the creation of the subject and its interaction with the environment in which they live. During the development, behavioral and biological changes are occurring, sometimes quickly and others slowly, respecting the neuronal maturation, social interaction and culture in which they live. In this aspect, some skills are innate and others, acquired, learned. In this context, emotion plays a modulator of cognitive functions, strengthening or weakening the storage of information, ie, influencing memory. It can present divided into stages (sensory, short term and long term), in steps (encoding, storage and retrieval), and types (declarative or explicit and implicit or non-declarative). The explicit type is subdivided into episodic and semantic, the implicit include the habits and skills, and the short-term memory includes the working memory. The brain areas involved are the hippocampus, frontal and temporal lobes, and amygdale. in the formation of new memories and the recognition and consolidation during learning, and amygdala, allowing storage of the episodes that involve more emotion. There are distinctions in the memory systems during the development: babies reproduce actions, recognize faces and family events and have implicit memory (which does not change much throughout development), preschool children have a more sophisticated memory by organizing the information better; and during school memory is already more developed. The study showed that semantic memory improves gradually with age, following the expansion of vocabulary; episodic memory develops in a more timely, and working memory presents late maturation, following the development of executive functions.