Multilevel inverters have advantages over two-level inverters such as reduced THD, ability to operate at low switching frequencies, reduced switching losses etc. Moreover, higher voltage levels can be handled with devices of lower voltage rating. The main disadvantage with the multilevel configurations compared to the two-level inverter configuration is the increase in the number of power devices required and the circuit complexity, which necessitates complex control schemes that add to the cost. Also, the reliability of the converters comes down as the number of devices increases. Reduction in complexity and modularity are desirable characteristics for the multilevel inverters. Open-end winding Induction Motor (IM) drive configurations are shown to have advantages over the motor drive schemes with isolated neutral. The DC-link requirement in case of open-end winding structures comes down to half the voltage rating of the conventional NPC inverters. The DC- link requirement in case of open-end winding structures comes down to half compared to that of the conventional NPC inverters. The number of switching states is higher in the case of open-end winding configuration compared to multiplicity of switching states of conventional NPC inverters, which gives a control flexibility that can be used for optimizing the hardware requirements. Taking advantage of the flexibility given by open-end winding configuration, this thesis proposes schemes which have reduced power circuit complexity. Non-sinusoidal voltage fed IM drives suffer from the problems related to the common mode voltage (CMV) generated by the inverters. This CMV causes bearing currents and shaft voltages which in turn cause increased conducted EMI, ground loop currents and premature bearing failure. A three-level scheme was proposed for an open-end winding Induction machine in the literature, which completely eliminate the CMV variation from the pole voltages as well as the phase voltages. This configuration uses 24 controlled switches and two isolated DC-sources. In this thesis, three-level inverter schemes with CMV elimination and reduced power device count for an open-end winding IM drive are proposed. The first scheme gets the reduction in switch count by sharing the top inverter of the three-level scheme and the second scheme achieves the same by sharing the bottom inverter. This way, the number of controlled switches comes down to 18 from 24. Another problem with multilevel inverters is the large number of isolated DC-sources required to achieve the multilevel inversion. Reducing the number of isolated supplies and using capacitors to split the voltage levels poses the problem of capacitor voltage balancing. A four-level inverter with both CMV elimination and capacitor voltage balancing for an open-end winding IM drive is proposed in this thesis. The motor is fed by two four-level inverters from both the sides. A closed loop capacitor voltage balancing scheme is implemented and the redundancies in the switching states are used for achieving the capacitor voltage balancing and thereby reducing the total number of DC-link to two. The control scheme is independent of the load power factor and maintains the balance in the entire modulation range. A five-level inverter scheme is proposed for an open-end winding IM drive in this thesis. It requires only two isolated DC-sources to achieve the five-level inversion. The motor is fed by one NPC three-level inverter from one side and a two-level inverter from the other. The inverters on either side share the DC-sources. Common mode voltage in the phases are made zero in an average sense using sine-triangle modulation in the proposed scheme so that the common mode currents through the phases are suppressed. The maximum fundamental voltage that can be obtained at the phase is limited to 0.5Vdc. DC-link requirement of the inverter scheme is half of that of conventional five-level inverter scheme because of the open-end winding structure. The two-level inverter, which should withstand half the DC-link voltage, is always in square wave operation and hence the switching losses are very less. All the schemes are simulated extensively in MATLAB/Simulink and experimentally verified on laboratory prototypes under V/f control. TI Motor control DSP and Xilinx CPLD/FPGA are used for generation of the PWM signals for the schemes. The inverters are switched at around 1.25 kHz to keep the switching losses low. Due to laboratory constraints, the experimental verification is done on low power prototypes. Nonetheless, the generality of the schemes allow them to be used for medium voltage high power applications.

In this thesis the design, control, stability, input power quality, and motor drive performance of ac motor drives with front end three phase diode rectifiers utilizing low capacitance dc bus capacitor are investigated. Detailed computer simulations of conventional motor drives with diode rectifier front end utilizing high capacitance dc bus capacitor and the drives with low capacitance dc bus capacitor are conducted and the performances are compared. Performance evaluation of various active control methods found in previous studies aiming to provide the dc bus stability of drives with low capacitance dc bus capacitor are done at various load levels and types. Design recommendations are provided for the drives utilizing low capacitance dc bus capacitor.

No description available.

A robust servo control system based on Integral Variable Structure Model Following Control (IVSMFC) is proposed. The IVSMFC approach comprises a reference model part for specifying the design requirements and an Integral Variable Structure Control (IVSC) part for minimizing the errors between the plant and the model. Sliding mode thus obtained features robustness against external disturbances and parameter variations. Design procedures in both continuous-time and discrete-time have been detailed. The IVSMFC-based servo control system has been successfully applied to a DSP-based brushless DC motor drive for globoidal cam indexing system and to power system. Simulation and experimental results demonstrate that the proposed scheme can achieve fast and robust responses.

Este trabalho apresenta o estudo comparativo do desempenho de três topologias de conversores do sistema monofásico para o sistema trifásico com número reduzido de componentes, para o acionamento de um motor de indução do tipo rotor gaiola de esquilo. O funcionamento de cada topologia é descrito e simulado digitalmente. O desempenho desses conversores é avaliado em diferentes modos de operação, com sequência de fase positiva ou negativa, com ênfase na qualidade de energia em termos de redução da distorção harmônica total e da melhoria do fator de potência na fonte. Com vistas à redução de custos, foi desenvolvido um protótipo experimental baseado no uso de módulo integrado de chaves semicondutoras de potência e de um microcontrolador de baixo custo. Os resultados experimentais se equiparam aos resultados obtidos por simulação. / This work presents the comparative performance of three topologies of single-phase to three-phase converters with reduced number of components while driving an induction motor of type squirrel-cage. The operation of each topology is described by means of simulation results. The performance of these converters is evaluated in different modes of operation, according to the positive or negative sequence, with an emphasis on power quality in terms of reduced total harmonic distortion and improved power factor at the input source. With a viewpoint for achieving reduced costs, an experimental prototype has been developed, based on the use of integrated module of power semiconductor switches and a cheap microcontroller. Experimental results comparable to those obtained by simulations are obtained.

Este trabalho apresenta o estudo comparativo do desempenho de três topologias de conversores do sistema monofásico para o sistema trifásico com número reduzido de componentes, para o acionamento de um motor de indução do tipo rotor gaiola de esquilo. O funcionamento de cada topologia é descrito e simulado digitalmente. O desempenho desses conversores é avaliado em diferentes modos de operação, com sequência de fase positiva ou negativa, com ênfase na qualidade de energia em termos de redução da distorção harmônica total e da melhoria do fator de potência na fonte. Com vistas à redução de custos, foi desenvolvido um protótipo experimental baseado no uso de módulo integrado de chaves semicondutoras de potência e de um microcontrolador de baixo custo. Os resultados experimentais se equiparam aos resultados obtidos por simulação. / This work presents the comparative performance of three topologies of single-phase to three-phase converters with reduced number of components while driving an induction motor of type squirrel-cage. The operation of each topology is described by means of simulation results. The performance of these converters is evaluated in different modes of operation, according to the positive or negative sequence, with an emphasis on power quality in terms of reduced total harmonic distortion and improved power factor at the input source. With a viewpoint for achieving reduced costs, an experimental prototype has been developed, based on the use of integrated module of power semiconductor switches and a cheap microcontroller. Experimental results comparable to those obtained by simulations are obtained.

A split-phase induction motor (SPIM) is obtained by splitting each of the three-phase stator windings of an induction motor into two equal halves. This results in two sets of three-phase windings with a spatial angle difference of 30◦ (electrical) between them. The two sets of windings are fed from two different voltage-source inverters for speed control of the split-phase motor drive. Low dc bus voltage requirement and improved torque profile are some of the advantages of the split-phase motor, compared to the normal three-phase induction motor. A pulse width modulation (PWM) technique is used to produce the gating signals for the power semiconductor devices in the two inverters. The PWM technique can either be a carrier comparison (CC) based method or a space-vector (SV) based scheme. The carrier based PWM methods employ six modulating waves, which are compared against a common triangular carrier to generate the gating pulses. In space-vector based PWM schemes, the voltage reference is specified in terms of a rotating reference vector. In each subcycle, a set of voltage vectors are applied for appropriate durations of time to produce an average vector equal to the reference vector. Unlike three-phase induction motor drives, where the voltage vectors are two dimensional, the voltage vectors in the case of SPIM drive are four dimensional. This thesis presents a detailed survey on carrier-comparison based and space-vector based PWM techniques for the SPIM drive. In this thesis, sine-triangle PWM (STPWM) is analyzed from a space-vector perspective. The set of voltage vectors applied and the sequence of application of the voltage vectors in each half-carrier cycle are studied. The analysis shows that the set of voltage vectors and the switching sequence employed by STPWM are different from those used by the well known SVPWM tech-niques. Two other CC based PWM techniques, based on common mode injection, are considered for the SPIM drive. In one method, the common-mode signal is derived from all the six modulating signals, and is the same for both the inverters. In the second method, the common-mode signal is different for the two inverters; each common-mode signal is derived from the three-phase sinusoidal signals of the respective inverter. The study shows that the latter method has the highest dc bus utilization and results in the lowest total harmonic distortion (THD) among the CC PWM techniques. An experimental comparison of the three carrier-comparison techniques with three well known space-vector PWM techniques is presented. Total harmonic distortion (THD) of the line current is measured at different modulation indices for all six techniques. The experimental results are obtained from a 6kW, 200V, 50Hz split-phase induction motor drive, with constant V /F ratio. The PWM techniques are implemented using an ALTERA cyclone II field programmable gate array (FPGA) digital controller. One of the SV techniques, termed here as 4-dimensional 24-sector (4D24SEC) PWM is found to be the best in terms of line current THD among all the CC and SV based PWM techniques considered. However, compared to any carrier-based technique, implementation of the 4D24SEC PWM based on the space vector approach is found to be resource intensive. Hence, an equivalent carrier-based implementation of 4D24SEC PWM is proposed in this thesis. The feasibility of the proposed approach is verified experimentally, and is found to be consuming much less logical resources than the space-vector implementation (i.e. 4102 logical elements for the CC approach as against 33,655 logical elements for the SV approach). A new space-vector PWM technique is also proposed in the thesis. This technique utilizes a new set of voltage vectors and a new switching sequence, which are motivated by the analyses of the carrier-based methods, presented earlier. The proposed technique is implemented, and is compared with other space-vector and carrier-based methods at different modulation indices and switching frequencies. The proposed PWM technique is found to have the same dc-bus utilization as the existing 4-dimensional SV based PWM techniques. The performance of the proposed method is found to be not better than existing 4-dimensional SV PWM methods. The possibilities for new switching sequence is being explored here.

No description available.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.

Baigiamajame darbe sudarytas uždarosios asinchroninės bejutiklės vektoriškai valdomos pavaros imitacinis modelis ir ištirtos charakteristikos. Teorinėje darbo dalyje yra aptariami asinchroninių elektros pavarų privalumai bei šiose pavarose naudojami greičio jutikliai. Aprašomi stebiklių privalumai bei trūkumai, pagrindžiamas jų naudojimas asinchroninėse pavarose. Nagrinėjami bejutiklių elektros pavarų ypatumai, aprašomi vektorinio valdymo bendrieji principai bei aprašomi bejutiklėse vektoriškai valdomose pavarose naudojamų stebiklių modeliai. Pateikiami du skirtingi asinchroninių variklių matematiniai modeliai. Tiriamojoje dalyje parenkamas asinchroninio variklio modelis, tiriant abiejų imitacinių modelių dinamines greičio charakteristikas. Sudaromas stebiklio imitacinis modelis. Tiriamos stebiklio greičio dinaminės charakteristikos, sudaroma uždaroji greičio reguliavimo sistema su stebikliu. Analizuojamos uždarosios greičio reguliavimo sistemos greičio charakteristikos be apkrovos, su šuoline apkrova ir harmoniškai kintančia apkrova. Nagrinėjama sistemos stiprinimo koeficiento įtaka uždarosios greičio reguliavimo sistemos greičio charakteristikų pereinamiesiams procesams. Magistro darbas baigiamas tyrimo išvadomis, kuriose aptariamas darbo rezultatų realaus pritaikymo galimybės. Darbą sudaro 8 dalys: įvadas, žymėjimai, literatūros šaltinių analizė, tyrimo tikslas ir uždaviniai, teorinė dalis, tiriamoji dalis išvados ir pasiūlymai, literatūros šaltiniai. / The final master degree thesis presents sensorless vector controlled induction motor drive simulation model and characteristics. In the analytic part of master thesis advantages of induction motor drives and speed sensors are described. Advantages and disadvantages of speed estimators are presented and purpose of using them are proved. Peculiarities of sensorless motor drives, principles of vector control and models of speed estimators are analyzed. Two simulation models of induction motor are proposed. In the research part characteristics of induction motors are compared and motor model is chosen. Characteristics of open loop induction motor drive are investigated and simulation model of closed loop induction motor drive with speed estimator is designed. Characteristics of closed loop control system at no load, constant load and harmonic load are analyzed and influence of speed controller gain is considered. Thesis is closed with conclusions about designed system application in real projects. Structure: introduction, list of symbols, literature review, the study aims and objectives, the theoretical part, research part, conclusions and proposals, references.