Les convertisseurs d'électronique de puissance sont de plus en plus exploités notamment dans les applications nécessitant la variation de vitesse de machines. L'utilisation de composants plus performants et plus puissants couplés à de nouvelles structures multiniveaux autorise l'accès à de nouveaux champs applicatifs, ou des fonctionnements à plus haut rendement. Ces convertisseurs statiques sont capables de gérer, par un pilotage adapté, les transferts d'énergie entre différentes sources et différents récepteurs selon la famille de convertisseur utilisée. Au sein de l'interface de pilotage, un schéma particulier permet de générer des signaux de commande pour les interrupteurs, il s'agit de la modulation et peut être vue par deux approches différentes : L'approche intersective issue d'une comparaison modulante-horteuse (appelée en anglais carrier based PWM) et l'approche vectorielle où les signaux de pilotage des trois bras de ponts sont considérés comme un vecteur global unique (appelée Modulation Vectorielle SVM). Le but de la MLI est de générer une valeur moyenne de la tension la plus proche possible du signal modulé. La commande usuelle par comparaison modulante-porteuse dans le cas des architectures multiniveaux nécessite autant de porteuses triangulaires qu'il y a de cellules à commander au sein d'un bras. Plus généralement, la stratégie de modulation de chacune des topologies multiniveaux est choisie en se basant sur des critères à optimiser liés à la qualité les formes d'ondes produites ou obtenues, suite à la conversion. Le choix de la variable de commande à implémenter dans le schéma MLI fait appel à l'expertise de l'expérimentateur et se réfère peu au modèle mathématique initial qui peut-être établit pour caractériser le fonctionnement de l'architecture d'électronique de puissance. En ce qui concerne les stratégies vectorielles SVM, une absence de modèle compatible avec les modèles, basés sur une comparaison modulante porteuse, d'onduleurs est constatée. Les types d'onduleurs triphasés à deux ou à N niveaux de tension admettent un modèle sous forme d'équations d'un système linéaire compatible qui s'écrit sous la forme V = f(a) dans le cas d'une MLI sinusoïdale et V = f(1) dans le cas d'une SVM, avec V les tensions de phase, a les rapports cycliques et f les instants de commutation. Dans cette configuration basique il est constaté que la matrice liant ces tensions aux rapports cycliques (ou aux instants de commutation) n'admet pas d'inverse, ce qui revient à dire qu'il n'est pas possible, avec les théories usuelles des fonctions linéaires, de résoudre ce système afin d'exprimer les rapports cycliques (ou les instants de commutation) en fonction des tensions de références. C'est ce qui explique qu'aujourd'hui un bon nombre d'implémentations pratiques de modulation se fait, suite à une analyse expérimentale des conséquences d'un choix de stratégie sur les variables d'intérêt. / The power electronic converters are increasingly exploited in particular in applications requiring variable speed machines. The use of more effcient and more powerful components coupled with new multilevel structures widens the fields of application and allows high efficiency functioning. These converters are able to manage, with a suitable control, the energy transfer between different sources and different receivers depending on the used converter family. In the control interface, a particular pattern is used to generate control signais for the switches, it is the modulation. Generally, the modulation strategy takes two forms : a Modulation based on comparaison modulating - caiTier (Carrier based Pulse Width Modulation, (CPWM)) or a Vector Modulation (SVM). The purpose of the PWM is to generate a signal which has a mean value as nearest as possible to the desired sinusoidal signal. The usual control by PWM, in the case of multi-level architectures, requires as many triangular carriers as there are cells to be controlled within an arm. The modulation strategy selection for each multilevel topology is based on optimizing criterias related to the quality of the produced waveforms after the conversion. The choice of the variable to implement in the PWM scheme requires expertise of the experimenter and refers little to the initial mathematical model that can be established to characterize the operation of the power electronics architecture. Concerning the vector strategies SVM, the lack of a compatible model with PWM inverters is observed. The three-phase inverters with two or N voltage levels can be modeled in the form of equations of a compatible linear system that is written as V= f(a) in the case of a sinusoïdal PWM and V= f(1) in the case of SVM, with V represents phase voltages, ais a duty cycle and fthe switching instants. In this basic configuration, it is found that the matrix linking these voltages duty cycles (or switching times) adrnits no inverse, which means that it is not possible with the usuallinear functions theories to solve this system in order to express the duty ratios (or the instants of switching) as a function of the reference voltages. This is the reason that today a number of practical implementations of modulation is done after experimental analysis of the consequences of strategy choices on the variables of interest. This study proposes the development of a generic formulation for the modeling of voltage inverters and especially multilevel inverters. The development of generic models for the implementation of modulation strategies is illustrated. The extension of the average model to the three-phase systems is performed to the usual structures of N levels such as the floating capacity and H bridge inverters. The idea is to generalize the model to the multi-level architectures, whether by the sinusoidal PWM modulation expressing the alpha as an output variable, or by the SVM expressing tau. This thesis aims to define a modeling approach and mathematically express the set of solutions in order to generate modulation strategies for various architectures of inverters studied. This will be done using a tool for solving linear systems. This resolution is based on finding degrees of freedom, to be identified at first, then express them in a second step by establishing the link with the criteria to optimize for given architectures. Two examples of application have been implemented on conventional two levels of voltage inverters and the thtree levels flying capacitor voltage inverter.

Dans nos travaux, nous nous intéressons à la commande des convertisseurs statiques à grand nombre d'interrupteurs. Le développement des topologies multi-niveaux multi-bras a ouvert l'accès aux domaines de la forte puissance et de la haute qualité harmonique. Outre cette montée en puissance, la commande spéciale de ces dispositifs permet de conférer au convertisseur des fonctionnalités avancées de plus en plus nécessaires, comme la possibilité de filtrage actif des harmoniques, la tolérance aux pannes, la gestion du réactif, les liaisons HVDC, etc. Toutefois, un plus grand nombre d'interrupteurs au sein d'une même structure de conversion se traduit par une forte croissance du nombre de variables de commande, des degrés de liberté et par une explosion combinatoire du nombre de configurations possibles. La synthèse de lois de commande suivant les approches traditionnellement conçues pour les topologies classiques, comme les méthodes de modulation vectorielle fondées sur la représentation géométrique du convertisseur, en devient rapidement fastidieuse pour les nouvelles topologies plus complexes. De plus, les interrupteurs présents en surnombre apportent des redondances fortes qui ne sont pas nécessairement exploitées, ou du moins arbitrairement. Nous proposons une nouvelle approche de commande qui se veut moins dépendante du nombre d'interrupteurs, et qui s'affranchit des limitations induites par les méthodes de modulation géométrique. Notre approche consiste dans un premier temps à formuler de manière algébrique des problèmes de commande qui sont généralement sous-déterminés, témoignant de la présence de redondances ou degrés de liberté, et contraints, car tenant compte des limitations propres aux rapports cycliques. De manière intéressante, ces problèmes offrent une similarité avec les problèmes dits d'allocation de commande rencontrés en aéronautique, en marine ou en robotique. Dans un second temps, dans le but de fournir à chaque période de découpage une solution de commande unique et optimisée, nous concevons de nouvelles méthodes d'allocation pour les convertisseurs statiques fondées sur l'optimisation numérique en ligne à partir de techniques d'optimisation linéaire. En conséquence, les rapports cycliques sont automatiquement optimisés pour satisfaire aux références de tension tout en respectant les saturations et en exploitant les redondances disponibles selon l'état actuel du convertisseur. Nous mettons en lumière les propriétés naturellement offertes par nos méthodes. Notamment, toutes nos solutions de modulation étendent de manière maximale la zone de linéarité du convertisseur. Nous proposons des méthodes d'allocation pour la commande en tension ou en courant de topologies variées : l'onduleur quatre bras deux niveaux, l'onduleur multicellulaire à condensateurs flottants, l'onduleur modulaire multi-niveaux. Concernant les convertisseurs multicellulaires, nos méthodes d'allocation utilisent automatiquement les degrés de liberté disponible pour fournir un équilibrage actif très rapide des tensions de condensateurs flottants. Aussi, grâce à la formulation algébrique des contraintes de commande, nos algorithmes peuvent prendre en compte un défaut sur un interrupteur pour conférer au convertisseur une propriété de tolérance aux fautes du point de vue de la commande. / In our works, we are interested in control of high-switch-count power converters. The development of multileg, multilevel converters has opened the access to high power and high harmonic quality. The special control of these devices brings to the converter advanced abilities that are more and more requested nowadays, like active harmonic filtering, fault tolerance, active and reactive power transfer, High Voltage Direct Current (HVDC) links, etc. However, a higher number of switches in a conversion structure leads to a higher number of control variables, as well as more redundancies and a combinatorial explosion of the number of possible configurations. The development of control laws resulting from approaches traditionally designed for classical topologies, as for space vector modulation methods, becomes harder for new, much complex topologies. Moreover, the too many available switches bring strong control redundancies that are not necessarily exploited, at least arbitrarily. We propose a new control approach that is expected to be less dependent on the number of switches, and that does not suffer from limitations proper to geometrical modulation methods. Firstly, our approach consists in the algebraic formulation of control problems that are generally under-determined, highlighting the presence of redundancies and degrees of freedom, and constrained, because control limitations are taken into account. Interestingly, a connection can be highlighted to the so-called control allocation problem in flight control, robotics, or marine applications. Secondly, in order to compute a unique and optimized control solution at each switching period, we develop new control allocation methods for power converters based on on-line numerical optimization using linear programming techniques. Consequently, duty cycles are automatically optimized to satisfy voltage references while respecting saturations and exploiting available redundancies depending on the state of the converter. We highlight the properties naturally offered by our methods. In particular, all modulation solutions yield a maximized extension of the linearity range of the converter. We propose control allocation methods for the voltage or current control of many topologies: the four-leg two-level inverter, the multicellular flying capacitor inverter, the modular multilevel inverter.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

Submitted by Gilvanedja Silva (gilvanedja@biblioteca.ufpb.br) on 2018-03-22T20:42:08Z No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) / Made available in DSpace on 2018-03-22T20:42:09Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) Previous issue date: 2017-05-25 / This work presents a technique using carrier-based pulse width modulation (PWM) applied to single-phase asymmetrical multilevel inverters with diodes clamped, aiming to increase the amount of output voltage levels to improve signal quality, reducing the total harmonic distortion rate (THD). The technique was used in inverters of three, four and five levels per arm, providing an output signal with seven, thirteen and nineteen levels respectively, presenting two, six and ten levels higher than the equivalent symmetrical multilevel inverters. The technique was described with a set of equations and procedures that can be generalized for inverters of any number of levels. To verify the operation, simulations were performed using the PSIM program and an experimental assembly of an asymmetrical multilevel inverter of three levels was performed, using a field programmable gate array device (FPGA) in the implementation of the PWM modulator. Finally, the simulation and experimental results that prove the effectiveness of the modulation strategy employed in this work are presented and compared / Este trabalho apresenta uma técnica utilizando a modulação por largura de pulso (PWM) baseada em portadora, aplicada aos inversores multiníveis monofásicos assimétricos com diodos de grampeamento, com o objetivo de elevar a quantidade de níveis na tensão de saída, para melhorar a qualidade do sinal, reduzindo a taxa de distorção harmônica total (THD). A técnica foi empregada em inversores de três, quatro e cinco níveis por braço, fornecendo um sinal de saída com sete, treze e dezenove níveis respectivamente, apresentando dois, seis e dez níveis a mais que os inversores multiníveis simétricos equivalentes. A técnica foi descrita com um conjunto de equações e procedimentos que pode ser generalizada para inversores de qualquer número de níveis. Para comprovar o funcionamento, foram realizadas simulações utilizando o programa PSIM e efetuada montagem experimental de uma inversor multinível assimétrico de três níveis, utilizando na implementação do modulador PWM um dispositivo em matriz de porta programável em campo (FPGA). Por fim, são apresentados e comparados os resultados de simulações e experimentais que comprovam a eficácia da estratégia de modulação empregada neste trabalho

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

<p dir="ltr">The short lifespan of capacitors in power electronics converters is a significant challenge. These capacitors, often electrolytic, are vital for voltage smoothing and frequency filtering. However, their susceptibility to heat, ripple current, and aging can lead to premature faults. This can cause issues like output voltage instability and short circuits, ultimately resulting in catastrophic failure and system shutdown. Capacitors are responsible for 30% of power electronics failures.</p><p dir="ltr">To tackle this challenge, scientists, researchers, and engineers are exploring various approaches detailed in technical literature. These include exploring alternative capacitor technologies, implementing active and passive cooling solutions, and developing advanced monitoring techniques to predict and prevent failures. However, these solutions often come with drawbacks such as increased complexity, reduced efficiency, or higher upfront costs. Additionally, research in material science is ongoing to develop corrosion-resistant capacitors, but such devices are not readily available.</p><p dir="ltr">This dissertation presents a capacitorless solution for dc-dc and dc-ac converters. The proposed solution involves harnessing parasitic elements and integrating them as intrinsic components in power converter technology. This approach holds the promise of enhancing power electronics reliability ratings, thereby facilitating breakthroughs in electric vehicles, compact power processing units, and renewable energy systems. The central scientific premise of this proposal is that the capacitance requirement in a power converter can be met by deliberately augmenting parasitic components.</p><p dir="ltr">Our research hypothesis that incorporating high dielectric material-based thin-films, fabricated using nanotechnology, into planar magnetics will enable the development of a family of capacitorless electronic converters that do not rely on discrete capacitors. This innovative approach represents a departure from the traditional power converter schemes employed in industry.</p><p dir="ltr">The first family of converters introduces a novel capacitorless solid-state power filter (SSPF) for single-phase dc-ac converters. The proposed configuration, comprising a planar transformer and an H-bridge converter operating at high frequency, generates sinusoidal ac voltage without relying on capacitors. Another innovative dc-ac inverter design is the twelve step six-level inverter, which does not incorporate capacitors in its structure.</p><p dir="ltr">The second family of capacitorless topologies consists of non-isolated dc-dc converters, namely the buck converter and the buck-boost converter. These converters utilize alternative materials with high dielectric constants, such as calcium copper titanate (CCTO), to intentionally enhance specific parasitic components, notably inter capacitance. This innovative approach reduces reliance on external discrete capacitors and facilitates the development of highly reliable converters.</p><p dir="ltr">The study also includes detailed discussions on the necessary design specifications for these parasitic capacitors. Furthermore, comprehensive finite element analysis solutions and detailed circuit models are provided. A design example is presented to demonstrate the practical application of the proposed concept in electric vehicle (EV) low voltage side dc-dc power converters used to supply EVs low voltage loads.</p>