The purpose of this Master Thesis is to analyze what suitable hardware platforms there are on the market in order to build a low price control and information system for mobile applications, called small display module. The thesis will be underlying material for making a decision for further development. The result of the thesis consists mainly of a Windows CE kernel and a schematic for a CPU card, on which it would be suitable to build the display module. Another major part of the report is the introduction of different techniques that could be of interest when designing a processor based system. The processor architecture that was chosen is the x86. This is mainly due to CPU availability, but as well as the fact that existing software can be used on the display module without any significant modifications. Many interesting processors were sorted out because they hade a very high price on the development kits from the manufacturer and because the possible production volume can not manage this cost. The development kit makes the development easier and can be used for performance tests before prototypes are built.

This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.

The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.

No description available.

RISC-V is an open-source instruction set that has been gaining popularity in recent years, and, with support from large chip manufacturers like Intel and the benefits of its open-source nature, RISC-V devices are likely to continue gaining momentum. Many courses in a computer science program involve development on an embedded device. Usually, this device is of the ARM architecture, like a Raspberry Pi. With the increasing use of RISC-V, it may be beneficial to use a RISC-V embedded device in one of these classroom environments. This research intends to assist development on the SiFive HiFive1 RevB, which is a RISC-V embedded device. This device was chosen because of its ease of use, functionality-rich API, and affordability. In order to make developing with this board very approachable for a student, this research involved the development of a small suite of tools. These tools support common functionality like: building a source file into an executable ELF file, converting that ELF executable into an Intel HEX executable format that is required to run on the device, uploading the Intel HEX executable onto the device, and attaching a debug session to the program that is running on the device. With the help of this toolchain, developing on this RISC-V embedded device should be very approachable for most students.

The aim of this thesis is the development and implementation of a controlled testing platform for the Robust Intelligent Sensing and Controls (RISC) Lab at Utah State University (USU). This will be an open source adaptable expandable robotics platform usable for both education and research. This differs from the many other platforms developed in that the entire platform software will be made open source. This open source software will encourage collaboration among other universities and enable researchers to essentially pick up where others have left off without the necessity of replicating months or even years of work. The expected results of this research will create a foundation for diverse robotics investigation at USU as well as enable attempts at novel methods of control, estimation and optimization. This will also contribute a complete software testbed setup to the already vibrant robotics open source research community. This thesis first outlines the platform setup and novel developments therein. The second stage provides an example of how this has been used in education, providing an example curriculum implementing modern control techniques. The third section provides some exploratory research in trajectory control and state estimation of the tip of an inverted pendulum atop a small unmanned aerial vehicle as well as bearing-only cooperative localization experimentation. Finally, a conclusion and future work is discussed.

RISC-V is an open-source instruction-set architecture (ISA) forming the basis of thousands of commercial and experimental microprocessors. The Scalar Cryptography extension ratified in December 2021 added scalar instructions that target common hashing and encryption algorithms, including SHA2 and AES. The next step forward for the RISC-V ISA in the field of cryptography and digital security is the development of vector cryptography instructions. This thesis examines if it is viable to add vector implementations of existing RISC-V scalar cryptography instructions to the existing vector instruction format, and what improvements they can make to the execution of SHA2 and AES algorithms. Vector cryptography instructions vaeses, vaesesm, vaesds, vaesdsm, vsha256sch, and vsha256hash are proposed to optimize AES encryption and decryption, SHA256 message scheduling, and SHA256 hash rounds, with pseudocode, assembly examples, and a full 32-bit instruction format for each. Both algorithms stand to benefit greatly from vector instructions in reduction of computation time, code length, and instruction memory utilization due to large operand sizes and frequently repeated functions. As a proof of concept for the vector cryptography operations proposed, a full vector-based AES-128 encryption and SHA256 message schedule generation are performed on the 32-bit RISC-V Ibex processor and 128-bit Vicuna Vector Coprocessor in the Vivado simulation environment. Not counting stores or loads for fair comparison, the new Vector Cryptography extension completes a full encryption round in a single instruction compared to sixteen with the scalar extension, and can generate eight SHA256 message schedule double-words in a single instruction compared to the forty necessary on the scalar extension. These represent a 93.75% and 97.5% reduction in required instructions and memory for these functions respectively, at a hardware cost of 19.4% more LUTs and 1.44% more flip-flops on the edited Vicuna processor compared to the original.

Chez la plupart des eucaryotes, la présence d’ARN double brin induit la mise en place de mécanismes qui peuvent inhiber l’expression de gènes sur la base d’une complémentarité de séquence. L’exemple le mieux connu est le cas de l’interférence par l’ARN telle qu’elle a été décrite initialement chez C. elegans, où les ARN double brin génèrent une endonucléase spécifique de séquence qui dégrade tout ARN parfaitement complémentaire du petit ARN guide contenu dans le complexe RISC. En plus de cette activité post-transcriptionnelle, il a été observé chez de nombreux eucaryotes l’existence de mécanismes apparentés à l’interférence par l’ARN et qui inhibent la transcription en agissant au niveau de la chromatine. Si ces mécanismes ont été clairement mis en évidence chez les plantes et les champignons il n’existe que quelques exemples de ce type de régulation chez les mammifères. De manière inattendue, le fait de cibler le promoteur d’un gène avec de petits ARN double brin peut conduire à une augmentation de son expression. Cette réponse paradoxale n’a été observée jusqu’à présent que dans des cellules de mammifère, et si elle suscite un intérêt en particulier pour stimuler l’expression de gènes suppresseurs de tumeurs, son mécanisme est encore inconnu.Mes travaux ont porté sur l’étude de l’induction de l’expression par des petits ARN. Ils reposent tout d’abord sur le développement d’une approche expérimentale qui permet de suivre l’activité du promoteur du gène ciblé. Pour cela, j’ai utilisé des constructions indicatrices organisées autour d’un promoteur bidirectionnel qui contrôle l’expression de deux protéines fluorescentes. Lorsque l’on cible le messager de l’une de ces protéines, l’expression de l’autre est augmentée et j’ai pu montrer que ceci corrèle avec la quantité d’ARN messager et de polymérase II présente sur le promoteur bidirectionnel. Ainsi, l’utilisation d’un promoteur bidirectionnel permet effectivement de suivre le niveau de transcription du gène ciblé par le petit ARN.Cette induction de l’expression détectée de manière « controlatérale » n’est pas due à un effet hors cible des petits ARN car elle nécessite la présence de la séquence cible sur l’un des transcrits de la construction indicatrice. L’induction peut être observée avec de nombreux petits ARN différents, y compris s’ils interagissent comme des micro ARN. Les constructions indicatrices que j’ai développées sont donc biaisées en faveur d’une réponse de type induction transcriptionnelle enréponse à un silencing. L’utilisation d’un promoteur bidirectionnel est probablement à l’origine de ce biais à travers la possibilité d’induire une transcription convergente sur les plasmides lorsqu’ils sont circulaires. De fait, la linéarisation de la construction indicatrice supprime l’induction, du moins pour les constructions les plus simples.Si le coeur du complexe RISC, la protéine Ago2, est nécessaire au silencing et à l’induction, j’ai pu montrer que dans le deuxième cas c’était en fait pour guider le complexe RISC sur les transcrits et non pas pour les couper. En effet, le silencing des protéines TNRC6A et B diminue fortement l’induction sans toucher au silencing s’il procède en mode siRNA. De plus l’ancrage sur le transcrit EGFP induit une réponse de même type que le petit ARN (silencing et induction). Cette approche d’ancrage m’a permis d’identifier les domaines nécessaires au silencing et à l’induction et de montrer qu’ils sont distincts.Ce travail permet donc de mettre en évidence que l’induction transcriptionnelle observée sur nos constructions indicatrices est due à une activité des partenaires des protéines Argonaute, la famille GW182/TNRC6. Cette observation ouvre la voie à une caractérisation du mécanisme de cette induction en montrant qu’elle relève d’une activité spécifique du complexe RISC. / In the majority of the eucaryote, the presence of double-strands RNA induce the inhibition of gene expression base on the complementary of sequence. The best known example is the case of RNA interference in C. elegans which is the first model described, in which the double-strands RNA generate an specific endonuclease who degrade all RNA complementary perfectly to the small RNA guide included in the complex RISC. In addition to this post-transcriptional activity, it has been observed in many eukaryotes the existence of mechanisms related to RNA interference and it inhibit transcription by acting at the chromatin. If these mechanisms have been clearly demonstrated in plants, fungi, there are only several examples of this type of regulation in mammals. Unexpectedly, the targeting the promoter of a gene with small double-stranded RNA can lead to increased expression. This paradoxical response has not been observed so far in mammalian cells, but it raises interest particularly to stimulate the expression of tumor suppressor genes, unfortunely the mechanism is still unknown.My work has focused on studying the induction of expression by small RNAs. They are based first on the development of an experimental approach that allows to monitor the promoter activity of the targeted gene. To do this I used indicator constructions organized around a bidirectional promoter that controls the expression of two fluorescent proteins. When targeting the messenger of one of these proteins, the expression of the other is increased and I was able to show that thisincrease correlates with the amount of RNA messenger polymerase II presented on the bidirectional promoter. Thus, the use of a bidirectional promoter can effectively monitor the level of transcription of the gene targeted by the small RNA. This induction of expression detected in a "contralateral" is not due to an off-target effect of siRNA because it requires the presence of the target sequence on one of the transcripts of the construction indicator. The induction can be observed with many different small RNAs, including the interact as micro RNA. Thus the construction indicator that I developed are biased in an induction response transcriptionally in response to a silencing. The use of a bidirectional promoter is probably the origin of this bias through the possibility of inducing a convergent transcription when the plasmids are circular. In fact, the linearization of the construction indicator removes the induction, at least for the simplest constructions. If the heart of the complex RISC is the protein Ago2, is necessary for the silencing and the induction, I was able to show that in the second case Ago2 was in fact to guide the RISC complex on the transcripts but not to cut it. Indeed, the silencing of proteins TNRC6A and B reduces induction significantly without affecting the silencing if it processe in the siRNA model. Also anchoring the transcript EGFP induces a response similar to the small RNA (silencing and induction). This anchor approach allowed me to identify domaines necessary for silencing and induction and show that they are distinct. This work makes it possible to demonstrate that the transcriptional induction observed in our constructions indicator is due to a activity partner ofArgonaute proteins, the GW182/TNRC6 family. This observation open the way for characterization of the mechanism of this induction by showing that it belongs to a specific activity of the RISC complex.

The Task Scheduling Paradigm is a general technique for leveraging fine and coarse grain parallelism from applications of several domains with minimum impact on code readability, relying on the automatic inference of data dependencies among tasks. The performance of Task Parallel applications is correlated with the speed at which the underlying Task Scheduling System is able to detect such dependencies, something that is critical for fine-granularity workloads, which cannot amortize scheduling overheads with long periods of useful computation. That being the case, several groups have recently been developing FPGA-accelerated Task Scheduling Systems architectures where a software Task Scheduling Runtime is able to offload its bookkeeping computations to an FPGA-based accelerator with the goal of efficiently scheduling fine-grained tasks to CPU cores. Even though these FPGA-accelerated systems offer substantial gains over the software-only baseline, it is also true that FPGA-CPU communication bottlenecks prevent such designs from handling scenarios with either large number of cores or very fine-grained tasks. With that in mind, we proposed the implementation of a Native Task Scheduling System that is, a processor with native support for task scheduling embedded into its architecture with the goal of substantially reducing these overheads. More specifically, this project aimed at embedding the HW logic of Picos, a mature Task Scheduling Accelerator developed by the Barcelona Supercomputing Center (BSC), into Rocket Chip, an open-source, silicon-proven, multi-core implementation of RISC-V. The ISA of the resulting system provides special instructions for Task Applications to interact with this Task Scheduling Logic, ruling out all FPGA-CPU communication latencies. To evaluate the prototype performance, we both (1) adapted Nanos, a mature Task Scheduling runtime, to benefit from the new task-scheduling-accelerating instructions; and (2) developed Phentos, a new HW-accelerated light weight Task Scheduling runtime. Our experiments show that task parallel programs using Nanos-RV the Nanos version ported to our system are on average 2.13 times faster than those being serviced by baseline Nanos, while programs running on Phentos are 13.19 times faster, considering geometric means. Using eight cores, Nanos-RV is able to deliver speedups with respect to serial execution of up to 5.62 times, while Phentos produces speedups of up to 5.72 times. / Paralelismo por Tarefas é uma técnica genérica de extração de paralelismo de granularidade arbitrária aplicável a programas de vários domínios, com mínimo impacto sobre legibilidade de código, baseada na inferência automática de dependências de dados entre tarefas. O desempenho de aplicações paralelas baseadas nesse paradigma depende da velocidade com a qual o runtime de Paralelismo por Tarefas que lhe dá suporte é capaz de detectar tais dependências, fato que é ainda mais crítico para aplicações envolvendo tarefas de granularidade fina, já que nesse cenário o overhead de escalonamento não é amortizado por períodos significativamente maiores de computação útil. Recentemente, diversos grupos têm desenvolvido Sistemas de Suporte a Paralelismo por Tarefas acelerados por FPGAs, os quais são capazes de fazer offload das operações de inferência de dependências para um acelerador em FPGA de modo a melhorar o seu desempenho ao lidar com tarefas de granularidade fina. Por outro lado, ainda que esses sistemas acelerados por FPGA apresentem ganhos substanciais com relação às alternativas baseadas puramente em software, o desempenho dessas soluções é prejudicado por gargalos de comunicação entre a CPU e a FPGA, os quais limitam a capacidade desses sistemas de lidar com cenários envolvendo grande número de núcleos ou tarefas muito finas. Motivados por isso, implementamos um Sistema de Suporte Nativo a Paralelismo por Tarefas isto é, um processador com suporte arquitetural nativo a Paralelismo por Tarefas com o objetivo de reduzir consideravelmente tais overheads de comunicação. Mais especificamente, integramos a lógica em hardware do Picos, um acelerador de Paralelismo por Tarefas desenvolvido pelo Barcelona Supercomputing Center (BSC), ao Rocket Chip, uma implementação multi-core de código livre do RISC-V desenvolvida pela Universidade da Califórnia, Berkeley. O sistema resultante contém em sua ISA (Instruction Set Architecture) as instruções necessárias para que aplicações baseadas em tarefas possam interagir diretamente com essa lógica de escalonamento, minimizando os overheads associados ao uso de runtimes intermediários e eliminando toda a latência de comunicação FPGA-CPU. Para avaliar a performance do protótipo que então se construiu, nós tanto (1) adaptamos o runtime de escalonamento de tarefas Nanos para que ele pudesse ser acelerado pelas novas instruções de escalonamento de tarefas, quanto (2) criamos um novo runtime leve de escalonamento de tarefas a que demos o nome de Phentos. Nossos experimentos mostram que programas baseados em paralelismo por tarefas usando o runtime Nanos-RV a versão do runtime Nanos com suporte ao sistema que produzimos são executados em média 2,13 vezes mais rapidamente do que versões dos mesmos programas utilizando a versão básica do Nanos, enquanto programas executados com o Phentos são em média 13,19 vezes mais rápidos do que suas versões correspondentes baseadas na mesma versão básica do Nanos. Tais valores médios correspondem à média geométrica dos conjuntos de dados pertinentes. Usando oito núcleos, Nanos-RV entrega ganhos de desempenho com relação a execuções seriais de até 5,62 vezes, enquanto Phentos entrega ganhos de até 5,72 vezes.

Thesis--Technische Universität Hannover. / Includes bibliographical references.