Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um registrador constante zero; possui um pipeline de instruções de 3 estágios, atingindo no pico de execução uma instrução por ciclo de máquina; e as instruções de salto têm sua execução retardada de uma instrução. A Arquitetura de Computadores é analisada, em especial as Arquiteturas RISC (Reduced Instruction Set Computer - Processador com Conjunto de Instruções Reduzido) e CISC (Complex...), mostrando suas características e comparando-as. Algumas máquinas RISC importantes são vistas e o tema de Arquiteturas VLSI e suas implicações tecnológicas no projeto também é abordado. A arquitetura do Risco é descrita dando-se ênfase aos objetivos do projeto e construindo uma visão geral do processador. O tratamento de exceções é apresentado e o conjunto de instruções é analisado quanto ao formato, aos tipos e ao processamento no pipeline. A organização interna do Risco 6 tratada em detalhes, descrevendo-se a Parte Operativa (barramentos, o banco de registradores, a unidade de tratamento da constante, o contador de programa e incrementador associado, a unidade lógico-aritmética, a unidade de deslocamento/rotação) e a Parte de Controle to funcionamento do pipeline de instrug6es, a decodificação, o autômato de controle, a geração e a validação dos comandos). A simulação funcional do Risco, feita em HDC, também é reportada, incluindo o modelamento, os vetores de testa e os resultados. A implementação do Risco é discutida enfatizando-se alguns blocos críticos quanto A Área e ao desempenho. Os barramentos e o banco de registradores, a ULA e a unidade de deslocamento/rotação são estudados em detalhes pela sua importância no desempenho da maquina. Um teste chip contendo a maior parte dos blocos funcionais da parte operativa foi construído, tendo sido aprovado nos testes funcionais. Por fim, faz-se comentários sobre os resultados obtidos, os problemas encontrados e as etapas futuras no desenvolvimento do Risco, alem de serem expostas as conclusões finais. / This work presents the study, the definition, the electric and logic simulation, and the implementation of some blocks of a 32-bit CMOS microprocessor, with RISC architecture - the Risco. Among Risco's main characteristics it is highlighted that data, instructions and addresses are 32-bit words; the address unit is the word, allowing an access to 4-Giga words (16 GBytes); communication with memory is made through a data and address bus of 32 bits; it has 32 registers of 32 bits, including program counter, stack pointer, processor status word, and a zero constant register; it also has an instruction pipeline of three stages, fully capable of issuing one instruction at the execution peak per every machine cycle; and control flow instructions are implemnted as delayed branches. A study on computer architecture is carried out, and special attention is given to the RISC (Reduced Instruction Set Computer) and CISC (Complex...) architectures by means of making comparisons between them, showing their main characteristics and listing some important RISC machines. The VLSI architectures are also discussed, giving emphasis to their technological importance for the Risco's project. Risco's architecture is described, bringing into prominence the aims of the project and an overview of the processor. Exception handling is presented and the instruction set is analysed with regard to format, type and pipeline processing. Risco's internal organization is dealt with in detail, providing descriptions of the data path (buses, register bank, constant unit, program counter and associated incrementer, barrel shifter) and of the control part (operation of pipeline instruction, as well as decodification, control automaton, generation and validation of commands). Risco's functional simulation, through HDC, is mentioned, including modeling, test vectors, and results. Risco's implementation is also discussed giving emphasis to some critical blocks in regard to area and performance. Buses, register bank, arithmetic-logic unit, and barrel shifter are dealt with in detail because of their importance concerning the machine performance. A test-chip, containing most of the functional blocks of the data path, was made and successfully passed the functional tests. Finally, some comments are made with regard to results, main problems, and next stages in the development of Risco.

Este trabalho apresenta uma proposta para implementação de um subconjunto de instruções e comandos de uma linguagem Pascal Padrão ISSO, aplicada a arquitetura RISC, tendo como base a arquitetura RISC-LIE [Vale91], proposta e desenvolvida no IFQSC. Para definição e construção de parte do código gerado foi utilizada a ferramenta de desenvolvimento de compiladores YACC, que definiu toda estrutura gramatical da linguagem, sendo que as demais estruturas foram desenvolvidas usando interfaces em linguagem C. O código gerado pelo computador utilizou trinta instruções de máquina que compõe o simulador da arquitetura RISC-LIE, gerando assim códigos compatíveis que podem ser interpretados por esse simulador. / This work presents a proposal for an implementation of a subset of instructions and commands of Standard Pascal ISO applied to RISC architectures. The work was developed using the RISC-LIE architecture as our target [Vale91]. The RISC-LIE has been proposed and developed at IFQSC. Part of the code was defined and constructed using YACC, a tool for compilers development which defined the grammatical structure of language. The remainder routines were developed using the C language. The code produced by the compiler used the thirty instructions of the RISC-LIE instruction set. These instructions are implemented in the RISC-LIE architecture simulator. Therefore, generates codes that can be interpreted by this simulator.

Les protéines se liant à l’ARN de la famille IMP sont les protéines oncofoetales conservées, qui régulent le transport, la stabilité et la traduction de plusieurs ARNm cibles. Les IMPs sont impliqués dans la tumorigenèse et dans le développement embryonnaire par le contrôle de la prolifération cellulaire, la différenciation, la migration, la polarisation et d`autres processus cellulaires. IMP-3 est difficilement détectable dans des tissus adultes normaux, mais il est surexprimé dans les nombreux cancers, où il a été caractérisé comme un marqueur d’agressivité et de la croissance tumorale rapide, ainsi que d’un pronostic défavorable pour les patients. Dans notre étude, nous avons utilisé une lignée cellulaire RD de rhabdomyosarcome (RMS), où IMPs étaient initialement décrits comme des protéines régulatrices de l`ARNm de IGF-2. Nous avons essayé d'élucider le mécanisme par lequel IMP3 régule l’expression des cyclines D1 et D3, contribuant ainsi à la compréhension des processus oncogéniques dans les RMS et autres cancers.Nous avons montré que IMP3 régule l'expression des cyclines D1 et D3 d'une manière significative in vivo. Nous avons également démontré, qu'en absence de IMP3, les ARNm des cyclines sont exportés vers le cytoplasme et s’associent avec les polyribosomes, mais ne sont pas traduits. En outre, l'inhibition d`IMP3 n'a pas d'influence sur la stabilité des ARNm des cyclines. Nous démontrons que dans des cellules cancéreuses humaines, IMP3 interagit avec plusieurs protéines se liant à l'ARN, et que nombre de ces protéines a un effet sul l’expression des cyclines, ce que suggère l'existence d'un complexe régulateur multiprotéique sur les 3'UTR des cyclines D1 et D3. Nos résultat montrent que l'inhibition de deux protéines clés de RNA-induced silencing complex (RISC) (AGO2 et GW182/TNRC6), rétablit les niveaux d'expression des cyclines D1 et D3, qui ont été considérablement diminués en l’absence d’IMP3 ou de ses partenaires protéiques ILF3/NF90 et PTBP1. Nous concluons que les complexes d`IMP3 et RISC peuvent concourir pour la régulation des ARNm des cyclines. Nous avons également identifié les miARNs qui peuvent être impliqués dans ce processus, ainsi que les domaines fonctionnellement importants dans les 3 'UTR des cyclines, où se passe la competition entre les complexes d’IMP-3 et RISC. Nos résultats sont compatibles avec l'existence de IMP3 - contenant complexe multiprotéique, qui est associé à 3'UTRs des cyclines et régule leur traduction en les protégeant contre la répression traductionnelle par miRISC. / RNA-binding proteins of the IMP family (IGF2 mRNA-binding proteins 1-3) are conserved oncofetal proteins, regulating transport, stability and decay of multiple mRNAs. IMPs are involved in embryonic developement and tumorigenesis by controlling cell proliferation, differentation, migration, polarization and many other important aspects of cell function. IMP-3 is hardly detectable in normal adult tissues, but is overexpressed in many cancers, where it has been reported as a marker of tumor aggressiveness, rapid growth, and bad prognosis for patients. In our research we utilized a rhabdomyosarcoma (RMS) cell line RD, where IMPs were first described as IGF-2 mRNA regulating proteins. We aimed to elucidate the mechanism by which IMP3 regulates the expression of cyclins D1 and D3, thereby contributing to the understanding of oncogenic processes in RMS.In this study, we show that IMP3 regulates the expression of cyclin D1 and D3 in a significant manner in vivo. We also demonstrate that in the absence of IMP3, the mRNAs of the cyclins are exported to the cytoplasm and associated with polyribosomes, but not translated. IMP3 inhibition does not influence the stability of cyclin mRNAs. We demonstrate that in human cancer cells, IMP3 interacts with multiple RNA-binding proteins, and that a number of these IMP-3 partners impacts on the expression of cyclins D1 and D3. These observations suggest the existence of a regulatory IMP-3 containing RNP complex on the 3’UTR of mRNAs of cyclin D1 and D3. Our results show that an inhibition of two key proteins of RNA-induced silencing complex (RISC) (AGO2 and GW182/TNRC6) rescues the expression of cyclin D1 and D3 proteins, which is significantly decreased in the absence of IMP3 or its protein partners ILF3/NF90 and PTBP1. Therefore, IMP3 and RISC complexes can compete for cyclin mRNAs translational repression/activation. We also identified a number of miRNAs that can be involved in this process, and characterized functionally important regions within 3’ UTRs of the cyclins, where the competition between IMP-3 and RISC complexes takes place. Our results are consistent with the existence of IMP3 - containing multiprotein complex, which is associated with 3’UTRs of the cyclins and regulates their translation by protecting them from miRISC-dependent translational repression.

<p>The cellular microRNA (miRNA) pathway has emerged as an important regulator of host-virus interactions. While miRNAs of viral and cellular origin have been demonstrated to modulate viral gene expression and host immune responses, reports detailing these activities in the context of mammalian retroviruses have been controversial. Using modern, high-throughput small RNA sequencing we provide evidence that the spumaretrovirus bovine foamy virus expresses high levels of viral miRNAs via noncanonical biogenesis mechanisms. In contrast, the lentivirus human immunodeficiency virus type 1 (HIV-1) does not express any viral miRNAs in a number of cellular contexts. Comprehensive analysis of miRNA binding sites in HIV-1 infected cells yielded several viral sequences that can be targeted by cellular miRNAs. However, this analysis indicated that HIV-1 transcripts are largely refractory to binding and inhibition by cellular miRNAs. In addition, we demonstrate that HIV-1 exerts minimal perturbations on cellular miRNA profiles and that viral replication is not affected by the ablation of mature cellular miRNAs. Together, these data demonstrate that the ability of retroviruses to encode miRNAs is not broadly conserved and that lentiviruses, particularly HIV-1, have evolved to avoid targeting by cellular miRNAs.</p> / Dissertation

RISC-V is a new open-source instruction set architecture (ISA) that in De-cember 2016 manufactured its rst mass-produced processors. It focuses onboth eciency and performance and diers from other open-source architec-tures by not having a copyleft license permitting vendors to freely design,manufacture and sell RISC-V chips without any fees nor having to sharetheir modications on the reference implementations of the architecture.The goal of this thesis is to evaluate the performance of the GCC andLLVM/clang compilers support for the RISC-V target and their ability tooptimize for the architecture. The performance will be evaluated from ex-ecuting the CoreMark and Dhrystone benchmarks are both popular indus-try standard programs for evaluating performance on embedded processors.They will be run on both the GCC and LLVM/clang compilers on dierentoptimization levels and compared in performance per clock to the ARM archi-tecture which is mature yet rather similar to RISC-V. The compiler supportfor the RISC-V target is still in development and the focus of this thesis willbe the current performance dierences between the GCC and LLVM com-pilers on this architecture. The platform we will execute the benchmarks onwil be the Freedom E310 processor on the SiFive HiFive1 board for RISC-Vand a ARM Cortex-M4 processor by Freescale on the Teensy 3.6 board. TheFreedom E310 is almost identical to the reference Berkeley Rocket RISC-Vdesign and the ARM Coretex-M4 processor has a similar clock speed and isaimed at a similar target audience.The results presented that the -O2 and -O3 optimization levels on GCCfor RISC-V performed very well in comparison to our ARM reference. Onthe lower -O1 optimization level and -O0 which is no optimizations and -Oswhich is -O0 with optimizations for generating a smaller executable code sizeGCC performs much worse than ARM at 46% of the performance at -O1,8.2% at -Os and 9.3% at -O0 on the CoreMark benchmark with similar resultsin Dhrystone except on -O1 where it performed as well as ARM. When turn-ing o optimizations (-O0) GCC for RISC-V was 9.2% of the performanceon ARM in CoreMark and 11% in Dhrystone which was unexpected andneeds further investigation. LLVM/clang on the other hand crashed whentrying to compile our CoreMark benchmark and on Dhrystone the optimiza-tion options made a very minor impact on performance making it 6.0% theperformance of GCC on -O3 and 5.6% of the performance of ARM on -O3, soeven with optimizations it was still slower than GCC without optimizations.In conclusion the performance of RISC-V with the GCC compiler onthe higher optimization levels performs very well considering how young theRISC-V architecture is. It does seems like there could be room for improvement on the lower optimization levels however which in turn could also pos-sibly increase the performance of the higher optimization levels. With theLLVM/clang compiler on the other hand a lot of work needs to be done tomake it competetive in both performance and stability with the GCC com-piler and other architectures. Why the -O0 optimization is so considerablyslower on RISC-V than on ARM was also very unexpected and needs furtherinvestigation.

AnalysisofshortArgonauteisoformsfrommouseoocytes Abstract: Argonaute proteins carrying small RNAs form the conserved core of RNA silencing mechanisms, which repress viruses, mobile genetic elements, and genes in a sequence specific manner. The microRNA (miRNA) pathway is a dominant mammalian RNA silencing mechanism in somatic cells, which post-transcriptionally regulates large fraction of genes and thereby adjusts protein levels. miRNA-guided Argonautes inhibit translation and induce deadenylation of complementary mRNAs, ultimately resulting in their decay. In contrast to RNA interference (RNAi), which employs Argonaute slicer activity to directly cleave perfectly complementary RNAs, an effective miRNA-mediated mRNA repression requires multiple Argonaute-associated protein factors and enzymes. The miRNA pathway has been implicated in many complex biological processes ranging from organogenesis, stress-response to haematopoiesis or cancer. Surprisingly, canonical miRNAs are not essential for oocytes and early embryonic development in mice. Even the most abundant miRNAs present in mouse oocytes are unable to effectively repress target genes. However, RNAi, which shares key enzymes with the miRNA pathway, is highly active in oocytes and early embryos. The cause of miRNA inactivity in mouse oocytes remains...

The ARM architecture is dominating in the mobile and embedded markets and is making an upwards push into the server and networking markets where virtualization is a key technology. Similar to x86, ARM has added hardware support for virtualization, but there are important differences between the ARM and x86 architectural designs. Given two widely deployed computer architectures with different approaches to hardware virtualization support, we can evaluate, in practice, benefits and drawbacks of different approaches to architectural support for virtualization. This dissertation explores new approaches to combining software and architectural support for virtualization with a focus on the ARM architecture and shows that it is possible to provide virtualization services an order of magnitude more efficiently than traditional implementations. First, we investigate why the ARM architecture does not meet the classical requirements for virtualizable architectures and present an early prototype of KVM for ARM, a hypervisor using lightweight paravirtualization to run VMs on ARM systems without hardware virtualization support. Lightweight paravirtualization is a fully automated approach which replaces sensitive instructions with privileged instructions and requires no understanding of the guest OS code. Second, we introduce split-mode virtualization to support hosted hypervisor designs using ARM's architectural support for virtualization. Different from x86, the ARM virtualization extensions are based on a new hypervisor CPU mode, separate from existing CPU modes. This separate hypervisor CPU mode does not support running existing unmodified OSes, and therefore hosted hypervisor designs, in which the hypervisor runs as part of a host OS, do not work on ARM. Split-mode virtualization splits the execution of the hypervisor such that the host OS with core hypervisor functionality runs in the existing kernel CPU mode, but a small runtime runs in the hypervisor CPU mode and supports switching between the VM and the host OS. Split-mode virtualization was used in KVM/ARM, which was designed from the ground up as an open source project and merged in the mainline Linux kernel, resulting in interesting lessons about translating research ideas into practice. Third, we present an in-depth performance study of 64-bit ARMv8 virtualization using server hardware and compare against x86. We measure the performance of both standalone and hosted hypervisors on both ARM and x86 and compare their results. We find that ARM hardware support for virtualization can enable faster transitions between the VM and the hypervisor for standalone hypervisors compared to x86, but results in high switching overheads for hosted hypervisors compared to both x86 and to standalone hypervisors on ARM. We identify a key reason for high switching overhead for hosted hypervisors being the need to save and restore kernel mode state between the host OS kernel and the VM kernel. However, standalone hypervisors such as Xen, cannot leverage their performance benefit in practice for real application workloads. Other factors related to hypervisor software design and I/O emulation play a larger role in overall hypervisor performance than low-level interactions between the hypervisor and the hardware. Fourth, realizing that modern hypervisors rely on running a full OS kernel, the hypervisor OS kernel, to support their hypervisor functionality, we present a new hypervisor design which runs the hypervisor and its hypervisor OS kernel in ARM's separate hypervisor CPU mode and avoids the need to multiplex kernel mode CPU state between the VM and the hypervisor. Our design benefits from new architectural features, the virtualization host extensions (VHE), in ARMv8.1 to avoid modifying the hypervisor OS kernel to run in the hypervisor CPU mode. We show that the hypervisor must be co-designed with the hardware features to take advantage of running in a separate CPU mode and implement our changes to KVM/ARM. We show that running the hypervisor OS kernel in a separate CPU mode from the VM and taking advantage of ARM's ability to quickly switch between the VM and hypervisor results in an order of magnitude reduction in overhead for important virtualization microbenchmarks and reduces the overhead of real application workloads by more than 50%.

Bibliography: leaves 237-251. / xxi, 251 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / The work in this thesis is devoted to the architecture, implementation and performance of a MATRISC processing mode. Simulation results for the MATRISC processor are provided which give performance estimates for systems which can be implemented in current technologies. It is concluded that the extremely high performance of MATRISC processors makes possible the construction of parallel computers with processing capabilities in excess of one teraflops. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1994

<p>The purpose of this Master Thesis is to analyze what suitable hardware platforms there are on the market in order to build a low price control and information system for mobile applications, called small display module. The thesis will be underlying material for making a decision for further development. The result of the thesis consists mainly of a Windows CE kernel and a schematic for a CPU card, on which it would be suitable to build the display module. Another major part of the report is the introduction of different techniques that could be of interest when designing a processor based system. The processor architecture that was chosen is the x86. This is mainly due to CPU availability, but as well as the fact that existing software can be used on the display module without any significant modifications. Many interesting processors were sorted out because they hade a very high price on the development kits from the manufacturer and because the possible production volume can not manage this cost. The development kit makes the development easier and can be used for performance tests before prototypes are built.</p>

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