Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.

Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are many open source processors based on Risc-V architecture, but it is still unclear how well an open-source Risc-V processor performs network packet processing tasks compared to an Arm-based processor. The main purpose of this thesis is to design a test model simulating and evaluating how well an open-source Risc-V processor performs packet processing compared to an Arm Cortex M7 processor. This was done by designing a C code simulating some key packet processing functions processing 50 randomly generated 72 bytes data packets. The following functions were tested: framing, parsing, pattern matching, and classification. The code was ported and executed in both an Arm Cortex M7 processor and an emulated open source Risc-V processor. A working packet processing test code was built, evaluated on an Arm Cortex M7 processor. Three different open-source Risc-V processors were tested, Arianne, SweRV core, and Rocket-chip. The execution time of both cases was analyzed and compared. The execution time of the test code on Arm was 67, 5 ns. Based on the results, it can be argued that open source Risc-V processor tools are not fully reliable yet and ready to be used for packet processing applications. Further evaluation should be performed on this topic, with a more in-depth look at the SweRV core processor, at physical open-source Risc-V hardware instead of emulators. / Nätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.

Many embedded systems lack a memory management unit (MMU) and thus often also lack protection of memory. This causes these systems to be less robust since the operating system (OS), processes, and threads are no longer isolated from each other. This is also a potential security issue and with the number of embedded systems rapidly increasing as a result of the rise of Internet of things (IoT), vulnerabilities like this could become a major problem. However, with a recent update to the RISC-V processor architecture, a possibility to isolate regions of memory without an MMU was introduced. This study aims to identify problems and possibilities of implementing such memory protection with RISC-V. Based on a study of literature and documentation on memory protection and the RISC-V architecture, a prototype was designed and implemented to determine potential problems and evaluate performance in terms of execution time and memory cost. The developed prototype showed aworking implementation of memory protection for the memory regions with RISC-V. The evaluation of the prototype demonstrated an increase in context switch execution time and memory usage. The results indicate that the implemented memory protection comes with an increased cost in performance with a constant factor and a small memory overhead. Therefore, it is recommended that implementations that wish to implement memory protection with RISC-V on smaller embedded systems where time and memory may be crucial takes the overhead in consideration. Further research and testing is needed to identify optimizations that could improve the performance as well as discover security flaws. / Många inbyggda system saknar en enhet för minneshantering (s.k. MMU) och saknar därför oftast minnesskydd. Detta leder till att dessa system blir mindre robusta eftersom operativsystemet, processer och trådar inte längre är isolerade från varandra. Detta är också en säkerhetsbrist och med antalet inbyggda system som snabbt ökar på grund av tillväxten av Internet of things (IoT), så kan sårbarheter som denna bli ett stort problem. Med en nyligen introducerad uppdatering av RISC-Vprocessor arkitekturen, så introducerades en möjlighet till att isolera minne utan hjälp av en MMU. Denna studie syftar till att identifiera problem och möjligheter av att implementera sådant minneskydd med RISC-V. Baserat på en studie av litteratur och dokumentation om minnesskydd och RISC-V arkitekturen designades och implementerades en prototyp för att hjälpa till att fastställa problem och möjligheter samt göra en utvärdering med avseende på prestanda- och minneskostnader. Den utvecklade prototypen visade en fungerande implementering av minneskydd för minnesregioner med RISC-V. Utvärderingen av prototypen visade en ökad exekveringstid för kontextbyten och ökad minnesanvändning. Resultaten indikerar att det implementerade minneskyddet kommer med en ökad kostnad i prestanda med en konstant faktor och en liten omkostnad i minne. Därför rekommenderas att implementeringar som vill implementera minneskydd med RISC-V på mindre inbyggda system där tid och minne kan vara avgörande tar hänsyn till omkostnaderna. Ytterligare studier och tester behövs för att identifiera optimeringar som kan förbättra prestandan och upptäcka säkerhetsbrister.

In this thesis, we explored the possibility of introducing a few vulnerabilities to a separation kernel to increase its performance. We made modifications to S3K, an open-source separation kernel that is in the final stages of being designed. To test the viability of our modifications we benchmarked both the unmodified and the modified versions and compared the results. We changed the scheduler and the inter-process communication used for time sharing: we introduced side-channel vulnerabilities to allow the modified functionalities to complete their work faster. The changes to the scheduler increased performance notably when having a high scheduling overhead, but not so much with low overhead. The changes to the inter-process communication proved to have limited usefulness, as the default version was already rather quick, and the new version had the drawback of increasing the time needed for scheduling. We also tested our scheduler modifications in the inter-process communication benchmarks. This greatly improved performance in all scenarios, and it made our modifications to the inter-process communication slightly more viable. To see how our results held up in a scenario closer to a real use case we also implemented a simple cryptographic application and designed tests based on it. When we ran the tests with different combinations of including or excluding our modifications we got similar results to our previous benchmarks. Overall, our modifications to the scheduler seem like a promising change to the separation kernel, given that one is willing to introduce the side-channels that come with the changes. The modifications to the inter-process communication on the other hand are more questionable and are likely only useful in specific scenarios. / I detta arbete utforskade vi möjligheten att introducera några sårbarheter till en separationskärna för att öka dess prestanda. Vi modifierade S3K, en separationskärna med öppen källkod som är i slutstadiet av att designas. För att testa hur praktiskt användbara våra modifikationer var så körde vi benchmarks på både den ursprungliga versionen och den modifierade versionen och jämförde resultaten. Vi ändrade schemaläggaren och interprocesskommunikationen som används för att dela tid: sidokanalssårbarheter introducerades för att tillåta de ändrade funktionerna att göra färdigt sina arbeten snabbare. Ändringarna till schemaläggaren visade sig öka prestandan noterbart när man hade en hög schemaläggnings-overhead, men skillnaden var inte så stor med låg overhead. Ändringarna till interprocesskommunikationen visade sig ha begränsad användbarhet, då standardversionen redan var ganska snabb och den nya versionen hade nackdelen att den ökade schemaläggningstiden. Vi testade också våra schemaläggningsmodifikationer i våra benchmarks för interprocesskommunikationen. Detta ökade prestandan mycket i alla scenarion, och gjorde våra modifikationer till interprocesskommunikationen något mer praktiskt användbara. För att se hur våra resultat stod sig i ett mer verkligt scenario så implementerade vi också en simpel kryptografisk applikation, och utformade test runt den. När vi testade olika kombinationer av att inkludera eller exkludera våra modifikationer fick vi liknande resultat som vi fick i tidigare benchmarks. Överlag så verkar våra modifikationer till schemaläggaren lovande, givet att man är villig att introducera de sidokanalssårbarheter som kommer med ändringarna. Modifikationerna till interprocesskommunikationen är dock mer tveksamma, och är sannolikt bara användbara i specifika scenarion.

International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In this paper we describe the design of the REAL/STAR 2000 system, a highperformance real-time computer for telemetry applications. The REAL/STAR 2000 is a symmetric, tightly-coupled multiprocessor, optimized for real-time processing. The system provides a high level of scalability and flexibility by supporting three configurations: single, dual, and quad processor configurations, based on Motorola 88100 RISC processors. The system runs the multiprocessor REAL/IX operating system, a real-time implementation of the AT&T UNIX System V. It compiles with BCS and OCS standards, meets the POSIX 1003.1 standard, and has the current functionality of the emerging POSIX 1003.4 real-time standard. The REAL/STAR 2000 promotes an open system approach to real-time computing by supporting major industry standards. Benchmark results are also presented in the paper.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

INTRODUÇÃO: A literatura demonstra que tromboembolismo venoso permanece como uma doença subdiagnosticada entre os pacientes hospitalizados, com aproximadamente 25% dos casos associados à internação. OBJETIVOS: Avaliar as doenças associadas ao desenvolvimento de tromboembolismo pulmonar (TEP) diagnosticado em autópsias, e demonstrar a frequência de TEP como causa do óbito ou fator contributivo. MÉTODOS: Estudo caso-controle retrospectivo, realizado no Instituto Central do Hospital das Clínicas da Faculdade de Medicina da Universidade de São Paulo, no período de 1995 a 2004. Revisamos os relatórios diagnósticos das autópsias, identificando TEP fatal, quando TEP foi a causa de morte, e TEP não fatal, quando TEP foi doença associada. RESULTADOS: 1.506 pacientes (502 casos e 1.004 controles), 18.359 óbitos no período, média 2.040; 71,2% desses submetidos a autópsias. Observou-se importante declínio nas taxas de autópsias. De 1995-1999 (87,2%) e 2000-2004 (54,4%); p = 0,016. Dos 502 casos (3,8%), em 328 (2,5%) TEP foi causa de morte e 174 (1,3%), causa contributiva. Gênero: 51,6% homens e 48,4% mulheres. Idade: TEP fatal (328) vs controles (1.004), diferença estatisticamente significativa (p = 0,013). Condições prevalentes: câncer grupo, 31,4%, pós-operatório grupo, 17,2%, infecção grupo, 11,7%, e AVC grupo, 11%. Câncer de pulmão, 3,5%, câncer de cérebro e linfoma, 2,8%. Tempo de internação foi utilizado como indicador de imobilização. Outras doenças: AVCH (7,7%), pós-operatório de abdome (6,7%), pneumonia (5,9%), AVCI (3,1%) e pós-operatório vascular (4%) foram frequentes no grupo controle. Em contrapartida, aterosclerose (1,4%), ITU (1,2%), pós-operatório de ginecologia (0,8%), pós-operatório de obstetrícia (0,6%) e doença falciforme (0,6%) foram frequentes no grupo TEP. Cirrose, média de 14,9 dias de internação dos controles vs TEP com 4,4 dias (p < 0,001). Análise multivariada incluiu as condições com p 0,20 da univariada, idade e tempo de internação. Fator protetor para TEP: aneurisma de aorta (OR 0,02, IC 95% 0,46-0,56; p = 0,004), cirrose (OR 0,16, IC 95% 0,08-0,34; p < 0,001) e SIDA (OR 0,44, IC 95% 0,23-0,84; p = 0,013). Entretanto, AVCI (OR 1,82, IC 95% 1,04-3,19; p = 0,035), câncer de cérebro (OR 2,47, IC 95% 1,28-4,78; p = 0,007), câncer indeterminado (OR 3,12, IC 95% 1,01-9,68; p = 0,049), DPOC (OR 2,83, IC 95% 1,47-5,43; p = 0,002), ICC (OR 1,71, IC 95% 1,11-2,62; p = 0,015) e ITU (OR 4,34, IC 95% 1,05-17,82; p = 0,042) mostraram associação positiva com TEP. Idade vs TEP (OR 1,10, IC 95% 1,04-1,16; p = 0,001). Tempo de internação vs TEP (OR 1,19, IC 95% 1,05-1,36; p = 0,008). DISCUSSÃO: A porcentagem dos pacientes com TEP permanece inalterada, ocorrência de 4,1% e 3,4% no primero e no segundo períodos, com uma média de 3,8%. Em 50,4% dos pacientes não foi realizado o diagnóstico clínico de TEP. CONCLUSÃO: Constatou-se AVCI, câncer de cérebro indeterminado, DPOC, ICC e ITU com significância estatística e associação com TEP. Algumas fraquezas do presente estudo devem ser apuradas, e talvez explicarão as discordâncias com a literatura para algumas doenças. A identificação de fatores associados a TEP auxiliarão no diagnóstico precoce / INTRODUCTION: Literature shows that venous thromboembolism (VTE) remains as a sub-diagnostic disease among hospitalized patients, approximately 25% of all cases are associated to hospitalization. PURPOSE: Evaluate diseases associated to pulmonary thromboembolism (PE) development diagnosed in autopsies, and demonstrate the frequency of PE as cause of death or as a contributive factor. METHOD: The reports performed from 1995 to 2004 in a Brazilian tertiary referral medical school we reviewed for a retrospective study the autopsies diagnosis, identified as fatal PE, when PE was the cause of death and nonfatal PE, when PE was an associated disease. RESULTS: 1,506 patients (502 cases and 1004 controls), 18,359 deaths during the period, average 2,040; 71.2% of these were submitted to autopsies. It was observed an important decline in the autopsies rates. From 1995-1999 (87.2%) and 2000-2004 (54.4%) p = 0.016. From 502 cases (3.8%), 328 (2.5%) PE was the cause of death and 174 (1.3%) PE was contributive cause. Gender: 51.6% males and 48.4% females. AGE: fatal PE (328) vs controls (1,004) significant statistic difference (p = 0.013). Prevalent Conditions: cancer group, 31.4%, postsurgical group, 17.2%, infectious group, 11.7%, and CVA group, 11%. Pulmonary Cancer, 3.5%, Brain cancer and Lymphoma, 2.8%. Hospitalization period was taken as immobilization indicator. Other diseases: HCVA (7.7%), abdomen postsurgical (6.7%), pneumonia (5.9%), ICVA (3.1%) and vascular postsurgical (4%) were frequent in the control group. On the other hand, atherosclerosis (1.4%), UTI (Urinary Tract Infection) (1.2%), gynecology postsurgical (0.8%), obstetrics postsurgical (0.6%) and sickle cell anemia (0.6%) were frequent in the PE group. Cirrhosis, average of 14.9 hospitalization days of the controls vs PE with 4.4 days (p < 0.001). Logistic regression analysis includes the in univariated analysis with p 0.20, age and the hospitalization period. Protector factor for PE: Aortic aneurysm (OR 0.02, 95% CI 0.46-0.56; p = 0.004), cirrhosis (OR 0.16, 95% CI 0.08-0.34; p < 0.001) and SIDA (OR 0.44, 95% CI 0.23-0.84; p = 0.013). However, ICVA (OR 1.82, 95% CI 1.04-3.19; p = 0.035); brain cancer (OR 2.47, 95% CI 1.28-4.78; p = 0.007); undetermined cancer (OR 3.12, 95% CI 1.01-9.68, p= 0.049), COPD (OR 2.83, 95% CI 1.47-5.43; p = 0.002), CHF (OR 1.71, 95% CI 1.11-2.62; p = 0.015) and UTI (OR 4.34, 95% CI 1.05-17.82; p = 0.042), showed positive association with PE. Age vs PE (OR 1.10, 95% CI 1.04-1.16; p = 0.001). Hospitalization Period vs PE (OR 1.19, 95% CI 1.05-1.36; p = 0.008). DISCUSSION: The percentage of patients with PE remains unchanged, occurrence of 4.1% and 3.4% in the first and second periods, with an average of 3.8%. In 50.4% of the patients, the clinical diagnosis of TEP was not performed. CONCLUSION: We certified ICVA, brain cancer, undetermined cancer, COPD, CHF and UTI with significant association with PE. Some weaknesses of the present study should be refined, and maybe will explain the disagreement with the literature to some diseases. The identification of factors associated to PE will help in precocious diagnosis