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This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution.

Variations in ionospheric plasma density can cause large amplitude and phase changes in the radio waves passing through this region. Ionospheric weather can have detrimental effects on several communication systems, including radars, navigation systems such as the Global Positioning Sytem (GPS), and high-frequency communications. As a result, creating models of the ionospheric density is of paramount interest to scientists working in the field of satellite communication. Numerous empirical and theoretical models have been developed to study the upper atmosphere climatology and weather. Multiple measurements of plasma density over a region are of marked importance while creating these models. The lack of spatially distributed observations in the upper atmosphere is currently a major limitation in space weather research. A constellation of CubeSat platforms would be ideal to take such distributed measurements. The use of miniaturized instruments that can be accommodated on small satellites, such as CubeSats, would be key to acheiving these science goals for space weather. The accepted instrumentation techniques for measuring the electron density are the Langmuir probes and the Plasma Impedance Probe (PIP). While Langmuir probes are able to provide higher resolution measurements of relative electron density, the Plasma Impedance Probes provide absolute electron density measurements irrespective of spacecraft charging. The central goal of this dissertation is to develop an integrated architecture for the PIP that will enable space weather research from CubeSat platforms. The proposed PIP chip integrates all of the major analog and mixed-signal components needed to perform swept-frequency impedance measurements. The design's primary innovation is the integration of matched Analog-to-Digital Converters (ADC) on a single chip for sampling the probes current and voltage signals. A Fast Fourier Transform (FFT) is performed by an off-chip Field-Programmable Gate Array (FPGA) to compute the probes impedance. This provides a robust solution for determining the plasma impedance accurately. The major analog errors and parametric variations affecting the PIP instrument and its effect on the accuracy and precision of the impedance measurement are also studied. The system clock is optimized in order to have a high performance ADC. In this research, an alternative clock generation scheme using C-elements is described to reduce the timing jitter and reference spurs in phase locked loops. While the jitter performance and reference spur reduction is comparable with prior state-of-the-art work, the proposed Phase Locked Loop (PLL) consumes less power with smaller area than previous designs.

Der Beitrag befasst sich mit einer ersten methodisch-systematischen Analyse der Biomorphisierung von Mensch-Maschine-Schnittstellen, also der Nutzung von biologischen Aktivitätsmustern für Signalkodierungen. Aufbauend auf Beispielen aus dem Alltag werden menschliche Eigenschaften, die sich zur Anthropomorphisierung und Biomorphisierung eignen, analysiert. Sodann werden geeignete Signalparameter zusammengestellt, die mit den technischen Ausgabemöglichkeiten und den dazugehörigen Signalen verbunden werden können. Beispielhaft wurde bei der Mensch-Maschine-Schnittstelle eines Geldautomaten eine Biomorphisierung deren Interaktionen vorgenommen. Ein Ausblick auf Folgeuntersuchungen, welche die Interaktionen evaluieren, schließt den Beitrag.

Der Beitrag befasst sich mit einer ersten methodisch-systematischen Analyse der Biomorphisierung von Mensch-Maschine-Schnittstellen, also der Nutzung von biologischen Aktivitätsmustern für Signalkodierungen. Aufbauend auf Beispielen aus dem Alltag werden menschliche Eigenschaften, die sich zur Anthropomorphisierung und Biomorphisierung eignen, analysiert. Sodann werden geeignete Signalparameter zusammengestellt, die mit den technischen Ausgabemöglichkeiten und den dazugehörigen Signalen verbunden werden können. Beispielhaft wurde bei der Mensch-Maschine-Schnittstelle eines Geldautomaten eine Biomorphisierung deren Interaktionen vorgenommen. Ein Ausblick auf Folgeuntersuchungen, welche die Interaktionen evaluieren, schließt den Beitrag.

Signalprojekteringen konstruerar och skapar de förutsättningar som krävs för att en signalbygghandling ska färdigställas. Vid förändringar som exempelvis upprustningar, projekteras de signalställverk som finns placerade längs Sveriges järnvägar för att sedan byggas av entreprenader. Projekteringen är en grund för att skapa rätt förutsättningar för att genomföra ett kvalitativt bygge. Trafikverket har märkt av kvalitetsbrister inom signalprojekteringen, som har flertal orsaker men mycket pekar mot en brist på kompetens. Trafikverket har sedan 2019 infört nya kompetenskrav för sina upphandlingar med konsulter, som ska säkerställa att arbetet genomförs med rätt teknisk kompetens. Uppgiften är att undersöka om Trafikverkets nya kompetenskrav används, följs upp och om de åstadkommit en effekt samt om kravskrivningen bör justeras och åtgärder för främja kompetens, framföras. Examensarbetet genomförande bygger främst på datainsamling genom intervjuer och enkäter. Resultatet av detta projekt fastställde att kompetenskraven inte gett någon tydlig effekt i kvalitetsnivån. Mycket beror på att det är för tidigt för en utvärdering, då järnvägsprojekt har långa ledtider men också på andra faktorer. Kompetenskraven uppskattas men kravskrivning bör justeras för att bli tydligare. De åtgärder som ansågs mest lämpliga var återkoppling till projektör, eget forum för projektörer, anläggningsspecifika kurser och mentormöjligheter till oerfarna projektörer. En åtgärd som kan motverka mycket med kvalitetsbrister som nämns i projektet är mervärdesupphandlingar. Mervärdesupphandling medför möjligheter som att kravställa mjuka kriterier som exempelvis erfarenhet och utbildningar och motverkar de negativa effekter men den nuvarande upphandlingsformen på lägst pris. / Signal designing means construction and modelling of railway signal facilities. Changes within the railway leads to modelling being made where the adequate prerequisites for a functioning facility are drawn by using CAD or BIM. Trafikverket have noticed various of quality deficiencies within the modelling phase of their facilities. It is mainly due to a lack of technical competence for the signal designers. Since 2019, Trafikverket have implemented new requirements for competence during their negotiations with consulting firms that conduct the designs, as a countermeasure for these quality deficiencies within competence. However, the effect of these countermeasures is still unknown. The objective for this project is to examine if the new requirements are used in the projects, if they are followed-up and if there are any effects from them. Moreover, to conclude if the requirements should be adjusted and if there are valid measures to increase the development of competence for signal designers. The methodology of the project is mostly based on interviews with specialists and analyses of the results. The result concluded that there is no definite effect of the competence requirements, mostly due to the length (time) of railway related projects. Furthermore, the competence requirements are appreciated by Trafikverkets employees however, it should be adjusted to be more definite. The best countermeasures are feedback to signal designers and followed by other countermeasure such as an own forum, more specific facility courses (education) and mentors for signal designers. A new form of negotiation which is called the “More value negotiation” is also a method of countering quality deficiencies.

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs.

De nombreux dispositifs embarqués récents comme les téléphones portables, les GPS ou encore les consoles de jeu, possèdent un ou des haut-parleurs, chacun étant piloté par un amplificateur audio sur circuit intégré. De tels amplificateurs audio doivent répondre le mieux possible à quatre contraintes : une qualité audio satisfaisante, une immunité aux perturbations induites par le système, une faible consommation et une surface de silicium minimale. Ce travail de thèse sous contrat CIFRE a pour origine la création de l’entreprise Primachip en mai 2009 par Christian Dufaza et Hassan Ihs. Cette startup a été bâtie sur une architecture innovante d’amplificateur audio de classe D intégré. Son originalité repose sur le principe de rétroaction partielle qui s’applique à une boucle contenant un modulateur numérique Delta Sigma (ΔΣ) qui pilote l’étage de puissance et un convertisseur analogique-numérique (ADC) effectuant la rétroaction. Cela permet d’obtenir la stabilité de cette boucle tout en offrant une excellente réjection des bruits de l’étage de puissance. Un prototype sur silicium de l’architecture d’amplificateur de classe D numérique a été conçu et fabriqué. Un nouvel ADC ΔΣ temps continu a été développé pour ce prototype, afin d’obtenir des performances supérieures ou égales à l’état de l’art. Les résultats obtenus sur le circuit se sont révélés encourageants, bien que toutes les spécifications n’aient pas été atteintes. L’analyse des erreurs de ce premier circuit doit permettre la réalisation d’un amplificateur intégré exploitant au mieux cette architecture de classe D numérique. / Most current embedded devices, such as smartphones, GPS or portable consoles, feature one speaker or more, those speakers being driven by an integrated audio amplifier. This type of amplifier must meet four specifications: an adequate audio quality, to be immune to system disturbances, low power consumption and the smallest silicon area. This work takes its origin from the creation of Primachip in May 2009 by Christian Dufaza and Hassan Ihs. The aim of this startup was to develop and sell an innovative audio class-D amplifier for mobile market: the digital class-D concept. A partnership with the IM2NP laboratory was decided to propose a PhD topic under CIFRE contract (PhD in an industrial environment), in order to study and improve the amplifier architecture. Its originality is in the partial feedback concept which applies to a loop made of a digital ΔΣ modulator driving the power stage, with an analogue-to-digital converter (ADC) in the feedback path. It makes it possible to achieve stability while offering an outstanding power supply rejection. An integrated prototype of the class-D amplifier was designed, fabricated and evaluated. A new continuous-time ΔΣ ADC has been added to enable the digital class-D loop to achieve performances superior or equal to state of the art. The circuit measurement results were encouraging, although not ideal. The analysis of the prototype errors was performed. The conclusions should allow the design of an integrated audio amplifier making the best of the digital class-D architecture.

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modernday application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology. ∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches. System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions. / Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna. Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASICdesign med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden. ∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar. Systemoch beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer. De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

Abstract Multiple-input multiple-output transmitted signal design for the partially coherent Rayleigh fading channels with discrete inputs under a given average transmit power constraint is consider in this thesis. The objective is to design the space-time constellations and linear precoders to adapt to the degradation caused by the imperfect channel estimation at the receiver and the transmit-receive antenna correlation. The system is partially coherent so that the multiple-input multiple-output channel coefficients are estimated at the receiver and its error covariance matrix is fed back to the transmitter. Two constellation design criteria, one for the single and another for the multiple transmit antennae are proposed. An upper bound on the average bit error probability for the single transmit antenna and cutoff rate, i.e., a lower bound on the mutual information, for multiple transmit antennae are derived. Both criteria are functions of channel estimation error covariance matrix. The designed constellations are called as partially coherent constellation. Additionally, to use the resulting constellations together with forward error control codes requires efficient bit mapping schemes. Because these constellations lack geometrical symmetry in general, the Gray mapping is not always possible in the majority of the constellations obtained. Moreover, different mapping schemes may lead to highly different bit error rate performances. Thus, an efficient bit mapping algorithm called the modified binary switching algorithm is proposed. It minimizes an upper bound on the average bit error probability. It is shown through computer simulations that the designed partially coherent constellation and their optimized bit mapping algorithm together with turbo codes outperform the conventional constellations. Linear precoder design was also considered as a simpler, suboptimal alternative. The cutoff rate expression is again used as a criterion to design the linear precoder. A linear precoder is obtained by numerically maximizing the cutoff rate with respect to the precoder matrix with a given average transmit power constraint. Furthermore, the precoder matrix is decomposed using singular-value-decomposition into the input shaping, power loading, and beamforming matrices. The beamforming matrix is found to coincide with the eigenvectors of the transmit correlation matrix. The power loading and input shaping matrices are solved numerically using the difference of convex functions programming algorithm and optimization under the unitary constraint, respectively. Computer simulations show that the performance gains of the designed precoders are significant compared to the cutoff rate optimized partially coherent constellations without precoding. / Tiivistelmä Väitöskirjassa tarkastellaan lähetyssignaalien suunnittelua osittain koherenteissa Rayleigh-häipyvissä kanavissa toimiviin monitulo-monilähtöjärjestelmiin (MIMO). Lähettimen keskimääräinen lähetysteho oletetaan rajoitetuksi ja lähetyssignaali diskreetiksi. Tavoitteena on suunnitella tila-aikakonstellaatioita ja lineaarisia esikoodereita jotka mukautuvat epätäydellisen kanavaestimoinnin aiheuttamaan suorituskyvyn heikkenemiseen sekä lähetin- ja vastaanotinantennien väliseen korrelaatioon. Tarkasteltavien järjestelmien osittainen koherenttisuus tarkoittaa sitä, että MIMO-kanavan kanavakertoimet estimoidaan vastaanottimessa, josta niiden virhekovarianssimatriisi lähetetään lähettimelle. Työssä esitetään kaksi konstellaatiosuunnittelukriteeriä, toinen yhdelle lähetinantennille ja toinen moniantennilähettimelle. Molemmat kriteerit ovat kanavan estimaatiovirheen kovarianssimatriisin funktioita. Työssä johdetaan yläraja keskimääräiselle bittivirhetodennäköisyydelle yhden lähetinantennin tapauksessa sekä rajanopeus (cutoff rate), joka on alaraja keskinäisinformaatiolle, usean lähetinantennin tapauksessa. Konstellaatioiden käyttö yhdessä virheenkorjauskoodien kanssa edellyttää tehokaita menetelmiä, joilla bitit kuvataan konstellaatiopisteisiin. Koska tarvittavat konstellaatiot eivät ole tyypillisesti geometrisesti symmetrisiä, Gray-kuvaus ei ole yleensä mahdollinen.Lisäksi erilaiset kuvausmenetelmät voivat johtaa täysin erilaisiin bittivirhesuhteisiin. Tästä johtuen työssä esitetään uusi kuvausalgoritmi (modified bit switching algorithm), joka minimoi keskimääräisen bittivirhetodennäköisyyden ylärajan. Simulointitulokset osoittavat, että työssä kehitetyt konstellaatiot antavat paremman suorituskyvyn turbokoodatuissa järjestelmissä kuin perinteiset konstellaatiot. Työssä tarkastellaan myös lineaarista esikoodausta yksinkertaisena, alioptimaalisena vaihtoehtona uusille konstellaatioille. Esikoodauksen suunnittelussa käytetään samaa kriteeriä kuin konstellaatioiden kehityksessä eli rajanopeutta. Lineaarinen esikooderi löydetään numeerisesti maksimoimalla rajanopeus kun rajoitusehtona on lähetysteho. Esikoodausmatriisi hajotetaan singulaariarvohajotelmaa käyttäen esisuodatus, tehoallokaatio ja keilanmuodostusmatriiseiksi, jonka havaitaan vastaavan lähetyskorrelaatiomatriisin ominaisvektoreita. Tehoallokaatiomatriisi ratkaistaan numeerisesti käyttäen difference of convex functions -optimointia ja esisuodatusmatriisi optimoinnilla unitaarista rajoitusehtoa käyttäen. Simulaatiotulokset osoittavat uusien esikoodereiden tarjoavan merkittävän suorituskykyedun sellaisiin rajanopeusoptimoituihin osittain koherentteihin konstellaatioihin nähden, jotka eivät käytä esikoodausta.