Three-dimensional (3-D) system integration is believed to be a promising technology and has gained tremendous momentum in the semiconductor industry recently. The Silicon interposer is the key enabler for the 3-D systems, and is expected to have high input/output counts, fine wiring lines and many TSVs. Modeling and design of the silicon interposer can be challenging and is becoming a critical task. This dissertation mainly focuses on developing an efficient modeling approach for silicon interposers in 3-D systems. The developed numerical methods can be classified as several categories. 1. The investigation of the coupling effects in large TSV arrays in silicon interposers. The importance of coupling between TSVs for low resistivity silicon substrates is quantified both in frequency and time domains. This has been compared with high resistivity silicon substrates. 2. The development of an electromagnetic modeling approach for non-uniform TSVs. To model the complex TSV structures, an approach for modeling conical TSVs is proposed first. Later a hybrid modeling method which combines the conical TSV modeling method and cylindrical modeling method is proposed to model the non-uniform TSV structures. 3. The development of a hybrid modeling approach for power delivery networks (PDN) with through-silicon vias (TSVs). The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. 4. The development of an efficient approach for modeling signal paths with TSVs in silicon interposers. The proposed method utilizes the 3-D finite-difference frequency-domain (FDFD) method to model the redistribution layer (RDL) transmission lines. A new formulation on incorporating multiport networks into the 3-D FDFD formulation is presented to include the parasitic effects of TSV arrays in the system matrix. 5. The development of a 3-D FDFD non-conformal domain decomposition method. The proposed method allows modeling individual domains independently using the FDFD method with non-matching meshing grids at interfaces. This non-conformal domain decomposition method is applied to model interconnections in silicon interposer.

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.

A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of > 99.99 atomic % purity were grown at 250°C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ~ 1700 Å of highly conformal copper was grown at 225°C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125°C at a rate of 20 Å/min to give a continuous ~ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring. © 2008 Elsevier B.V.

This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays. / text

With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.

Les dictats de la course à la miniaturisation et à l'accroissement des performances suivit par les industriels de la microélectronique, se heurte aujourd'hui aux limites physiques, technologiques et économiques. Une alternative innovante pour dépasser ces inconvénients, réside en l'intégration tridimensionnelle de circuits intégrés. Cette technologie consiste à empiler verticalement différents niveaux de circuits aux fonctionnalités diverses. Elle ouvre la voie à des systèmes multifonctions ou hétérogènes, aux performances électriques bien meilleures que les circuits bidimensionnels existants. L'empilement de ces puces est réalisable par l'intermédiaire de vias traversant nommés « Though Silicon Via » (« TSV »), qui sont obtenus par la succession de différentes étapes technologiques, dont une d'entre elles consiste à réaliser par gravure plasma, des microcavités profondes à travers le silicium. Actuellement deux procédés de gravure plasma sont principalement utilisés pour la conception de « TSV », le procédé Bosch et le procédé cryogénique, avec dans les deux cas des avantages et des inconvénients différents. L'objet de cette thèse s'inscrit dans le développement d'un procédé de gravure plasma innovant et alternatif à ceux actuellement utilisés, afin de limiter leurs inconvénients (rugosité de flancs, manque de contrôle des profils, basse température…). Dans cette logique deux procédés de gravure profonde ont été envisagés, exploitant les chimies de gravure SF6/O2/HBr et SF6/O2/HBr/SiF4. L'ensemble de l'étude vise à une meilleure compréhension des mécanismes de gravure et de passivation des cavités à fort facteur de forme grâce en particulier à l'exploitation des techniques d'analyse de surface par XPS. / The dictates of miniaturization and increased performance followed by microelectronics manufacturers faces currently physical, technological and economic limitations. An innovative alternative to these problems is the three-dimensional integration of integrated circuits. This technology involves the vertical stacking of different levels of functionality on the various circuits, and thus opens the way for multifunctional or heterogeneous systems, with electrical performance that are much better than those existing in the two-dimensional circuits. The stacking of these chips is achievable through crossing vias named TSV for "Through Silicon Via", which are obtained by the succession of different technological steps,. One of these steps is the realization by plasma etching of deep silicon microcavities. Currently two plasma etch processes are mainly used for the design of TSV or other silicon structures, the Bosch Process and the Cryogenic process, in both cases with different advantages and disadvantages. The purpose of this thesis is to develop an innovative and alternative plasma etching method comparing to those currently used, to minimize their disadvantages (sidewall roughness, lack of profiles control, low temperature ...). In this logic two deep etch processes have been considered, exploiting SF6/O2/HBr and SF6/O2/HBr/SiF4 etching chemistries. All the studies focuses at better understanding of the mechanisms of etching and passivation of high aspect ratio cavities, especially through exploitation of XPS surface analysis

L’utilisation de photodiodes avalanche monophotoniques (PAMP) pour une utilisation au sein d’imageur préclinique par tomographie d’émission par positrons est d’intérêt. En effet, l’utilisation de ces photodétecteurs intégrés au CMOS est poussée par leurs excellentes performances de résolution en temps ainsi que leur haute sensibilité. Cependant, l’utilisation de ces détecteurs nécessite également un circuit intégré de contrôle visant à protéger les photodiodes de courants trop élevés lors de déclenchement d’avalanches et de contrôler leurs temps mort. Ces circuits de plus en plus sophistiqués nécessitent un espace significatif diminuant ainsi la surface photosensible à la surface de la puce et diminuant leurs sensibilités. L’assemblage 3D puce-à-puce est donc nécessaire dans le but d’augmenter la surface photosensible et de ne pas limiter les fonctionnalités de contrôles électroniques individuelles à chaque PAMP. Ce document présente le développement d’un procédé d’assemblage 3D puce-à-puce visant l’intégration de matrices de PAMP. Les étapes de microfabrication nécessaires visent l’intégration d’interconnexions verticales au travers du substrat (TSV) permettant de transmettre les signaux d’une couche à l’autre et le collage 3D de ceux-ci. De plus, des mesures de caractéristiques de bruits ont été effectuées sur des puces ayant subi certaines étapes de microfabrication du procédé d’assemblage 3D. Ces mesures ont été effectuées dans le but de déterminer l’impact potentiel du procédé d’assemblage sur les performances des PAMP intégrés en 3D.

In this paper, processing effects of electroplating and post- plating annealing on via extrusion are investigated. The study is based on two TSV structures with identical geometry but different processing conditions. Via extrusion, stress and material behaviors of the TSV structures were first compared. Electron backscatter diffraction (EBSD) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) were used to characterize the microstructure of TSVs and the additives incorporated during electroplating. Based on the results, processing effects on via extrusion and its mechanism are discussed, including grain growth, local plasticity, and diffusional creep.

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Tables

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.