This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.

Abstract The aim of this work was to develop time-to-digital converters(TDC) with a wide measurement range of several hundred microseconds and with a measurement precision of a few picoseconds. Because of these requirements, the focus of this work was mainly on TDC architectures based on the Nutt interpolation method, which has several advantages when a long measurement range is a requirement. Compared to conventional data converters the characteristics of a Nutt TDC differ significantly when, for example, quantization errors and linearity errors are considered. In this thesis, the operating principle of a Nutt TDC is analysed and, in particular, the effects of reference clock instabilities are studied giving new insight how the different phase noise processes can be reliably translated into time interval jitter, and how these affect the measurement precision when very long time intervals are measured. Furthermore, these analytical results are confirmed by measurements conducted with a long-range TDC designed as part of this work. Two long-range TDCs have been designed, each based on different interpolator architectures. The first TDC utilises discrete component time-to-voltage converters(TVC) as interpolators. Other key functionality is implemented on an FPGA. The interpolators use Miller integrators to improve the linearity and the single-shot precision of the converter. The TDC has a nominal measurement range of 84ms and it achieves a single-shot precision of 2ps for time intervals shorter than 2ms, after which the precision starts to deteriorate due to the phase noise of the reference clock. In addition to the discrete TDC, an integrated long-range CMOS TDC has been designed with 0.35μm technology. Instead of TVCs, this TDC features cyclic/algorithmic interpolators, which are based on switched-frequency ring oscillators(SRO). The frequency switching is used as a mechanism to amplify quantization error, a key functionality required by any cyclic or a pipeline converter. The interpolators are combined with a 16-bit main counter giving a total range of 327μs. The RMS single-shot precision of the TDC is 4.2ps without any nonlinearity compensation. Furthermore, a calibration functionality implemented partially on-chip ensures that the accuracy of the TDC varies only ±2.5ps in a temperature range of -30C to 70C. Although implemented with fairly old technology, the interpolators’ effective linear range and precision represent state-of-the-art performance. / Tiivistelmä Tämän työn tavoitteena oli kehittää aika-digitaalimuuntia (TDC), joilla on laaja satojen mikrosekuntien mittausalue ja muutaman pikosekunnin kertamittaustarkkuus. Näistä vaatimuksista johtuen tässä työssä keskitytään pääasiassa Nuttin interpolointimenetelmään perustuviin TDC-arkkitehtuureihin. Verrattuna tavanomaisiin datamuuntimiin, Nutt TDC:n toiminta poikkeaa merkittävästi, kun tarkastellaan kvantisointi- ja lineaarisuusvirhettä. Tässä väitöskirjatyössä Nuttin menetelmään perustavan TDC:n toiminta analysoidaan, jonka yhteydessä tutkitaan erityisesti referenssioskillaattorin epästabiilisuuksien vaikutusta mittausepävarmuuteen. Tämän pohjalta vaihekohinan eri kohinaprosessit voidaan luotettavasti muuntaa taajuustason kohinatiheysmittauksista aika-tasossa kuvattavaksi aikavälijitteriksi. Nämä teoreettiset tulokset ovat varmistettu yhdellä osana tätä työtä suunnitellulla pitkän kantaman TDC:llä. Teoreettisen tarkastelun lisäksi kaksi pitkän kantaman TDC:tä on suunniteltu, toteutettu ja testattu. Ensimmäinen näistä perustuu erilliskomponenteilla toteutettuun aika-jännitemuunnokseen (TVC) pohjautuvaan interpolointimenetelmään. Analogisten interpolaattoreiden ohella muu olennainen toiminnallisuus toteutettiin FPGA:lle. Interpolaattorit käyttävät Miller-integraattoreita lineaarisuuden ja kertamittaustarkkuuden parantamiseksi. TDC:n nimellinen mittausalue on 84ms ja sillä saavutetaan 2ps:n kertamittaustarkkuus, kun mitattava aikaväli on lyhyempi kuin 2ms, minkä jälkeen mittaustarkkuus heikkenee referenssioskillaattorin vaihekohinan vaikutuksesta. Toinen pitkän kantaman TDC perustuu 0.35μm:n CMOS teknologialla totetutettuun integroituun piiriin. Aika-jännitemuunnoksen sijasta tämä TDC perustuu sykliseen/algoritmiseen interpolointitekniikkaan, jossa taajuusmoduloitua rengasoskillaattoria(SRO) käytetään kvantisointivirheen vahvistamiseksi. Interpolaattorit ovat yhdistetty 16-bittiseen referenssioskillaattorin laskuriin, jolloin TDC:n mittausalue on noin 327μs. Tämän TDC:n RMS kertamittaustarkkuus on 4.2ps, joka saavutetaan ilman epälineaarisuuden kompensointia. Samalle piirille on lisäksi toteutettu kalibrointitoiminnallisuus, jolla varmistetaan TDC:n hyvä mittaustarkkuus kaikissa olosuhteissa. Mittaustarkkuus poikkeaa maksimissaan vain ±2.5ps, kun lämpötila on välillä -30C-70C. Vaikka TDC on toteutettu kohtalaisen vanhalla CMOS teknologialla, interpolaattoreiden efektiivinen lineaarinen alue ja mittaustarkkuus edustavat alansa huippua.

Abstract The aim of this work was to improve the performance and usability of a digital time-to-digital converter (TDC) in CMOS technology. The characteristics of the TDC were improved especially for the needs of pulsed laser time-of-flight (TOF) distance measurement, where picosecond-level precision with a long µs-level measurement range is needed in order to approach mm-level measurement accuracy. Stability in the face of process, voltage and temperature variations, multiple measurement channels, alternative measurement modes, a high integration level, standard interfaces and simple usage were the main features for development. The measurement architecture is based on counter and timing signal interpolation on two levels. The counter counts the full reference clock cycles between the timing signals, while a new recycling delay line developed in this thesis interpolates within the reference clock cycle. This technique utilizes a short delay line several times per reference clock cycle, which minimizes the interpolation nonlinearity. The same structure also makes the use of a low, MHz-level reference frequency possible, and thus only a crystal is needed as an external oscillator component. The parallel load capacitor-scaled delay line structure acts as the second, sub-gate-delay interpolation level. The INL does not accumulate in elements connected in parallel, and the load capacitance differences enable high, ps-level resolution to be achieved. Four TDC circuits in 0.35 µm CMOS technology were designed and tested in the course of this work, of which the latest, a 7-channel TDC, is able to measure the time intervals between the start pulse and three separate stop pulses in one measurement and to resolve the pulse widths or rise times at the same time. In laser TOF distance measurement this functionality can be used when several echoes arrive at the receiver, and also to compensate for the detection threshold problem known as timing walk error. The TDC achieves 8.9 ps interpolation resolution within the cycle time of a 20 MHz reference clock using only 8 delay elements on the first interpolation level and 14 delay elements on the second. A measurement precision better than 9 ps was achieved without using result post-processing or look-up tables. This work shows that versatile, high performance TDCs can be created in standard CMOS technology. / Tiivistelmä Väitöskirjatyön tavoitteena oli parantaa CMOS-aika-digitaalimuuntimien suorituskykyä ja käytettävyyttä. Muuntimen ominaisuuksia kehitettiin erityisesti laseretäisyysmittauksen tarpeita ajatellen, missä millimetritason mittaustarkkuus laajalla mittausaluella edellyttää aika-digitaalimuuntimelta pikosekuntitason tarkkuutta mikrosekuntien mittausalueella. Stabiilius prosessiparametri-, jännite- ja lämpötilavaihteluita vastaan, useat mittauskanavat, useat mittausmoodit, korkea integraatioaste, standardoidut liitäntäväylät ja helppo käytettävyys olivat erityisesti kehityksen kohteina. Suunniteltu mittausarkkitehtuuri koostuu laskurista ja kaksitasoisesta ajoitussignaali-interpolaattorista. Laskuri laskee kokonaiset referenssikellojaksot ajoitussignaalien välillä ja työssä kehitetty referenssiä kierrättävä viivelinjarakenne rekistereineen interpoloi ajoitussignaalien paikat referenssikellojaksojen sisältä. Referenssinkierrätystekniikka hyödyntää lyhyttä viivelinjaa useampaan kertaan kellojakson aikana, mikä minimoi epälineaarisuuden interpoloinnissa. Sama rakenne mahdollistaa myös MHz-tason referenssitaajuuden, jolloin matalataajuista kidettä voidaan käyttää referenssilähteenä. Toinen interpolointitaso koostuu rinnakkaisista kapasitanssiskaalatuista viive-elementeistä, mitkä mahdollistavat alle porttiviiveen mittausresoluution. Rinnakkaisessa rakenteessa elementtien epälineaarisuudet eivät summaudu, mikä mahdollistaa pikosekuntitason mittaustarkkuuden. Väitöskirjatyössä suunniteltiin ja toteutettiin neljä aikavälinmittauspiiriä käyttäen 0,35 µm CMOS-teknologiaa, joista viimeisin, 7-kanavainen muunnin kykenee mittaamaan aikavälin useampaan pulssiin yhdellä kertaa sekä voi selvittää samalla pulssien leveydet tai nousuajat. Laseretäisyysmittauksessa monikanavaisuutta voidaan käyttää kun useita kaikuja lähetetystä pulssista saapuu vastaanottimeen sekä kompensoimaan mittauksessa esiintyviä muita virhelähteitä. Käytettäessä 20 MHz:n kidettä referenssilähteenä muunnin saavuttaa alle 9 ps:n interpolointiresoluution ja tarkkuuden ilman epälineaarisuudenkorjaustaulukoita. Työ osoittaa, että edullisella CMOS-teknologialla voidaan toteuttaa monipuolinen ja erittäin suorituskykyinen aika-digitaalimuunnin.

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

No description available.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

Cette thèse aborde le problème de génération d'horloge globale dans les SoCs complexes dans le contexte des technologies CMOS profondément submicroniques. Actuellement, afin de contourner les difficultés liées aux techniques classiques de distribution d'horloge (p.ex. arbre, grille) dans les systèmes synchrones, les concepteurs qui désirent de se rendre sur le paradigme Synchronisation Globale se tournent vers les techniques de synchronisation rompant avec les approches classiques (par exemple oscillateurs distribués, les ondes stationnaires , oscillateurs couplés, les retards programmables). Cette étude s'inscrit dans ce courant. Dans ce travail, nous avons étudié et mis au point un système de génération d'horloge sur puce destiné à un SoC synchrone de haute fiabilité. Cette architecture est basée sur un réseau d'oscillateurs couplés en phase et en fréquence à l'aide d'un réseaux de boucles à verrouillage de phase tout numériques (ADPLLs). Pendant cette recherche nous avons mis au point les spécifications et choisi une architecture de réseau. Un modèle théorique du système a été mis en place en collaboration avec CEA-LETI et Supélec dans le cadre du projet ANR HODISS. Nous avons analysé le comportement du système dans les simulations sur différents niveaux d'abstraction, en enquêtant des conditions de stabilité de son fonctionnement synchrone. L'ADPLL a été proposé comme un nœud élémentaire du réseau de synchronisation distribuée. L'utilisation d'ADPLL permet de contourner les difficultés d'implémentation, qui sont généralement associées à PLL analogique. Nous avons conçu les blocs principaux de l'ADPLL: un oscillateur à commande numérique (Digitally-Controlled Oscillator, DCO), un détecteur de phase/fréquence (PFD) et un bloc de traitement d'erreur. Une technique de conception basée sur les cellules a été adapté pour le développement d'oscillateur. Cette technique réduit considérablement la complexité de l'implémentation de l'oscillateur. Les autres blocs ont été conçus en utilisant un flot de conception numérique commun. Afin de réduire les risques associés à l'implémentation de silicium, le système a été validé dans une plate-forme de prototypage FPGA. Les résultats des mesures ont montré que la synchronisation de réseau se comporte comme prédit par la théorie et ainsi que les simulations. Deux circuits de prototypage ont été conçus, mis en œuvre et testés dans une technologie CMOS 65 nm de STMicroelectronics. La première puce est une preuve de concept d'un DCO conçu très linéaire et monotone. Les paramètres mesurés de l'oscillateur sont conformes aux spécifications. La performance mesurée a démontré une gigue de moins de 15 ps rms, en consommant 6.2 mW/GHz @ 1.1 V. La plage de réglage de l'oscillateur est 999-2480 MHz avec une résolution de 10 bits. La deuxième puce est un réseau d'horloge avec 4x4 nœuds qui se compose de 16 ADPLLs distribués. Chacun d'entre eux utilise les blocs conçu précédemment: DCO, PFD et bloc de traitement d'erreur. Les expérimentes ont montré que la technique proposée de génération d'horloge distribuée est réalisable sur une puce réelle CMOS. La performance mesurée démontre l'erreur de synchronisation entre les oscillateurs voisins moins de 60 ps, alors que la consommation d'énergie est 98.47 mW/GHz.

No description available.

This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.