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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
121

Circuit design and hardware implementation of an analog synthesizer

Murhed, Olle January 2023 (has links)
Since the heyday of analogue synthesizers in the 70's, they have largely been replaced by digital hardware and software synthesizers. However, in recent years, there has been a revival in analogue designs, possibly due to its ``warmer" sound. This projects aims to take part of this renewal by building a simple analogue synth design with the most basic modules (e.g. oscillators, filters, mixers, amplifier), accompanied by a step sequencer for programming melodies. This will be done by designing circuits and implementing them on breadboards. The circuits were designed with inspiration from various online resources, along with theoretical analysis and simulation software for complex circuitry. The result is a fully functional synthesizer with four sawtooth oscillators. The only modules missing from the initial design are battery support and a line out output for recording the output of the synthesizer. The pitch specification was met as the oscillator did not differ from the expected frequency by more than $\pm$15 cents (hundredths of a semitone), for a range of five octaves. Some possible improvements include better step sequencer user friendliness by installing a display to indicate the notes, more robustness by implementing the synth on a circuit board instead of breadboard. Some improvements can be made for the synth. For example, a display for the step sequencer would facilitate melody programming. Moreover, implementing the synth on a circuit board instead of breadboards would greatly improve robustness and reduce the risk of sound disruptions.
122

Design of a Low Power Fractional-N PLL Frequency Synthesizer in 65nm CMOS

Chaille, Jack Ryan 23 May 2022 (has links)
No description available.
123

The Design, Building, and Testing of a Constant on Discreet Jammer for the IEEE 802.15.4/ZIGBEE Wireless Communication Protocol

Marette, Alexandre J 01 June 2018 (has links) (PDF)
As wireless protocols become easier to implement, more products come with wireless connectivity. This latest push for wireless connectivity has left a gap in the development of the security and the reliability of some protocols. These wireless protocols can be used in the growing field of IoT where wireless sensors are used to share information throughout a network. IoT is being implemented in homes, agriculture, manufactory, and in the medical field. Disrupting a wireless device from proper communication could potentially result in production loss, security issues, and bodily harm. The 802.15.4/ZigBee protocol is used in low power, low data rate, and low cost wireless applications such as medical devices and home automation devices. This protocol uses CSMA-CA (Carrier Sense Multiple Access w/ Collision Avoidance) which allows for multiple ZigBee devices to transmit simultaneousness and allows for wireless coexistence with the existing protocols at the same frequency band. The CSMA-CA MAC layer seems to introduce an unintentional gap in the reliability of the protocol. By creating a 16-tone signal with center frequencies located in the center of the multiple access channels, all channels will appear to be in use and the ZigBee device will be unable to transmit data. The jamming device will be created using the following hardware implementation. An FPGA connected to a high-speed Digital to Analog Converter will be used to create a digital signal synthesizer device that will create the 16-tone signal. The 16-tone signal will then be mixed up to the 2.4 GHz band, amplified, and radiated using a 2.4 GHz up-converter device. The transmitted jamming signal will cause the ZigBee MAC layer to wait indefinitely for the channel to clear. Since the channel will not clear, the MAC layer will not allow any transmission and the ZigBee devices will not communicate.
124

Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation

Tiagaraj, Sathya Narasimman 27 September 2016 (has links)
No description available.
125

Frequency Synthesis for Cognitive Radio Receivers and Other Wideband Applications

Zahir, Zaira January 2017 (has links) (PDF)
The radio frequency (RF) spectrum as a natural resource is severely under-utilized over time and space due to an inefficient licensing framework. As a result, in-creasing cellular and wireless network usage is placing significant demands on the licensed spectrum. This has led to the development of cognitive radios, software defined radios and mm-wave radios. Cognitive radios (CRs) enable more efficient spectrum usage over a wide range of frequencies and hence have emerged as an effective solution to handle huge network demands. They promise versatility, flex-ability and cognition which can revolutionize communications systems. However, they present greater challenges to the design of radio frequency (RF) front-ends. Instead of a narrow-band front-end optimized and tuned to the carrier frequency of interest, cognitive radios demand front-ends which are versatile, configurable, tun-able and capable of transmitting and receiving signals with different bandwidths and modulation schemes. The primary purpose of this thesis is to design a re-configurable, wide-band and low phase-noise fast settling frequency synthesizer for cognitive radio applications. Along with frequency generation, an area efficient multi-band low noise amplifier (LNA) with integrated built-in-self-test (BIST) and a strong immunity to interferers has also been proposed and implemented for these radios. This designed LNA relaxes the specification of harmonic content in the synthesizer output. Finally some preliminary work has also been done for mm-wave (V-band) frequency synthesis. The Key Contributions of this thesis are: A frequency synthesizer, based on a type-2, third-order Phase Locked Loop (PLL), covering a frequency range of 0.1-5.4 GHz, is implemented using a 0.13 µm CMOS technology. The PLL uses three voltage controlled oscillators (VCOs) to cover the whole range. It is capable of switching between any two frequencies in less than 3 µs and has phase noise values, compatible with most communication standards. The settling of the PLL in the desired state is achieved in dynamic multiple steps rather than traditional single step settling. This along with other circuit techniques like a DAC-based discriminator aided charge pump, fast acquisition pulse-clocked based PFD and timing synchro-negation is used to obtain a significantly reduced settling time A single voltage controlled LC-oscillator (LC-VCO) has been designed to cover a wide range of frequencies (2.0-4.1 GHz) using an area efficient and switch-able multi-tap inductor and a capacitor bank. The switching of the multi-tap inductor is done in the most optimal manner so as to get good phase-noise at the output. The multi-tap inductor provides a significant area advantage, and in spite of a degraded Q, provides an acceptable phase noise of -123 dBc/Hz and -113 dBc/Hz at an offset of 1 MHz at carrier frequencies of 2 and 4 GHz, respectively. Implemented in a 0.13 µm CMOS technology, the oscillator with ≈ 69 % tuning range, occupies an active area of only 0.095 mm2. An active inductor based noise-filter has been proposed to improve the phase-noise performance of the oscillator without much increase in the area. A variable gain multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (0.8 GHz to 2.4 GHz) using an area efficient switchable-π network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip Built-in-Self-Test (BIST) circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (I I P3) ranges from -15 dBm to 0 dBm. Implemented in a 0.13 µm CMOS technology, the LNA occupies an active area of about 0.29 mm2. Three different types of VCOs (stand-alone LC VCO, push-push VCO and a ring oscillator based VCO) for generating mm-wave frequencies have been implemented using 65-nm CMOS technology and their measured results have been analyzed
126

L'impact des changements technologiques sur le travail de Paul Baillargeon dans la série Star Trek

Gauthier, François R. 12 1900 (has links)
La version intégrale de ce mémoire est disponible uniquement pour consultation individuelle à la Bibliothèque de musique de l’Université de Montréal (www.bib.umontreal.ca/MU). / Le compositeur canadien Paul Baillargeon a réalisé la musique de plus de quarante épisodes des séries télévisées Star Trek, maintenant traduites et diffusées à travers le monde. Star Trek est l’une des dernières séries télévisuelles américaines ayant utilisé un orchestre symphonique d’envergure avant que ses principaux compositeurs réalisent eux-mêmes leurs bandes sonores à l’aide d’ordinateurs et d’échantillons numériques, remplaçant ainsi la cinquantaine de musiciens qui perpétuait la tradition acoustique de la production musicale à Hollywood. Non seulement ces outils influencent-ils la musique de Paul Baillargeon, mais ils transforment aussi son travail au sein de la postproduction des populaires séries télévisées. Ce regard microscopique sur l’influence des technologies musicales dans la création télévisuelle s’inscrit dans un contexte plus vaste qui concerne les transformations culturelles et sociales issues des rapides progrès technologiques auxquelles nous assistons depuis deux décennies. / Canadian composer Paul Baillargeon wrote the music for more than forty television shows for the Star Trek series, now translated and broadcasted around the world. Star Trek was one of the last television series produced by a complete symphonic orchestra when Paul Baillargeon started using computers and digital samples, thereby replacing those musicians that were perpetuating Hollywood’s acoustical tradition. Not only do these tools affect the music of Paul Baillargeon, they also transform his work among the postproduction team of the popular television series. This close look at how musical technology influences composition and music production for that particular composer is part of a vast context in which technological progress has transformed our cultural and social fields for the past two decades.
127

Frequency Synthesis in Wireless and Wireline Systems

Turker, Didem 1981- 14 March 2013 (has links)
First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.
128

High performance continuous-time filters for information transfer systems

Mohieldin, Ahmed Nader 30 September 2004 (has links)
Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications.
129

Spectrum Sensing Receivers for Cognitive Radio

Khatri, Vishal January 2016 (has links) (PDF)
Cognitive radios require spectral occupancy information in a given location, to avoid any interference with the existing licensed users. This is achieved by spectrum sensing. Existing narrowband, serial spectrum sensors are spectrally inefficient and power hungry. Wideband spectrum sensing increases the number of probable fre-quency candidates for cognitive radio. Wideband RF systems cannot use analog to digital converters (ADCs) for spectrum sensing without increasing the sampling rate and power consumption. The use of ADCs is limited because of the dynamic range of the signals that need to be sampled and the frequency of operation. In this work, we have presented a CMOS based area efficient, dedicated and scalable wideband parallel/serial spectrum sensor for cognitive radio. The key contributions of the thesis are: 1. An injection locked oscillator cascade (ILOC) for parallel LO synthesis. An area-efficient, wideband RF frequency synthesizer, which simultaneously gen-erates multiple local oscillator (LO) signals, is designed. It is suitable for parallel wideband RF spectrum sensing in cognitive radios. The frequency synthesizer consists of an injection locked oscillator cascade where all the LO signals are derived from a single reference oscillator. The ILOC is implemented in a 130-nm technology with an active area of 0.017 mm2. It generates 4 uni-formly spaced LO carrier frequencies from 500 MHz to 2 GHz. 2. A wideband, parallel RF spectrum sensor for cognitive radios has been de-signed. This spectrum sensor is designed to detect RF occupancy from 250 MHz to 5.25 GHz by using an array of CMOS receivers with envelope detec-tors. A parallel LO synthesizer is implemented as an ILOC. The simulated sensitivity is around -25 dBm for 250 MHz wide bandwidth. 3. A mitigation technique for harmonic downconversion in wideband spectrum sensors. The downconversion of radio frequency (RF) components around the harmonics of the local oscillator (LO), and its impact on the accuracy of white space detection using integrated spectrum sensors, is (are) studied. We propose an algorithm to mitigate the impact of harmonic Down conversion by utilizing multiple parallel downconverters in the system architecture. The proposed algorithm is validated on a test-board using commercially avail-able integrated circuits (IC) and a test-chip implemented in a 130-nm CMOS technology. The measured data shows that the impact of the harmonic down-conversion is closely related to the LO characteristics, and that much of it can be mitigated by the proposed technique. 4. A wideband spectrum sensor for narrowband energy detection. A wideband spectrum sensing system for cognitive radio is designed and implemented in a 130-nm RF mixed-mode CMOS technology. The system employs an I-Q downconverter, a pair of complex filters and a pair of envelope detectors for energy detection. The spectrum sensor works from 250 MHz to 3.25 GHz. The design makes use of the band pass nature of the complex filter to achieve two objectives : i) Separation of upper sideband (USB) and lower sideband (LSB) around the local oscillator (LO) signal and ii) Resolution of smaller bands within a large detection bandwidth. The measured sensitivity is close to -45 dBm for a single tone test over a bandwidth of 40 MHz. The measured Image reject ratio (IRR) is close to 30 dB. The overall sensing bandwidth is 3.5 GHz and the overall wideband detection bandwidth is 250 MHz which is partitioned into 40 MHz narrowband chunks with 8 such overlapping chunks.
130

Digitální elektronický hudební syntezátor s analogovým řízením pro platformu Eurorack / Digital Musical Synthesizer with Analog Control for Eurorack Platform

Klecl, Martin January 2019 (has links)
This work explores the topic of digital audio signal processing for modular synthesizers and the design of digital oscillator for modular standard known as Eurorack. Introduction of the theoretical part is dedicated to basic terms and blocks used in modular synthesizers. The thesis also characterizes and presents the methods of sound synthesis. The second part of the theory concerns analog and digital signal conversion made by digital signal processors DSP, focusing on ARM with focus on ARM architecture. The practical part of the thesis concerns design and construction of the digital oscillator which generates periodic waveforms without aliasing distortion. The oscillator also allows several types of modulations and waveforming and the module has several inputs for connecting control voltages or external audio signals.

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