Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized. / Master of Science

Modulära synthesizers blev en stor kommerciell succé in på 1960-talet som sedan in på 2010-talet skulle få uppmärksamhet på nytt, troligtvis i samband med en "Do it yourself-rörelse" (DIY-movement). En sampler är ett instrument som finns både självständigt och som styrspänningskontrollerad modul inom modulärsyntes. Vanligt är att vissa aspekter till uppspelning går att kontrollera med styrspänning, exempelvis uppspelningshastigheten. Något varken jag eller min handledare har sett tidigare är direktåtkomst med styrspänning till minnespekare i en ljudbuffer för samplermoduler. Därför implementerade jag The Buffer, en samplermodul i en virtuell modulärsyntesmiljö - VCV Rack. I arbetet undersökte jag två frågeställningar: kopplingen mellan inspänningen till modulen och det resulterande ljudet, samt även vilket maximalt minnesområde som går att adressera för styrspänningen så att pekarna sveper konsekutivt genom varje frame av ljudspåret. I den senare utforskade jag två möjliga svar, ett teoretiskt största möjliga, och ett med utgångspunkt i min implementation. Jag utförde även en användarstudie på mer subjektiv basis för en indikation på modulens användbarhet.

Det här arbetet diskuterar ett utforskande musikaliskt gestaltningsprojekt, Från botten av en brunn, som utgörs av fyra satser för klarinett, cello och modulärt synthesizersystem baserat på var sin person ur den japanska författaren Haruki Murakamis roman Kafka på stranden (Umibe no Kafuka, 海辺のカフカ) från 2002. Arbetet har utgått ifrån en metodisk bearbetning av romantexten med hjälp av grundad teori för att skapa både syntetiska och samplade klanger och komposition ur texten. Grundad teori togs ursprungligen fram inom sociologi för att forma ny kunskap ur kvalitativ data med hjälp av en rigorös process, där teoretisk känslighet stödjer och vägleder tolkningar. I mitt arbete har det här snarare handlat om estetisk sensibilitet som väglett mina tolkningar av texten, hjälpt mig att göra urval och omforma romanen till musik och framförande. / This work discusses an exploratory musical composition project, From the bottom of a Well, which consists of four movements for clarinet, cello, and modular synthesizer system, where each movement is based on each person from the Japanese author Haruki Murakami's novel Kafka on the beach (Umibe no Kafuka, 海辺のカフカ) from 2002. The work has been based on a methodical processing of the novel text with the help of grounded theory to create both synthetic and sampled sounds and composition from the text. Grounded theory was originally developed in sociology to shape new knowledge from qualitative data using a rigorous process, where theoretical sensitivity supports and guides interpretations. In my work, this has rather been about aesthetic sensibility that has guided my interpretations of the text, helped me to make selections, and to transform the novel into a music composition and a performance.

Osciladores Controlados por Tensão (VCOs - Voltage-Controlled Oscillators) são circuitos de grande importância em sistemas de comunicação por radiofrequência atuais. Muitos trabalhos de pesquisa recentes têm focado no desenvolvimento de VCOs para aplicações em uma faixa muito grande de frequências (isto é, suportando amplo tunning range). O desenvolvimento de VCOs com uma ampla faixa de sintonia tem motivação na abertura de bandas de frequência, que até pouco tempo estavam licenciadas apenas para usos específicos, porém agora estão também abertas para a utilização de sistemas de rádios cognitivos. A ideia é que o rádio cognitivo tenha recursos para detectar se um canal (ou faixa de frequência) está sendo usado e, em caso de o canal não estar sendo usado, o rádio cognitivo deve se reconfigurar para operar nesse canal. Desse modo, os rádios cognitivos devem possuir um alto grau de reconfigurabilidade, de forma que possam operar em uma faixa muito ampla de frequências. Esse requisito exige o uso de de VCOs com um amplo tunning range. Este trabalho apresenta um projeto completo de um LC-VCO com uma larga faixa de frequência de operação (widedand). Um amplo tunning range foi obtido a partir do chaveamento (ou programação) do valor da capacitância total do tanque-LC do VCO, gerando assim várias sub-bandas de frequência. O ganho do VCO (KVCO) manteve-se com pequenas variações para todas as subbandas de frequência, com um valor médio de 88.6MHz, sendo 112MHz e 80MHz os valores máximo e mínimo, respectivamente. O ruído de fase variou de -118.4dBc/Hz a -107.4dBc/Hz para as portadores em 3.7GHz e 8.1GHz, respectivamente, enquanto que a potência dissipada do circuito LC-VCO variou de 1.8mW a 5.6mW para todo o tunning range. Para a figura de mérito power-frequency-tunning-normalized (FOMPFTN), os valores obtidos foram na faixa 3.1dB e 11.2dB, comparáveis com a maioria dos trabalhos publicados na área. / Voltage-Controlled Oscillators (VCOs) are very important circuits in current radio frequency communication systems. Much research has been focused recently on developing wideband VCOs in CMOS. The motivation on wideband VCOs is based on the opening of frequency bands, which until recently were licensed for specific uses, for use by cognitive radio systems. The idea is that cognitive radio must have the ability to detect whether a channel (or frequency band) is being used and if the channel is not being used, the cognitive radio must reconfigure itself to operate on that channel. Thus, cognitive radios should possess a high degree of reconfigurability, so that they can operate in a very wide frequency range. This requires the use of VCOs with a wide tunning range. This work presents a complete design of a LC-VCO with a wide operating frequency range (widedand). A wide tunning range has been obtained from the switching (or programming) the value of the total capacitance of the LC-tank of the VCO, thereby generating multiple frequency sub-bands. The VCO gain (KVCO) was maintained with small variations for all frequency sub-bands, with an average value of 88.6MHz, with 80MHz and 112MHz for the minimum and maximum values, respectively. The phase noise ranged from -118.4dBc/Hz to -107.4dBc/Hz for carriers at 3.7GHz and 8.1GHz, respectively, while the power dissipated in the LC-VCO circuit ranged from 1.8mW to 5.6mW for all tunning range. For the figure of merit power-frequency-tuning-normalized (FOMPFTN), the results were in the 3.1dB to 11.2dB range, comparable to most recently published works.

The invention of the synthesizer meant the possibility of achieving virtually any sound in one mechanism, a superbly convenient device for musical creativity. Perhaps the perfect space for this approval of sound creativity was in the modern electronic film score. The synthesizer also flourished in popular music immediately following its emergence, but a common form began to solidify itself among synthesizer music. Shortly after, improvements in electronic instrument technology led to the democratization of electronic music and equipment, ultimately leading to electronic music as the new mainstream.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

A fully integrated, fast-locking fractional-N frequency synthesizer is proposed and demonstrated in this work. In this design, to eliminate the need for large, inaccurate capacitors and resistors in a loop filter, an analog continuous-time loop filter whose performance is sensitive to process and temperature variations and aging has been replaced with a programmable digital Finite Impulse Response (FIR) filter. In addition, using the adaptive loop gain control proportional to the frequency difference, the frequency-locking time has been reduced. Also, the phase noise and spurs have been reduced by a Multi-stAge noise SHaping (MASH) controlled Fractional Frequency Detector (FFD) that generates a digital output corresponding directly to the frequency difference. The proposed frequency synthesizer provides many benefits in terms of high integration ability, technological robustness, fast locking time, low noise level, and multimode flexibility. To prove performance of the proposed frequency synthesizer, the frequency synthesizers analysis, design, and simulation have been carried out at both the system and the circuit levels. Then, the performance was also verified after fabrication and packaging.

In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset. Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.