Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction. At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145. Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC. Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave. HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.

<p>Advancements of the semiconductor technology opened a new era in</p> <p>wireless communications which led manufacturers to produce faster,</p> <p>more functional devices in much smaller sizes. However, testing</p> <p>these devices of today's technology became much harder and expensive</p> <p>due to the complexity of the devices and the high operating speeds.</p> <p>Moreover, testing these devices becomes more important since decreasing</p> <p>feature sizes increase the probability of parametric and catastrophic</p> <p>faults because of the severe effects of process variations. Manufacturers</p> <p>have to increase their test budgets to address quality and reliability</p> <p>concerns. In the radio frequency (RF) domain, overall test cost are higher</p> <p>due to equipment costs, test development and test time costs. Advanced</p> <p>circuit integration, which integrates various analog and digital circuit</p> <p>blocks into single device, increases test costs further because of the</p> <p>additional tests requiring new test setups with extra test equipments.</p> <p>Today's RF transceiver circuits contain many analog and digital circuit</p> <p>blocks, such as synthesizers, data converters and the analog RF front-end</p> <p>leading to a mixed signal device. Verification of the specifications and</p> <p>functionality of each circuit block and the overall transceiver require</p> <p>RF instrumentation and lengthy test routines. In this dissertation, we</p> <p>propose efficient component and system level test methods for RF</p> <p>transceivers which are low cost alternatives to traditional tests.</p> <p>In the first component level test, we focus on in-band phase noise of the</p> <p>phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at</p> <p>measuring the timing jitter that may require precise reference clocks and/or</p> <p>additional computation of measured specs. We propose a built in test (BiT)</p> <p>circuit to perform a go/no-go test for in-band PLL phase noise. The proposed</p> <p>circuit measures the band-limited noise power at the input of the voltage</p> <p>controlled oscillator (VCO). This noise power is translated as the high</p> <p>frequency in-band phase noise at the output of the PLL. Our circuit contains</p> <p>a self calibration sequence based on a simple sinusoidal input signal to make</p> <p>it robust with respect to process variations.</p> <p>The second component level test is a built in self test (BiST) scheme</p> <p>proposed for analog to digital converters (ADC) based on a linear ramp</p> <p>generator and efficient output analysis. The proposed analysis method is</p> <p>an alternative to histogram based analysis techniques to provide test time</p> <p>improvements, especially when the resources are scarce. In addition to the</p> <p>measurement of differential nonlinearity (DNL) and integral nonlinearity</p> <p>(INL), non-monotonic behavior of the ADC can also be detected with the</p> <p>proposed technique. The proposed ramp generator has a high linearity</p> <p>capable of testing 13-bit ADCs.</p> <p>In the proposed system level test methods, we utilize the loop-back</p> <p>configuration to eliminate the need for an RF instrument. The first loop-back</p> <p>test method, which is proposed for wafer level test of direct conversion</p> <p>transceivers, targets catastrophic and large parametric faults. The use of</p> <p>intermediate frequencies (IF) generates a frequency offset between the transmit</p> <p>and receive paths and prevents a direct loop-back connection. We overcome this</p> <p>problem by expanding the signal bandwidth through saturating the receive path</p> <p>composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the</p> <p>receiver path is determined, complete transceiver can be tested for catastrophic</p> <p>signal path faults by observing the output signal. A frequency spectrum</p> <p>envelope signature technique is proposed to detect large parametric faults.</p> <p>The impact of impairments, such as transmitter receiver in-phase/quadrature</p> <p>(I/Q) gain and phase mismatches on the performance have become severe due to</p> <p>high operational speeds and continuous technology scaling. In the second system</p> <p>level loop-back test method, we present BiST solutions for quadrature modulation</p> <p>transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian</p> <p>minimum shift keying (GMSK) baseband modulation schemes. The BiST methods</p> <p>use only transmitter and receiver baseband signals for test analysis. The</p> <p>mapping between transmitter input signals and receiver output signals are</p> <p>used to extract impairment and nonlinearity parameters separately with the</p> <p>help of signal processing methods and detailed nonlinear system modeling.</p> <p>The last system level test proposed in this dissertation combines the benefits </p> <p>of loop-back and multi-site test approaches. In this test method, we present </p> <p>a 2x-site test solution for RF transceivers. We perform all operations on </p> <p>communication standard-compliant signal packets, thereby putting the device </p> <p>under the normal operating conditions. The transmitter on one device under </p> <p>test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX </p> <p>path. Parameters of the two devices are decoupled from one another by carefully </p> <p>modeling the system into a known format and using signal processing techniques.</p> / Dissertation

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this thesis, we develop a novel PTL synthesizer that can efficiently generate PTL-based circuits. We proposed a new synthesis method (hybrid PTL/CMOS Library design) that has multiple driving strengths and multiple threshold voltages to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flow employs the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS logic cells. Thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow.

The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity.

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.

This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

This thesis presents the CMOS integer-N frequency synthesizer for 2 GHz 802.11 WLAN applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, and a pulse-swallow counter. In pulse-swallow counter, we use less numbers of transistors divide-by-2/3 prescaler to work in high frequency in order to reduce power consumption. We complete the design of pulse-swallow counter for 2-GHz (seven channels) and the 5-GHz (four channels) application. The average power consumption of pulse-swallow counter is 2.49 mW and 2.98 mW for 2-GHz and 5-GHz application respectively. We use Verilog-A language to complete VCO behavior model for frequency synthesizer and utilize the Spectre simulation results justify the feasibility of our proposed frequency synthesizer. The total power consumption of frequency synthesizer is 3.432mW and 4.673mW for 2-GHz and 5-GHz frequency synthesizer, respectively.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy