This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer. The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can. Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.

Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.

This thesis investigates techniques for stealth hydroacoustic communication using spread spectrum. The Swedish naval defense organisations have a vision that all their units should be able to communicate with each other, even between underwater vehicles. But the properties of water makes it a complex channel to use for wireless communications. Radiomagnetic waves have very limited range in water, therefore acoustic waves are used. In this report the basics of wireless communication systems are described including source coding, channel coding, modulation techniques as well as different techniques for spread spectrum. The fundamental principle for all spread spectrum systems is to use more bandwidth than necessary to spread the signal energy in the frequency spectrum. This limits the data rate but results in a robust communication link which is difficult to detect, intercept and to jam. In addition to the theoretical background, this thesis also gives a brief description of a Matlab system and a VHDL-system that was developed during the project. Finally the results of this project are presented and some suggestions of further developments are given.

This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow.

In this thesis, a new way of using predisortion for linearization of power amplifiers is evaluated. In order to achieve an adequate power level for the jamming signal, power amplifiers are used in military jamming systems. Due to the nonlinear characteristic of the power amplifier, distortion will be present at the output. As a consequence, unwanted frequencies are subject to jamming. To decrease the distortion, linearization of the power amplifier is necessary. In the system of interest, a portion of the distorted power amplifier output signal is fed back. Using this measurement, a predistortion signal is synthesized to allow suppression of the unwanted frequency components. The predistortion signal is updated a number of times in order to achieve a good outcome. Simulations are carried out in Matlab for testing of the algorithm. The evaluation of the new linearization technique shows promising results and that good suppression of distortion components is achieved. Furthermore, new predistortion features are possible to implement, such as predistorsion in selected frequency bands. However, real hardware testing needs to be carried out to confirm the results.

The evolving technology has over the past decade contributed to a bandwidth explosion on the Internet. This makes it interesting to look at the development of the workhorses of the Internet, the core routers. The main objective of this project is to develop a 16 port gigabit core router architecture using intellectual property (IP) blocks and a SoCBUS on-chip interconnection network. The router architecture will be evaluated by making simulations using the SoCBUS simulation environment. Some changes will be made to the current simulator to make the simulations of the core router more realistic. By studying the SoCBUS network load the bottlenecks of the architecture can be found. Changes to the router design and SoCBUS architecture will be made in order to boost the performance of the router. The router developed in this project can under normal traffic conditions handle a throughput of 16x10Gbit/s without dropping packets. This core router is good enough to compete with the top of the line single-chip core routers on the market today. The advantage of this architecture compared to others is that it is very flexible when it comes too adding new functionality. The general on-chip network also reduces the design time of this system.

This master thesis has been done at Enea Epact AB. The purpose of this thesis is to develop and implement a Link Quality Control algorithm for GPRS/EPGRS in the current testing tool. A Link Quality Control (LQC) shall take quality values from mobile stations and base stations and decide a codingsscheme that opimizes the throughput of data. The Advantage with LQC is that it adapts the used coding scheme to the channel quality. If the channel quality is too bad for the used coding scheme, a slower coding scheme with more redundancy should be selected. On the other hand, if the channel quality is too good for the used coding scheme, LQC should recommend a faster coding scheme with less redundancy. The testing tool is now using a static coding schme that doesn’t change during a data session. An LQC is therefore necessary for better simulation of the traffic and to make the tests more real.

The purpose behind this thesis is to develop a software (SceneServer) that can generate data such as images and vertex lists from computer models. These models are placed in a virtual environment and they can be controlled either from a graphical user interface (GUI) or from a MATLAB client. Data can be retrieved and processed in MATLAB. By creating a connection between MATLAB and a 3D environment, computer vision algorithms can be designed and tested swiftly, thus giving the developer a powerful platform. SceneServer allows the user to manipulate, in detail, the models and scenes to be rendered. MATLAB communicates with the SceneServer application through a Java library, which is connected to an interface in SceneServer. The graphics are visualised using Open Scene Graph (OSG) that in turn uses OpenGL. OSG is an open source cross-platform scene graph library for visualisation of real-time graphics. OpenGL is a software interface for creating advanced computer graphics in 2D and 3D.

This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.

Contrast-enhanced magnetic resonance angiography (MRA) is used to obtain images showing the vascular system. To detect stenosis, which is narrowing of for example blood vessels, maximum intensity projection (MIP) is typically used. This technique often fails to demonstrate the stenosis if the projection angle is not suitably chosen. To improve identification of this region a color-coding algorithm could be helpful. The color should be carefully chosen depending on the vessel diameter. In this thesis a segmentation to produce a binary 3d-volume is made, followed by a distance transform to approximate the Euclidean distance from the centerline of the vessel to the background. The distance is used to calculate the smallest diameter of the vessel and that value is mapped to a color. This way the color information regarding the diameter would be the same from all the projection angles. Color-coded MIPs, where the color represents the maximum distance, are also implemented. The MIP will result in images with contradictory information depending on the angle choice. Looking in one angle you would see the actual stenosis and looking in another you would see a color representing the abnormal diameter.