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Nanoporous GaN films are prepared by UV assisted electrochemical etching using HF solution as an electrolyte. To assess the optical quality and morphology of these nanoporous films, micro-photoluminescence (PL), micro-Raman scattering, scanning electron microscopy (SEM), and atomic force microscopy (AFM) techniques have been employed. SEM and AFM measurements revealed an average pore size of about 85-90 nm with a transverse dimension of 70-75 nm. As compared to the as-grown GaN film, the porous layer exhibits a substantial photoluminescence intensity enhancement with a partial relaxation of compressive stress. Such a stress relaxation is further confirmed by the red shifted E₂(TO) phonon peak in the Raman spectrum of porous GaN. / Singapore-MIT Alliance (SMA)

With the raise of nanotechnology researching, many special physical and chemical properties were found gradually in nanoscale. Among them, the one-dimension nanostructure owns high specific surface area and excellent electron emission properties. Moreover, the two-dimension arrayed nanostructure has the characteristics of photonic crystal and moth-eye effect. Currently, advanced lithographic methods such as electron beam (E-beam) or deep ultraviolet (DUV) lithography and X-ray lithography are adopted to define periodic nanoscale patterns. But these lithographic equipment are too expensive. Moreover, costly etching methods such as inductively coupled plasma reactive ion etching (ICP-RIE) or electron cyclotron resonance reactive ion etching (ECR-RIE) must be used to form arrayed silicon nanostructure with high aspect ratios. The nanoscale array patterns can be defined on the surface of the silicon wafer by the self-assembly of a polystyrene nanosphere. The photo-assisted electrochemical etching (PAECE) has the advantage of forming nanopore, and the aspect ratio of etched nanopores can be as high as 50:1 which is better than ICP-RIE. Therefore, PAECE is very suitable to fabricate nanostructure. This high-cost drawback makes most of academias and small/medium enterprises hard to invest in nanotechnology. This study combines the self-assembly nanosphere lithography (SANSL) process and photo-assisted electrochemical etching to fabricate a nanostructure array with a high aspect ratio on the surface of a silicon wafer. Experimental results show that the nanosphere array with a nearly perfect arrangement can be obtained in the sample of 1.8 ∗1.8 cm2 by spin coating and vibration coating. Using reactive ion etching (RIE) can transfer the nanosphere array pattern to the silicon nitride layer, and form the etching window of PAECE. The concentration of the HF electrolyte used in PAECE was 2.5 wt%. When PAECE was performed with etching mask can produce deeper and periodic nanopores. The surfactant of SDSS added in the HF electrolyte of PAECE can reduce the contact angle of electrolyte and avoid the phenomenon of hole-reaming. When the voltage of 1 V is used to etch for 12.5 min, the etching depth of the nanopore array structure is about 5.69 £gm and its diameter is about 90 nm, such that the aspect ratio of the pore can reach about 63:1. If the etching voltage was increased, the width of pore will be increased and the depth of pore will be reduced gradually at the same time. When the etching voltage of 2 V is applied to etch for 5 min, the etching height of the nanopillar is about 2 £gm and its diameter is about 100 nm, such that the aspect ratio of the pillar can reach about 20:1. The nanopillar was arranged periodically according to the definition of nanosphere, therefore the arrayed nanopillar can be realized successfully. Dropping the solution which has biological samples into the gap of nanopillar, it will affect the light which goes through the nanostructure and produce specific parameters of polarization. The results showed that when the DI water was dropped into the nanopillar structure, the degree of polarization (DOP) is 0.981, azimuth is 4.86¢X and ellipticity is 2.83¢X. When the solution which has alkaline lysis plasmid of 5 £gg/ml was dropped into the nanopillar structure, the DOP is 0.957, azimuth is 7.7¢X and ellipticity is 3.99¢X. The result shows that the change of polarization parameter has the relations with the concentration of biological samples in solution. Therefore, the measure system can be combined with nanopillar array to develop the photonic crystal biosensor. This study also applies the developed nanopore nanostructure array to fabricate sub-wavelength antireflection structure of solar cell. Experimental results show that the deeper in structure and then the better in antireflective effect. After performing 1 V PAECE for 5 min, the weighted mean reflectance can be reduced to 1.73% under the wavelength range of 280¡V890 nm. Further coating of a silicon nitride layer on the surface of a nanostructure array reduces the weighted mean reflectance even to 0.878 %. Finally, this study also uses various voltage of PAECE to produce nanostructure array with different surface area for the electrode fabrication of fuel cell. Experimental results show that the larger in surface area of sample and then the better in catalysis effect. Two-staged PAECE of 1.5 V and 1.75 V can yield nanopillar with surface area of 14.2 cm2 , which is about 50.2 times higher than a planar electrode. When the surface of such a nanopillar array is coated with platinum of 1000 Å, the reaction current of nanopillar array is 10.2 mA, which is 72.9 times higher than that obtained by only a planar electrode.

Ces travaux de thèse ont pour but l’évaluation et le développement de briques technologiques en silicium poreux répondant à la problématique de l’intégration monolithique 3D rattachée au concept du “more than Moore” : d’une part l’intégration sur silicium de composants passifs RF, d’autre part, la réalisation de chemins traversants d’interconnexion à fort facteur d’aspect par voie électrochimique. Dans un premier temps, différents substrats mixtes silicium / silicium poreux sont réalisés. Des inductances en cuivre, réalisées sur un substrat mésoporeux de 200 µm de profondeur et de porosité proche de 60%, atteignent des facteurs de qualité à 20 GHz jusqu’à 55% supérieurs à ceux mesurés sur silicium massif. Une perspective d’industrialisation de ce type d’application est à l’étude dans le cadre d’une thèse CIFRE. La gravure de matrices de pores à fort facteur d’aspect, bien qu’encore difficilement localisable en termes de qualité de périphérie, fait d’autre part l’objet de développements, notamment pour la fabrication de condensateurs à haute densité capacitive et de contacts d’interconnexions en cuivre. / Those thesis works deal with the evaluation and the development of porous silicon technological step in order to answer some of the monolithic integration challenges bring by the “more than Moore” problematic in microelectronics industry: on one hand, the integration on silicon of passive RF devices, on the other hand, realization by electrochemical etching of through silicon via. In a first time, several mixed porous silicon / silicon substrat are realized. Copper inductors, realized on 200 µm thick and 60% porosity mesoporous layer, show a quality factor superior to 55% to the one obtained on massive silicon. Industrialization perspectives are on the line via a CIFRE PhD convention. In a second time, several electrochemical etching process are evaluated. Among them, high aspect ratio macropore array etching, although poorly localizable, allows many perspectives: copper via and high density capacitor.

This study produced and analyzed shaped tungsten wire tips formed through electrochemical etching. Specifically, the cone length and the radius of curvature of the tip were analyzed. Having the tips move dynamically through an electrolytic solution, such as potassium hydroxide, and tuning the initial starting depth of the tungsten wire along with the dynamic speed of the tungsten wire as it passed throughout the solution allowed various types of tip profiles to be produced. The tip's radius of curvature was able to be reproduced with an accuracy between 88 - 92 %. The method provided would be applicable for the production of various styles of liquid-metal ion source (LMIS) probes and scanning probe microscope (SPM) tips.

Semiconductor nanotechnology is today a very well studied subject, and demonstrations of possible applications and concepts are abundant. However, well-controlled mass-fabrication on the nanoscale is still a great challenge, and the lack of nanofabrication methods that provide the combination of required fabrication precision and high throughput, limits the large-scale use of nanodevices. This work aims in resolving some of the issues related to nanostructure fabrication, and deals with development of nanofabrication processes, the use of size-reduction for reaching true nanoscale dimensions (20 nm or below), and finally the optical and electrical characterization to understand the physics of the more successful structures and devices in this work. Due to its widespread use in microelectronics, silicon was the material of choice throughout this work. Initially, a fabrication process based on electron beam lithography (EBL) was designed, allowing controlled fabrication of devices of dimensions down to 30 nm, although, generally, initial device dimensions were above 70 nm, allowing the flexible but low-throughput EBL, to be replaced by state-of-the-art optical lithography in the case of industrialization of the process. A few main processes were developed throughout the course of this work, which were capable of defining silicon nanopillar and nano-wall arrays from bulk silicon, and silicon nanowire devices from silicon-on-insulator (SOI) material. Secondly, size-reduction, as a means of providing access to few-nanometer dimensions not available by current lithography techniques was investigated. An additional goal of the size-reduction studies was to find self-limiting mechanisms in the process, that would limit the impact of variations in the size and other imperfections of the initial structures. Thermal oxidation was investigated mainly for self-limited size-reduction of silicon nanopillars, resulting in well-defined quantum dot arrays of few-nm dimensions. Electrochemical etching was employed to size-reduce both silicon nanopillars and silicon nanowires down into the 10-nm regime. This being a novel application, a more thorough study of electrochemical etching of low-dimensional and thin-layer structures was performed as well as development of a micro-electrochemical cell, enabling electrochemical etching of fabricated nanowire devices with improved control. Finally, the combination of nanofabrication and size-reduction resulted in two successful device structures: Sparse and spatially well-controlled single silicon quantum dot arrays, and electrically connected size-reduced silicon nanowires. The quantum dot arrays were investigated through photoluminescence spectroscopy demonstrating for the first time atomic-like photoemission from single silicon quantum dots. The silicon nanowire devices were electrically characterized. The current transport through the device was determined to be through inversion layer electrons with surface states of the nanowire surfaces greatly affecting the conductance of the nanowire. A model was also proposed, capable of relating physical and electrical properties of the nanowires, as well as demonstrating the considerable influence of charged surface states on the nanowire conductance. / QC 20101101

Le Silicium est le deuxième élément le plus abondant dans la croûte terrestre après l’oxygène. Il est produit par voie métallurgique dans un four à arc électrique, le quartz est réduit en présence de réducteurs (charbon de bois, houille et coke de pétrole). Le silicium métallurgique est principalement utilisé dans la métallurgie comme élément d’alliage, dans la chimie et l’industrie solaire. Le prix du Silicium est fonction de sa pureté. Les travaux de cette thèse se divisent en deux parties l’utilisation du Silicium Métallurgique (99% Si) pour le stockage de l’hydrogène, et la photoluminescence du ferrosilicium (disiliciure de fer) de qualité métallurgique. Des substrats de silicium métallurgique ont été soumis à une anodisation électrochimique dans une solution à base d’acide fluorhydrique. Le silicium poreux nanostructuré obtenu est légèrement différent du silicium poreux issu de substrat de silicium de qualité électronique de même résistivité. L’influence des principaux paramètres sur la génération de l’hydrogène : la porosité, la concentration, le volume et la température ont fait l’objet d’une étude détaillée. Le silicium poreux produit à partir de silicium métallurgique est un matériau de stockage d’hydrogène. Des substrats de disiliciure de fer de qualité métallurgique ont été soumis à une anodisation électrochimique. Le composé obtenu est du disiliciure de fer nanostructuré avec du silicium résiduel, ce produit est recouvert de fluorosilicate de fer hexahydraté qui a la particularité d’être luminescent. Il s’agit à ce jour de la première anodisation du disiliciure de fer, un mécanisme de gravure a été proposé et l’influence des principaux paramètres d’anodisation sur les propriétés de photoluminescence a été évaluée. / Silicon is the second most abundant element in the Earth crust after oxygen. Its use in metallurgy, building and electronic industry requires a huge fabrication level. Depending on the contamination level allowed, the price of this material varies in the orders of magnitude. This thesis focuses on the use of dirtiest metallurgical grade silicon and iron disilicide substrates for hydrogen storage and photoluminescence applications. The initial substrates were subjected to electrochemical etching in hydrofluoric acid-containing solutions. Anodization of metallurgical grade silicon substrate produces nanostructured porous silicon with somewhat shifted parameters (comparing with electronic grade porous silicon with the same resistivity), as it was studied in this thesis in details. It was shown, that metallurgical grade porous silicon can be applied as hydrogen storage material. Hydrogen generation is studied here based on the influences of some technically critical parameters: porosity, alkali concentration, volume and temperature. Electrochemical treatment of metallurgical grade iron disilicide substrates produces luminescent iron fluorosilicate hexahydrate, covering the residual nanostructured iron disilicide/silicon. Here, the influence of anodization parameters on photoluminescent properties is studied. Also, etching mechanism is proposed as for the new material never anodized.

Ces travaux de thèse portent sur la fabrication de via traversants conducteurs, brique technologique indispensable pour l’intégration des composants microélectroniques en 3 dimensions. Pour ce faire, une voie « tout-électrochimique » a été explorée en raison de son faible coût de fabrication par rapport aux techniques par voie chimique sèche. Ainsi, la gravure de macropores ordonnés traversants a été réalisée par anodisation du silicium en présence d’acide fluorhydrique puis leur remplissage de cuivre par dépôt électrochimique. L’objectif est de faire du silicium macroporeux une alternative crédible à la gravure sèche (DRIE) pour la structuration du silicium.Les conditions de gravure de matrices de macropores ordonnés traversants ont été étudiées à la fois dans des substrats silicium de type n et p faiblement dopés. La composition de l’électrolyte ainsi que le motif des matrices ont été optimisés afin de garantir la gravure de via traversants de forte densité et à facteur de forme élevé. Une fois gravés, les via traversant ont été remplis de cuivre. En optimisant ces paramètres une résistance minimale égale à 32 mΩ/via (soit 1,06 fois la résistivité théorique du cuivre à 20°C) a été mesurée. / These thesis works deal with the achievement of Through Silicon Via (TSV) essential technological issue for microelectronic device 3D integration. For this purpose, we opted for a “full-electrochemical” way of TSV production because of lower fabrication costs as compared to dry etching and deposition techniques. Indeed, ordered through silicon macropores were carried out by silicon anodization in hydrofluoric acid-containing solution and then filled by copper electrochemical deposition. The main objective is to determine if the macroporous silicon arrays can be a viable alternative as Deep Reactive Ion Etching (DRIE).The etching parameters of through silicon macropore arrays were studied both in low-doped n- and p-type silicon. The electrolyte composition as well as the density of the initiation sites was optimized to enable the growth of high aspect ratio, high density through silicon ordered macropores. After silicon anodization, through via were filled with copper. By optimizing the copper deposition parameters (bath composition and applied potential), the resistance per via was measured equal to 32 mΩ (i.e. 1.06 times higher than the theoretical copper bulk resistivity).

Les transducteurs ultrasonores capacitifs micro-usinés (CMUT) représentent aujourd’hui une réelle alternative aux technologies piézoélectriques dans le domaine de l’imagerie échographique médicale. Au cours des années, les procédés de fabrication des transducteurs se sont enrichis en vue d’améliorer leurs performances. A contrario le choix du substrat, généralement en silicium, a été peu étudié. Il est cependant reconnu que le support contribue à la signature acoustique du dispositif ultrasonore. L’objectif de ces travaux de thèse a été d’intégrer une couche de silicium poreux afin d’absorber une partie des ondes élastiques qui se propagent dans le substrat et interfèrent avec le signal acoustique émis. Nous montrons alors qu’il été possible de réaliser une couche de silicium poreux en face arrière de composants, sur plaquettes 6 pouces, sans dégrader leurs performances. Finalement, par l’intermédiaire de caractérisations acoustiques et des signatures impulsionnelles des transducteurs, nous révélons le potentiel prometteur de ce matériaux pour la réalisation de milieu arrière atténuant dédié à la transduction ultrasonore. / Capacitive micromachined ultrasonic transducers (CMUT) have emerged as a potential alternative to traditional piezoelectric transducers for ultrasound imaging. Along the years, CMUT processes have been evolved to enhance the device performances. In the meantime, no particular attention was paid on the silicon substrate, even if it is well-known that it could contribute to the transducer efficiency. The aim of this PhD thesis was to use porous silicon as a backing material for ultrasonic transducers to absorb a piece of the acoustic wave propagating in the substrate and which induce crosstalks in the acoustic signal. We show that porous silicon layer can be obtained on the rear side of already processed wafers without any damage on the performances of capacitive micromachined ultrasonic transducers. Finally, by means of acoustic characterizations and the transducer electroacoustic responses, we reveal the potential interest of porous silicon as backing material for ultrasonic transducers.

This thesis presents methods for fabricating MicroElectroMechanical System (MEMS) actuators and high-flow gas microvalves using wafer-level integration of Shape Memory Alloys (SMAs) in the form of wires and sheets. The work output per volume of SMA actuators exceeds that of other microactuation mechanisms, such as electrostatic, magnetic and piezoelectric actuation, by more than an order of magnitude, making SMA actuators highly promising for applications requiring high forces and large displacements. The use of SMAs in MEMS has so far been limited, partially due to a lack of cost efficient and reliable wafer-level integration approaches. This thesis presents new methods for wafer-level integration of nickel-titanium SMA sheets and wires. For SMA sheets, a technique for the integration of patterned SMA sheets to silicon wafers using gold-silicon eutectic bonding is demonstrated. A method for selective release of gold-silicon eutectically bonded microstructures by localized electrochemical etching, is also presented. For SMA wires, alignment and placement of NiTi wires is demonstrated forboth a manual approach, using specially built wire frame tools, and a semiautomatic approach, using a commercially available wire bonder. Methods for fixing wires to wafers using either polymers, nickel electroplating or mechanical silicon clamps are also shown. Nickel electroplating offers the most promising permanent fixing technique, since both a strong mechanical and good electrical connection to the wire is achieved during the same process step. Resistively heated microactuators are also fabricated by integrating prestrained SMA wires onto silicon cantilevers. These microactuators exhibit displacements that are among the highest yet reported. The actuators also feature a relatively low power consumption and high reliability during longterm cycling. New designs for gas microvalves are presented and valves using both SMA sheets and SMA wires for actuation are fabricated. The SMA-sheet microvalve exhibits a pneumatic performance per footprint area, three times higher than that of previous microvalves. The SMA-wire-actuated microvalve also allows control of high gas flows and in addition, offers benefits of lowvoltage actuation and low overall power consumption. / QC 20120514