Magistro darbe yra suformuluotos Lietuvos Notariato veiklos optimizavimo problemos, remiantis moksline literatūra bei kitais šaltiniais, išanalizuoti Lietuvos Notariato 1990 – 2010 m. laikotarpyje įvykusius pokyčius įtakoję veiksniai ir atskleisti, kokie sprendimai neigiamai, kokie teigiamai paveikė institucijos veiklą. Darbe iškeltos 4 hipotezės. Remiantis atliktu tyrimu, pirmoji hipotezė, kad Lietuvos Notariatui iš Valstybinio tapus Lotyniškuoju pagerėjo atliekamų paslaugų kokybė bei išaugo pasitikėjimas šios profesijos atstovais, buvo patvirtinta tik iš dalies; antroji hipotezė, kad Lietuvos tapimas Europos Sąjungos nare lotyniškojo tipo notarui atvėrė kelius integracijai į Europos teisinį tinklą - į patikimesnį profesinį bendradarbiavimą, buvo patvirtinta; trečioji hipotezė, kad sėkmingam Notariato veiklos optimizavimui būtinas elektroninių sistemų diegimas, buvo patvirtinta; ketvirtoji hipotezė, kad notarinių paslaugų vartotojai notarų veiklos optimizavimą vertina pagal gaunamų paslaugų kokybę bei jų kainodarą, buvo patvirtinta. / This master’s final paper formulates the problems of optimization of Lithuania’s Notary activity. Based on scientific literature and other sources, factors, which influenced the changes of Lithuania Notary in 1990 – 2010, were analyzed, and reveal, which decisions negatively or positively have affected the performance of the institution. There are four hypotheses raised in the master’s final paper. According to a study carried out, the first hypothesis says that when Lithuania’s Notary has changed to the Latin type, the quality of services has improved and the trust of the employees has increased. This hypothesis was only confirmed partially. The second hypothesis which says that after Lithuania became a member of the European Union, the notary of Latin was able to integrate into the European legal network, which meant stronger professional cooperation, was confirmed. The third hypothesis, which says that electronic systems are necessary for successful optimization of Notary activity, was confirmed. The fourth hypothesis, which says that customers of Notary service assess the optimization according to the quality of service and their pricing, was confirmed.

Power electronic systems have been widely used in the electrical power processing for applications with power levels ranging from less than one watt in battery-operated portable devices to more than megawatts in the converters, inverters and rectifiers of the utility power systems. These systems typically involve the passive elements such as inductors, capacitors, and resistors, the switching electronic components such as IGBTs, MOSFETS, and diodes, and other electronic circuits. Multifrequency averaging is one of the widely used modeling and simulation techniques today for the analysis and design of power electronic systems. This technique is capable of providing the average behavior as well as the ripple behavior of power electronic systems. This work begins with the extension of multifrequency averaging to represent uniformly sampled PWM converters. A new multifrequency averaging method of solving an observed issue with model stability is proposed and validated. Multifrequency averaging can also be applied to study the instability phenomenon in power electronic systems. In particular, a reduced-order multifrequency averaging method, along with a genetic algorithm based procedure, is proposed in this work to estimate the regions of attraction of power electronic converters. The performance of this method is shown by comparing the accuracy and efficiency with the existing methods. Finally, a new continuous-time multifrequency averaging method of representing discrete-time systems is proposed. The proposed method is applied to model digitally controlled PWM converters. Simulation and hardware results show that the proposed method is capable of predicting the average behavior as well as the ripple behavior of the closed-loop systems. Future research in the area of multifrequency averaging is proposed.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Thesis (M.S.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Nous avons développé un microscope à émission d'électrons balistiques (BEEM) sous ultra-vide, dédié à l'étude des propriétés électroniques d'interfaces d'hétérostructures à base de semiconducteurs III-V pertinentes pour des applications potentielles en électronique de spin. Dans un premier temps, nous avons étudié les contacts Schottky épitaxiés Au(110)/GaAs(001) et Fe(001)/GaAs(001). Nous montrons d'un point de vue théorique que le transport cohérent d'électrons chauds à travers le métal et la conservation de la composante transverse du vecteur d'onde électronique à l'interface métal/GaAs sont à l'origine des signatures spectroscopiques BEEM contrastées observées expérimentalement sur ces deux systèmes. Ensuite, l'étude du contact tunnel MgO/GaAs(001) a révélé la présence de canaux de conduction situés dans la bande interdite de MgO. Ces canaux sont associés à la présence de lacunes d'oxygène localisées dans l'oxyde, qui diminuent fortement la hauteur de barrière tunnel. Finalement, le phénomène de magnétorésistance d'électrons chauds dans la vanne de spin Fe/Au/Fe/GaAs(001) permet d'observer par BEEM des domaines et des parois de domaines magnétiques avec une résolution latérale nanométrique.

Orientador: Carlos Alberto dos Reis Filho / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-05T12:05:57Z (GMT). No. of bitstreams: 1 Cajueiro_JoaoPauloCerquinho_D.pdf: 1564955 bytes, checksum: 6ff645ea51f6ee2dcb9e7ab8db6363aa (MD5) Previous issue date: 2005 / Resumo: Uma nova técnica de compensação de temperatura para implementar tensões de referência em circuitos CMOS é descrita, desde o seu fundamento teórico até a comprovação experimental feita com amostras de circuitos integrados protótipos que a implementam. A ténica proposta se baseia no fato de que a tensão entre gate1, e fonte, VGS, de um transistor MOS pode tanto aumentar como diminuir com o aumento da temperatura, dependendo da corrente com que opera. Com base nisto, é possível empilhar n transistores, que estejam polarizados com uma corrente adequada de tal maneira que a queda de tensão sobre esta pilha de transistores, que tem amplitude nVGS, tenha, ao mesmo tempo, a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Em tais condições, a diferença entre estas duas tensões é constante, tornando-se uma referencia de tensão. Uma implementação alternativa à pilha de transistores para produzir a tensão nVGS consiste num único transistor de gate ?utuante no qual a tensão VGS equivalente tem amplitude ajustável em campo. Diversos circuitos que se baseiam nesta técnica foram projetados e alguns deles fabricados em tecnologia CMOS 0,35 µm.O desempenho do melhor circuito fabricado atingiu coe?ciente térmico de 100 ppm/°C na faixa térmica de -40 a 120 °C. Outras configurações foram simuladas mostrando que é possível atingir coeficientes térmicos menores que 10 ppm/°C. O estado da arte é representado por referências de tensão que têm coeficientes térmicos de 1 ppm/°C na mesma faixa térmica em que se caracterizam os circuitos desenvolvidos. Tais referências de tensão se baseiam principalmente nos circuitos chamados de bandgap. Há também, um produto recente da empresa Intersil que utiliza um transistor que opera como memória análoga fornecendo uma tensão referência memorizada com altíssima estabilidade térmica. O princípio em que este produto se baseia, entretanto, é diferente do que está sendo proposto neste trabalho apesar do uso comum de um transistor de gate ?utuante. A contribuição deste trabalho não está no desempenho que as fontes de referência que se baseiam no princípio atingiram. Sua contribuição reside na forma como pode ser implementada, utilizando somente transistores MOS e no fato de que tem amplitude ajustável em campo. 1A palavra gate está sendo usada em toda extensão do texto, em lugar da palavra ¿porta¿, para identi?car o terminal de alta resistência de um transistor MOS / Abstract: A new technique of temperature compensation to implement a voltage reference in CMOS circuits is described, from theoretical basis to experimental evidence made with samples of integrated circuits prototypes that implement it. The proposed technique is based on the fact that the voltage between gate and source, VGS, of a MOS transistor can either increase as diminish with the increase of temperature, depending on the current with that it operates. Based in this, it is possible to pile up n transistors, that are polarized with an adequate current in such way that the voltage on this stack of transistors, that has amplitude nVGS, has, at the same time, the same thermal variation than the VGS voltage produced in only one transistor. In such conditions, the difference between these two voltages is constant, becoming a voltage reference. An alternative implementation to the stack of transistors to produce the nVGS volage consists of a ?oating gate transistor in which equivalent VGS has adjustable amplitude in ?eld. Diverse circuits that are based on this technique had been projected and some of them manufactured in technology CMOS 0,35 µm. The performance of the best manufactured circuit reached 100 ppm/°C of thermal coefficient in the thermal band of -40 to 120 °C. Other con?gurations had been simulated showing that it is possible to reach thermal coe?cients lesser that 10 ppm/°C. The state of the art is represented by voltage references that have thermal coefficients of 1 ppm/°C in the same thermal band where the developed circuits had been characterized. Such voltage references are mainly based on the circuits called bandgap. There is, also, a recent product of the Intersil company who uses a transistor that operates as analogical memory supplying a voltage reference memorized with highest thermal stability. The base principle of this product is, however, different of that being considered in this work despite the use of a ?oating gate transistor. The contribution of this work is not in the performance that the reference sources that are based on the principle had reached. Its contribution inhabits in the form as it can be implemented, only using MOS transistors and in the fact that it has adjustable amplitude in ?eld / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

During development of control systems for power electronic systems, it is desirable to test the controller in real-time, by interfacing it with an emulator device. In this context, this work comprises the development of an emulator that can model accurately the dynamics of high speed power electronic systems and provides interfaces that are compatible with the real hardware. The realtime state calculations, based on discrete models, were performed on custom logic, implemented on an FPGA. The realized system allows to emulate Linear Parameter Varying (LPV) systems, achieving sampling rates up to 12MHz using a low cost Xilinx FPGA. As a result, power electronic systems with very high switching frequencies can be modeled. In addition, the FPGA incorporates a soft-core processor that allows a designer to easily re-configure the system model through software. The emulator system has been validated for a multiphase DC-DC converter, by comparing its results with the real hardware setup.

La croissance formidable des dispositifs sans fils et autonomes (réseaux de capteurs, objets connectés…) voit actuellement son développement limité par les batteries qui présente une durée de vie limitée et ainsi soulève des problèmes de maintenance. Afin de palier à cette limitation, l’utilisation de l’énergie directement disponible dans l’environnement immédiat du dispositif, conduisant au concept de « récupération d’énergie », est une voie fortement explorée depuis une dizaine d’années. Ainsi, l’objectif de cette thèse a été de développer de nouvelles techniques et/ou d’utiliser de nouveaux principes de conversion afin de proposer des alternatives aux techniques de récupération d’énergie classiques. Dans un premier temps, l’optimisation de récupérateurs électrostatiques a été étudiée. Les performances de ces systèmes étant fortement liées à la variation de capacité, une structure fractale, permettant un accroissement important des surfaces en regard entre deux électrodes (et donc de la capacité) lorsque ces dernières sont proches, a été proposée et modélisée. Il est ainsi montrer un accroissement significatif des possibilités de récupération d’énergie ; ces dernières étant étroitement liées à l’amplitude de vibration du système. Le second axe de recherche de cette thèse s’est attelé à développer un modèle haut niveau simple mais précis pour les structure utilisant des polymères électrostrictifs fonctionnant en flexion. Une analyse énergétique a permis de mettre en place un modèle électromécanique masse-ressort-amortisseur couplé avec une source de courant contrôlée par les excitations mécaniques et électriques du système, permettant ainsi une conception plus aisée du microgénérateur. Enfin, la dernière partie de cette thèse s’est intéressée à la conversion d’énergie thermique utilisant la variation de perméabilité des matériaux ferromagnétiques, ouvrant de nouvelles possibilités de conversion de l’énergie. En particulier, une technique simple et autonome consiste à créer un champ magnétique de polarisation à l’aide d’un aimant, permettant une variation du flux magnétique lors d’un changement de température, qui peut être converti sous forme électrique à l’aide d’un bobinage. / This thesis has been devoted to electrostatic mechanical energy harvesting based on capacitors inspired by fractal geometry, to mechanical energy harvesting based on beams with electrostrictive polymers, and to thermal energy harvesting based on ferromagnetic materials. For electrostatic energy harvesting without electrets, interdigitated capacitors are usually applied as in-plane overlap varying and in-plane gap closing electrostatic generators. In consideration of the limit of aspect ratio for fingers in the capacitor, we would like to improve the capacitor configuration by taking advantage of self-similarity patterns. The concept is to gradually add fingers of smaller widths between original ones to form a mountain-shape capacitor. According to the different width ranges of capacitors, they are classified as of different orders whose performances vary with the vibration amplitude. Harvested energy over one cycle for capacitors of order 1, 2 and 3 has been demonstrated by theoretical and FEM results. In application, the order of capacitor needs to be properly chosen to maximize the harvested energy. Electrostrictive polymer (polyurethane) has been utilized along with a beam to perform mechanical energy harvesting. Two models have been analyzed: clamped-free beam with a polymer film attached at the clamped end, clamped-free bimorph beam. The simple model for electrostrictive devices under flexural solicitation is set up on the base of analysis of energy conversion and it shows that the electrostrictive system can be reduced to a simple spring-mass-damper system with a quadratic dependence with the applied voltage on the mechanical side and to a current source controlled by the applied voltage with a capacitive internal impedance on the electrical side. Experiments based on the clamped-free beam with a polymer film attached to the clamped end have been carried out to evaluate the mechanical to electrical conversion. The thermal energy generator is based on a ferromagnetic material, a magnet and a coil. As the magnetic permeability of ferromagnetic materials encounters drastic variation around the Curie temperature, the concept of the generator is to take advantage of the permeability variation caused by temperature decrease to generate sharp variation in magnetic flux which induces a current in the coil. According to theoretical results, the generated current is closely related to the temperature variation and the variation velocity. Experiments have been carried out on Ni30Fe of which the Curie temperature is 55 ºC. When the temperature decreases from 20.5 ºC to -42.4 ºC, the maximum power is about 4×10^(-7)W with the load to be 2 Ω.

[pt] Nesta tese investigamos os efeitos das interações elétron- elétron nas propriedades de transporte nanosistemas. Em particular, estudamos sistemas constituídos por dois pontos quânticos conectados a dois contatos, em diferentes topologias. O principal interesse é estudar os efeitos do regime Kondo e da fase eletrônica na condutância. Na configuração onde os dois pontos são inseridos em cada braço de um anel atravessado por um fluxo magnético, denotada por PPL, calculamos as fases das correntes que circulam através de cada braço do anel. Estas fases são determinadas pelo efeito Aharonov-Bohm combinado com a inflência da interação de muitos corpos das cargas nos pontos. Este sistema apresenta ressonância Kondo para um número par de elétrons em concordância com os resultados experimentais1. Outro aspecto interessante da configuração PPL é que, mesmo na ausência de fluxo magnético, pode existir circulação de corrente no anel, dependendo dos parâmetros escolhidos. Consideramos outras duas topologias que envolvem dois pontos quânticos acoplados através de interação de tunelamento. Em uma delas, denotada PAL, os dois pontos estão alinhados com os contatos, e na outra, a configuração PPD, um ponto está inserido nos contatos entanto que o outro interage só com o primeiro. No limite de acoplamento fraco, estas duas configurações apresentam características bem distintas, no só na dependência da condutância com o potencial de porta mas também na correlação de spin dos pontos quânticos. Ambas configurações apresentam ressonância Kondo para um número par de elétrons de diferente natureza. Quando cada ponto está carregado com um elétron, no caso da configuração PAL, os spins dos pontos quânticos estão descorrelacionados enquanto que, na configuração PPD, os spins estão correlacionados ferromagneticamente. No limite do acoplamento forte as propriedades de transporte das dois configurações são similares. Os sistemas discutidos acima são representados por o Hamiltoniano de Anderson de duas impurezas acopladas, o qual é resolvido diagonalizando exatamente um aglomerado que é embebido no resto do sistema. Desta forma obtemos as propriedades de transporte a T = 0. Para estudar a dependência com a temperatura utilizamos o método da equação de movimento (EOM) no limite da repulsão Coulombiana infinita. Aplicamos este método ao caso da topologia PPD, obteniendo resultados para baixas temperaturas consistente com os obtidos com o método do aglomerado. / [en] In this thesis we investigate the effects of the eletron- eletron interaction on the transport properties of nanosystems. In particular, we study systems constituted by two quantum dots conected to leads, in different topologies. Our main interest is to study the effects of the Kondo regime and the electronic phase on the conductance. In the configuration where the two dots are inserted in each arm of a ring threaded by a magnetic flux, denoted by PPL, we calculate the phases of the currents going along each arm of the ring. These phases are determined by the Aharonov-Bohm effect combined with the dots many body charging effects. This system presents the Kondo phenomenon for an even number (two) of electrons in the dots, in agreement with experimental results1. An interesting aspect of PPL configuration is that, even in the absence of magnetic flux there can be a circulating current around the ring, depending on the system parameters. In the two other topologies we consider the two quantum dots coupled through tunneling interaction. In one of them, denoted by PAL, the two dots are aligned with the leads, and in the other, the PPD configuration, one dot is inserted into the leads while the other interacts only with the first. In the weak coupling limit these two configurations present quite different features, not only on the dependence of the conductance on the gate potencials applied to the dots, but also on the dots spin correlation. Both configurations present Kondo resonance for an even number electrons. In the PAL configuration the spins of the charged dots are uncorrelated, while in the PPD configuration they are ferromagnetically correlated. In the strong tunneling coupling limit the transport properties of two interacting dot configurations are very similar. The systems discussed above are represented by an Anderson two- impurity first-neighbor tight-binding Hamiltonian, that is solved by exactly diagonalizing a cluster that is embebed into the rest of the system. In this way we obtain only the properties of the system at T = 0. In order to study temperature dependence phenomena we use the equation of motion method (EOM) in the limit of infinite Coulomb repulsion. We apply it to the dots in the PPD topology. The results for low temperatures are consistent with hose obtained with the cluster method.

Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.