The growing interest in high speed and RF technologies assert for the importance of reliability characterization beyond the conventional DC methodology. In this work, the influence of bias temperature instability (BTI) stress on RF small signal parameters is shown. The correlation between degradation of DC and RF parameters is established which enables the empirical modelling of stress induced changes. Furthermore, S-Parameters characterization is demonstrated as the tool to qualitatively distinguish between HCI and BTI degradation mechanisms with the help of extracted small signal gate capacitances.

No description available.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

Silicon-on-Insulator (SOI) CMOS technology constitutes a good candidate for mixed signal RF CMOS applications. Due to its low junction capacitance and reduced leakage current, SOI provides reduced static and dynamic power consumption of the digital logic combined with increased cut-off frequencies. Moreover, in terms of passive device integration the major benefit of SOI when compared to the conventional bulk is the possibility to use a high resistivity substrate which allows a drastic reduction of substrate losses allowing a high quality factor of the passive devices. Another issue is the harsh environment applications. Electronics capable of operating at high temperatures are required in several industrial applications, including the automobile industry, the aerospace industry, the electrical and nuclear power industries, and the well-logging industry. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 300°C has been demonstrated. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latch up and reduced leakage current. In this context, various topologies of integrated transmission lines and spiral inductors implemented on standard and high substrate resistivities have been analyzed over a large temperature range. The temperature behavior of the SOI transistors is presented. The main figures-of-merit of the SOI MOSFETs are analyzed and the extraction of the extrinsic and intrinsic parameters of the small signal equivalent circuit is performed. Also, an example of RF circuit applications of the SOI technology, based on a fully integrated Low-Noise Amplifier for low-power and narrow-band applications, is investigated and characterized at high temperature. The main figures-of-merit of the designed circuit are extracted and discussed. The good results show that the SOI technology is now emerging as a good candidate for the realization of analog integrated circuits for low-power and high-temperature applications.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

La photonique du silicium a connu un développent massif pendant les dix derniers années. Presque toutes les briques technologiques de base ont été réalisées et ont démontrées des performances remarquables. Cependant, le manque d’une source laser intégrée en silicium a conduit les chercheurs à développer de composants basés sur l’intégration entre le silicium et les matériaux III-V.Dans cette thèse je décris la conception, la fabrication et la caractérisation des lasers hybrides III-V sur silicium basés sur cette intégration. Je propose un coupleur adiabatique qui permet de transférer intégralement le mode optique du guide silicium au guide III-V. Le guide actif III-V au centre du composant fourni le gain optique et les coupleurs, des deux cotés, assurent le transfert de la lumière dans les guides silicium.Les lasers mono longueur d’onde sont des éléments fondamentaux des communications optiques. Je décris les différentes solutions permettant d’obtenir un laser mono-longueur d’onde hybride III-V sur silicium. Des lasers mono longueur d’onde ont été fabriqués et caractérisés. Ils démontrent un seuil de 21 mA, une puissance de sortie qui dépasse 10 mW et une accordabilité de 45 nm. Ces composants représentent la première démonstration d’un laser accordable hybride III-V sur silicium. / Silicon photonics knew an impressive development in the last ten years. Almost all the fundamental building blocks have been demonstrated and reveal competitive performances. However, the lack of an efficient silicon integrated laser source has led the researchers to develop heterogeneous integration of III-V materials on silicon.In this thesis I describe the design, the fabrication and the performances of these hybrid III-V on silicon lasers. I propose the use of an adiabatic coupler that totally transfers the optical mode between the III-V and the silicon waveguides. The active waveguide on III-V materials at the center of the device provides the optical gain, while, on both side, adiabatic couplers allow a loss-less transfer of the optical mode to the silicon waveguide. Single wavelength emitting lasers are fundamental elements for high bandwidth optical links. I review all the effective solutions enabling single waveguide hybrid III-V on SOI lasers. DBR, microring based, DFB and AWG laser solutions were analysed. Single wavelength operating lasers have been fabricated and characterized. A laser threshold of only 21 mA, an output power of more than 10 mW and tunability over 45 nm with a SMSR of 45 dB have been measured. These devices represent the first demonstration of a monolithically integrated hybrid III-V/Si tunable laser made by wafer bonding technique.

Cette thèse apporte une contribution théorique et expérimentale à l'exploration des propriétés de dispersion et de polarisation de structures à cristaux photoniques à gradient (GPhCs). Nous explorons pour commencer la relation qui existe entre les déformations des surfaces équi-fréquences (EFS) de différents cristaux photoniques et les paramètres de maille des configurations envisagées. Compte tenu de la complexité des structures possibles obtenues à partir d'un chirp spatial bidimensionnel d'au moins un paramètre de maille, nous avons limité notre étude à un type particulier de structure basé sur un réseau carré de silicium sur isolant (SOI) planaire constitué de trous d'air de facteur de remplissage variable. Une expression analytique des EFS connexes en fonction du rayon des motifs a d’abord été extraite, et une structure GPhC de "référence" a ensuite été proposé pour l'exploration des propriétés de dispersion et de polarisation des GPhCs utilisant à la fois une approche consistant à propager un ou plusieurs rayons optiques dont les trajectoires sont données par les équations de l’optique Hamiltonienne et une approche tout numérique basée sur des simulations FDTD. Nous décrivons ensuite les processus de fabrication de salle blanche des structures à cristaux photoniques graduels, obtenues à partir de substrats semiconducteurs par lithographie par faisceau d'électrons et gravure ionique réactive. Les échantillons fabriqués sont étudiés expérimentalement par des techniques de mesure en champ lointain et en champ proche (SNOM) en s'appuyant sur une collaboration avec un autre groupe du CNRS. Les résultats expérimentaux montrent une relation dispersive quasi-linéaire de 0.25μm/nm dans la gamme de longueur d’onde allant de 1470nm à 1600nm. Les premiers dispositifs fabriqués présentent aussi la possibilité de séparer des couples de deux longueurs d'onde (démultiplexage) avec des pertes d'insertion faibles (inférieures à 2 dB) et un niveau de diaphonie faible (de l'ordre de -20 dB). Ils présentent également un effet très net de séparation des polarisations de la lumière avec une diaphonie inter-polarisations TE/TM de -27dB dans une bande spectrale de l’ordre de 70 nm. Au-delà de ces mesures optiques obtenus dans une configuration particulière de cristal photonique graduel, les travaux présentés dans cette thèse ont permis l'observation directe de la transition entre les régimes d’homogénéisation et de diffraction de propagation de la lumière dans un matériau optique artificiel tout diélectrique. Globalement, la méthodologie présentée et adoptée pour l'étude de la propagation de la lumière dans les structures étudiées a ouvert des perspectives pour la réalisation de fonctions optiques plus complexes. / This PhD thesis brings a theoretical and experimental contribution to the exploration of dispersive and polarization properties of graded photonic crystal (GPhC) structures. We first present a quantitative relationship between the deformations of the equi-frequency surfaces (EFSs) of different photonic crystals and the lattice parameters of the considered configurations. Considering the complexity of the possible GPhC structures made of a two-dimensional spatial chirp of at least one lattice parameter, we limit in this thesis our study to one particular type of GPhC structure based on a square lattice silicon on insulator (SOI) planar photonic crystal with a variable air hole filling factor profile. An analytical expression of the related EFSs as a function of the varied lattice parameter is extracted, and a GPhC “reference” structure is then proposed for the exploration of the dispersive and polarization properties of GPhCs using both Hamiltonian optic-assisted ray tracing as well as FDTD simulations. The clean room fabrication process of this GPhC structure family, which is based on electron beam lithography and reactive ion etching technologies, is reported. Fabricated samples are experimentally studied by far-field and near-field (SNOM) measurement techniques relying on a collaboration with a CNRS group of the Bourgogne university. Experimental results show an almost linear dispersive relationship of 0.25µm/nm in the 1470nm-1600nm spectral range. The fabricated samples also present the possibility for two-wavelength demultiplexing with low insertion loss (below 2dB) and low crosstalk level (around -20dB), and a polarization beam splitting effect with a crosstalk of -27dB in a 70nm bandwidth. Beyond these optical metrics obtained in one particular GPhC configuration, the works presented in this thesis have allowed the direct observation of the transition between the homogeneous and diffraction regimes of light propagation in an artificial optical all-dielectric material, and the presented and adopted methodology for the study of light propagation in GPhC structures has raised open perspectives for the realization of more complex optical functions in forthcoming works using low loss and flexible metamaterial-like photonic crystals.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process ?? a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 300 K, 4.2 2 K, and sub-K (30 30 mK base to 1000 1000 mK) showed that they function with desirable behaviour although exhibiting some deviations from their 300 300 K characteristics. The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 100 ps rise-times at 300 K, 4.2 2 K, and sub-K with a power dissipation of 12 12 uW at 100 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 300 K, 4.2 2 K, and sub-K which suitable for qubit control.

This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.