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The Medium Voltage DC (MVDC) architecture of shipboard power system (SPS) with higher power density and enhanced power control is seen as a future prospect in warships by US Navy. Optimal operation of SPS is essential to enable efficient power and energy usage in the tightly coupled and power limited systems. It helps in obtaining adequate and reliable power supply by rescheduling generator output and energy storage devices for different operating scenarios and can also ensure power supply to critical loads during fault conditions. The self-commutated Voltage Source Converters (VSCs) with high dynamic performance and independent control over the real and reactive powers are best suited in the MVDC architecture. Therefore, an optimal operation tool is developed for the multi-terminal VSC based MVDC SPS which minimizes the system operating costs by optimally coordinating generators and energy storage, and will also implement preventive and corrective actions for managing credible contingencies.

In recent years, both a significant increase in electrical demand and a large influx of intermittent renewable energy sources have put a considerable stress on the nation’s electrical grid. Conventional power flow control techniques such as capacitor banks and tap-changing transformers are incapable of adequately handling the rapid fluctuations in power supply and demand that today’s grid experiences. Flexible AC Transmission System (FACTS) controllers are a practical way to compensate for such rapid power fluctuations. One type of shunt FACTS controller is the Static Synchronous Compensator (STATCOM), which uses fully controllable switches to source or sink reactive power to a point on the grid, thus reducing voltage fluctuations due to load changes. The purpose of this thesis is to model and simulate the operation of two Distribution STATCOMs (D-STATCOMs) operating on the same point on the grid. These D-STATCOMs also utilize parallel full-wave rectifiers that directly connect the ac grid to the dc capacitor of the D-STATCOMs. Parameters such as power loss, reaction time, stability, and THD are measured for several test scenarios. Results from this thesis show that two D-STATCOMs operating on the same point can be stable and effective under a wide range of conditions. This thesis also concludes that the inclusion of parallel rectifiers with the D-STATCOMs results in no performance improvement of the D-STATCOMs.

The past few decades have seen a rapid sales increase and technological development of electric vehicles (EVs). As the key part of the electrical powertrain systems, the traction machine drive systems in modern EVs are composed of voltage source inverters (VSI) and electric machines. In this thesis, multiphase VSIs are studied and designed to achieve volume reductions when compared with existing 3-phase benchmark VSIs. Different existing switching strategies for arbitrary phase number multiphase VSIs are investigated resulting in an understanding of best practice and a newly proposed switching strategy. Thus, the first contribution of this thesis is switching strategies that support subsequent investigations and experimental validation. DC-link capacitor and heat sink are two bulkiest components in VSIs and hence it is more efficient to decrease their volumes to achieve the compactness improvement. The investigation methodology and procedure for arbitrary phase number VSI DC-link capacitor requirements, i.e. capacitance and RMS current ratings, are firstly developed. Increased phase number decreases the DC-link capacitor requirements and hence the VSI volume significantly. Throughout this analysis, the connected multiphase machine is considered appropriately, though no electric machine design is described in the thesis. While other authors have studied DC-link current ripple, this thesis qualifies and quantifies the system benefits. This is the second contribution. Multiphase VSIs thermal models are built and their respective thermal performances studied and evaluated against a reference 3-phase benchmark VSI. The power loss deviation among different semiconductor dies is lower or even eliminated in the multiphase VSIs. Furthermore, the multiphase integrated design VSIs have a significant heat sink volume reduction when compared to the 3-phase benchmark VSI. This study and concluding benefits are the third contribution. Finally, comparative test validations are made on an experimental set-up designed to illustrate the benefits of a 9-phase against a reference 3-phase system. Here, the test hardware and implementation are carefully designed to representatively illustrate performance benefits. / Thesis / Doctor of Philosophy (PhD)

Advancements in the power electronics systems have been directly related to the availability of improved power semiconductor devices. The device performance greatly determines the efficiency, reliability, volume, and cost of the power electronics system. This dissertation is dedicated to develop an advanced high power semiconductor device, the emitter turn-off (ETO) thyristor, which is targeted to improve the limitations of the present high power devices. Major improvements in electrical and mechanical designs of the ETO for high power and high frequency operation are proposed which result in improved snubberless turn-off capability, low conduction loss, and low gate drive power consumption of the new generation ETO. A revolutionary self-power generation method of the ETO is proposed. Different from the conventional high power devices which require the external power input for their gate drivers, ETO achieves complete optically controlled turn-on and turn-off and all the internal power required is self-generated. This advancement will have a major impact to high power converter designs. A novel integrated method to eliminate the dead-time requirement is proposed for ETO. This method not only improves the output waveform quality but also increases the reliability and reduces the cost of the high power PWM voltage source converters. With this unique function, the upper and the lower ETO's within a converter phase leg can receive the ideal complementary (without dead-time) PWM signals and solve shoot-through problems. Method to measure the ETO current and transfer the current information to a PWM signal is proposed. Based on the ETO's built-in current sensor, the over-current protection function of the ETO is designed as well. The experimental results show that the built-in current sensor has a very high precision, and the over-current protection function can effectively protect the ETO during the short circuit faults. In order to improve ETO's turn-off capability, a comprehensive investigation of the turn-off failure mechanism of the ETO was performed. A series of simulations and experiments are carried out to study the ETO turn-off operation. The detail turn-off failure mechanisms are presented. The conditions to cause the ETO failure are addressed. The approaches to improve the ETO's turn-off capability are discussed. / Ph. D.

In recent decades there has been a rapidly growing demand for high quality, uninterrupted power. In light of this fact, this study has addressed some of the causes of poor power quality and control strategies to ensure a high performance level in inverter-fed power systems. In particular, specific loading conditions present interesting challenges to inverter-fed, high power systems. No-load, unbalanced loading, and non-linear loading each have unique characteristics that negatively influence the performance of the Voltage Source Inverter (VSI). Ideal, infinitely stiff power systems are uninfluenced by loading conditions; however, realistic systems, with finite output impedances, encounter stability issues, unbalanced phase voltage, and harmonic distortion. Each of the loading conditions is presented in detail with a proposed control strategy in order to ensure superior inverter performance. Simulation results are presented for a 90 kVA, 400 Hz VSI under challenging loading conditions to demonstrate the merits of the proposed control strategies. Unloaded or lightly loaded conditions can cause instabilities in inverter-fed power systems, because of the lightly damped characteristic of the output filter. An inner current loop is demonstrated to damp the filter poles at light load and therefore enable an increase in the control bandwidth by an order of magnitude. Unbalanced loading causes unequal phase currents, and consequently negative sequence and zero sequence (in four-wire systems) distortion. A proposed control strategy based on synchronous and stationary frame controllers is shown to reduce the phase voltage unbalance from 4.2% to 0.23% for a 100%-100%-85% load imbalance over fundamental positive sequence control alone. Non-linear loads draw harmonic currents, and likewise cause harmonic distortion in power systems. A proposed harmonic control scheme is demonstrated to achieve near steady state errors for the low order harmonics due to non-linear loads. In particular, the THD is reduced from 22.3% to 5.2% for full three-phase diode rectifier loading, and from 11.3% to 1.5% for full balanced single-phase diode rectifier loading, over fundamental control alone. / Master of Science

Superconducting Magnetic Energy Storage (SMES) has branched out from its application origins of load leveling, in the early 1970s, to include power quality for utility, industrial, commercial and military applications. It has also shown promise as a power supply for pulsed loads such as electric guns and electromagnetic aircraft launchers (EMAL) as well as for vital loads when power distribution systems are temporarily down. These new applications demand more efficient and compact high performance power electronics. A 250 kW Power Conditioning System (PCS), consisting of a voltage source converter (VSC) and bi-directional two-quadrant DC/DC converter (chopper), was developed at the Center for Power Electronics Systems (CPES) under an ONR funded program. The project was to develop advanced power electronic techniques for SMES Naval applications. This thesis focuses on system analysis and development of a demonstration test plan to illustrate the SMES systems' ability to be multitasked for implementation on naval ships. The demonstration focuses on three applications; power quality, pulsed power and vital loads. An integrated system controller, based on an Altera programmable logic device, was developed to coordinate charge/discharge transitions. The system controller integrated the chopper and VSC controller, configured applicable loads, and dictated sequencing of events during mode transitions. Initial tests with a SMES coil resulted in problems during mode transitions. These problems caused uncontrollable transients and caused protection to trigger and processors to shut down. Accurate models of both the Chopper and VSC were developed and an analysis of these mode transition transients was conducted. Solutions were proposed, simulated and implemented in hardware. Successful operation of the system was achieved and verified with both a low temperature superconductor here at CPES and a high temperature superconductor at The Naval Research Lab. / Master of Science

The voltage source inverter (VSI) is certainly the most popular topology used in dc to ac power conversion. Virtually every commercial electric motor is driven by a VSI. There is a need for smaller and more efficient drives in high performance applications that is dictating unprecedented power density requirements on airborne motor drive systems. In reply to this need, higher switching frequencies are being sought and new switching devices like Silicon Carbide (SiC) JFETs have emerged. Although faster switching rates favor a reduction in the size of passive components and alleviate the current ripple in the inverter, a penalty is paid on switching losses. Owing to their low switching energy profile, SiC JFETs stand as promising candidates in high switching frequency environments. Their normally-on nature, however, raises a level of discomfort among designers due to the added complexities in the gate drive circuitry and the increased risk of dc bus shoot-through faults in voltage source inverters. Despite of these challenges the use of SiC JFETs continues proliferating in high power density applications. In an effort to study the new challenges introduced by this trend a 2 kW IGBT-based three-phase voltage source inverter operating at 65 kHz was designed, built, and tested. In addition a novel overcurrent protection residing in the inverter dc link is proposed in response to the concern of using normally-on devices in voltage source inverters. Successful hardware validation of both the VSI and the overcurrent protection circuit is supported with experimental results. / Master of Science

Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

Multilevel inverters are very popular for medium and high-voltage induction motor (IM) drive applications. They have superior performance compared to 2-level inverters such as reduced harmonic content in output voltage and current, lower common mode voltage and dv/dt, and lesser voltage stress on power switches. To get nearly sinusoidal current waveforms, the switching frequency of the conventional inverters have to be in¬creased. This will lead to higher switching losses and electromagnetic interference. The problem in using lower switching frequency is the introduction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching. Dodecagonal voltage space-vector based multilevel inverters have been proposed as an improvement over the conventional hexagonal space vector based inverters. They achieve complete elimination of 5th and 7th order harmonics throughout the modulation range. The linear modulation range is also extended by about 6.6%, since the dodecagon is closer to circle than a hexagon. The previous works on dodecagonal voltage space vector based VSI fed drives used voltage controlled PWM (VC-PWM). Although these controllers are more popular, they have inferior dynamic performance when compared to current controlled PWM (CC¬PWM). VSIs using current controlled PWM have excellent dynamic response, inherent short-circuit protection and are simple to implement. The conventional CC-PWM tech¬niques have large switching frequency variation and large current ripple in steady-state. xix As a result, there has been significant research interest to achieve current controlled VSI fed IM drives with constant switching frequency. Two current error space vector (CESV) based hysteresis controllers for dodecagonal voltage space-vector based VSI fed induction motor drives are proposed in this work. The proposed controllers achieve nearly constant switching frequency at steady state operation, similar to VC-SVPWM based VSI fed IM drives. They also have fast dynamic response while at the same time achieving complete elimination of fifth and seventh order harmonics for the entire modulation range, due to dodecagonal voltage vector switching. The first work proposes a nearly constant switching frequency current error space vector (CESV) based hysteresis controller for an IM drive with single dodecagonal voltage space vectors. Parabolic boundaries computed offline are used in the proposed controller. An open-end winding induction motor is fed from two inverters with asymmetrical DC link voltages, to generate the dodecagonal voltage space vectors. The drive scheme is first studied at different frequencies with a space vector based PWM (SVPWM) control, to obtain the current error space vector boundaries. The CESV boundary at each frequency can be approximated with four parabolas. These parabolic boundaries are used in the proposed controller to limit the CESV trajectory. Due to symmetries in the parabolas only two set of parabola parameters, at different frequencies, need to be stored. A generalized next vector selection logic, valid for all sectors and rotation direction, is used in the proposed controller. For this an axis transformation is done in all sectors, to bring the CESV trajectory to the first sector. The sector information is obtained from the estimated fundamental stator phase voltage. The proposed controller is extensively studied using vector control at different frequencies and transient conditions. This controller maintains nearly constant switching frequency at steady state operation, similar to VC-SVPWM inverters, while at the same time achieving better dynamic performance and complete elimination of 5th and 7th order harmonics throughout the modulation range. In the second work the nearly constant switching frequency current hysteresis con¬troller is extended to multilevel dodecagonal voltage space-vector based IM drives, with online computation of CESV boundaries. The multilevel dodecagonal space-vector dia¬gram has different types of triangles, and the previously proposed methods for multilevel hexagonal VSI based current hysteresis controllers cannot be used directly. The CESV trajectory of the VC-SVPWM, obtained for present triangular region, is used as the reference trajectory of the proposed controller. The CESV reference boundaries are com¬puted online, using switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages, which are found out from the stator current error ripple and the parameters of the induction motor. Whenever the actual current error space vector crosses the reference CESV tra¬jectory, an appropriate vector that will force it along the reference trajectory is switched. Extensive study of the proposed controller using vector control is done at different fre¬quencies and transient conditions. This controller has all the advantages of multilevel switching like low dv/dt, lesser electromagnetic interference, lower switch voltage stress and lesser harmonic distortion, in addition to all the dynamic performance advantages of the previous controller. The third work proposes an elegant 5th and 7th order harmonic suppression tech¬nique for open end winding split-phase induction motors, using capacitor fed inverters. Split-phase induction motors have been proposed to reduce the torque and flux ripples of conventional three-phase IM. But these motors have high 5th and 7th order harmonics in the stator windings due to lack of back-emf for these frequencies. A space-vector harmonic analysis of the split-phase IM is conducted and possible 5th and 7th order harmonic sup¬pression techniques studied. A simple harmonic suppression scheme is proposed, which requires the use of only capacitor fed inverters. A PWM scheme that can maintain the capacitor voltage as well as suppress the 5th and 7th order harmonics is also proposed. To test the performance of the proposed scheme, an open-loop v/f control is used on an open-end winding split-phase induction motor under no-load condition. Synchronized PWM with two samples per sector was used, for frequencies above 10 Hz. The har¬monic spectra of the phase voltages and currents were computed and compared with the traditional SVPWM scheme, to highlight the harmonic suppression. The concepts were initially simulated in Matlab/Simulink. Experimental verifica¬tion was done using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control tech¬niques presented shall still remain applicable. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the first work the output pins of the DSP was directly used to drive the inverter switches through a dead-band circuit. For the other two works, DSP outputs the sector information and the PWM signals. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. An FPGA (XC3S200) was used to translate the sector information and the PWM signals to IGBT gate signal logic. A constant dead-time of 1.5 µs was also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. The phase currents and DC bus voltages were measured using hall-effect sensors. An incremental shaft position encoder was also connected to the motor to measure the angular velocity. The switches were realized using 1200 V, 75 A IGBT half bridge modules.