Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal.

The objective of the research was to investigate proton-coupled electron transfer (PCET) reactions involving antioxidants to gain insight into the detailed mechanisms of glutathione (GSH), Trolox, and α-tocopherol (α-TOH). PCET reactions are complex redox reactions that transfer electrons and protons sequentially or in concert. These reactions are ubiquitous in natural or artificial processes that produce electrochemical energy that is extractable as electricity or as chemical fuels of high energy content. Examples of processes based on PCET are photosynthesis, respiration, nitrogen fixation, carbon dioxide reduction, redox fuel cells, and artificial photosynthesis. Antioxidants were selected as a PCET model to understand the coupling between proton transfer (PT) and electron transfer (ET) in order to elucidate structure-reactivity relationships under different experimental conditions. PCET reactions were studied with a set of electrochemical techniques to propose a preliminary mechanism that could be validated with digital simulations matching the electrochemical response. In some cases, other analytical techniques were used to aid in the system characterization. This thesis presents the results and discussion of the effects of oxidant-base pairs on the mediated oxidation of GSH, the -2e-/-H+ process of Trolox in aqueous and nonaqueous solvents with various pH values, and the particle collision electrolysis of α-tocopherol in oil-in-water emulsion droplets on an ultramicroelectrode. Ultimately our goal was to determine the kinetic and thermodynamic factors that control PCET reactions so that they can be applied in designing artificial systems for the production of energy using more abundant reagents with lower cost and better yields.

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal

La réalisation par des procédés robotisés de pièces composites à destination, notamment, de l’aéronautique vise à en augmenter la productivité. Cependant le Placement de Fibres Robotisé (PFR) est encore en phase de maturation et requiert de nombreux développements, en particulier dans le cas des composites à matrice thermoplastique ou à fibre sèche. Dans cette thèse, nous proposons différents outils qui permettent in fine de déterminer à l’avance la meilleure puissance de chauffe pour la mise en œuvre de ces composites. La difficulté réside dans le fait que cette puissance dépend de nombreux paramètres, non seulement au niveau de la matière utilisée (densité, chaleur spécifique. . .), mais encore au niveau du procédé lui-même (vitesse de déplacement, nombre et orientation des plis. . .). Nous avons construit un modèle réduit multi-paramétrique en utilisant la technique appelée Proper Generalised Decomposition (PGD). Les résultats ont été confrontés à ceux obtenus par des méthodes plus conventionnelles et aussi à des données expérimentales. / Realising composite parts mainly dedicated to aeronautics sector by robotised processes tends to increase productivity. However, Automated Tape Placement (ATP) is still in ripening stage and requires various developments, particularly in case of thermoplastic composites or dry fibres. In this manuscript, we propose different tools allowing to determine in advance the best heating power to drape composite fibres. Difficulty arises from dependence on many parameters, from material (density, specific heat) or from process itself (velocity, number and orientation of plies). Therefore we construct a multi-parametric reduced order model using the so called Proper Generalised Decomposition (PGD). Results have been faced to those obtained from more conventional methods but also to experimental data.

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.

No / Crystal structure prediction simulations were carried out to explore the solid state packing alternatives of two diastereomeric salts consisting of a chlorine-substituted cyclic phosphoric acid and the two enantiomers of ephedrine. The experimentally observed crystal structures were correctly simulated with an error of a few kcal/mol. This represents a significant achievement in crystal structure prediction due to the complexity of the mathematical search problem at hand (two distinct molecules in the asymmetric unit, one of which is flexible) and due to the complex energetics of these organic salts. In principle, these simulations show the way toward a truly predictive model for racemate resolution by preferential crystallization of diastereomeric salts.

This research work has investigated the electrochemistry of glutathione (GSH)and homocysteine (HCSH) in order to develop sensors for these biological thiols.Ru(bpy)33+ and IrCl62− have been used as mediators for the electrooxidation of GSH andHCSH because direct oxidation of these thiols is slow at most conventional electrodes.The electrochemical detection of GSH and HCSH has been pursued because of their biological roles. Concerted proton electron transfer (CPET) and stepwise proton electron transfer(PT/ET) pathways have been observed in the electrooxidation of GSH and HCSH.Oxidation of GSH by Ru(bpy)33+ carried out in deuterated and undeuterated buffered (pH= pD = 5.0) and unbuffered solutions (pH = pD 5.0−9.0) indicates a CPET pathway. AtpH 7.0 buffered solution, the involvement of the buffer was obvious, with rate increasing as the buffer concentration increases − an indication of a general base catalysis. The oxidation of GSH by IrCl62− follows through CPET at pH 7.0 when the optimum concentration of the buffer is established. The plot of the rate vs. buffer concentration gave a curvature at lower buffer concentration and then a plateau at higher concentration,which implies a change in the rate determining step as the buffer concentration increases.At lower buffer concentration, proton transfer was seen to be the rate determining step asthe reduction current increases upon scan rate increase. In the oxidation of HCSH by IrCl62−, CPET was observed at pH = pD values of7.0 and 8.0, whereas PT/ET was seen at pH = pD values of 9.0 and 10. Increase in the buffer concentration at pH 7.0 revealed the contribution of the buffer, in that, the oxidation proceeds more efficiently, seeing that the catalytic peak current shifts more negatively and the peak broadness diminishes. Increase in the temperature for the electrooxidation of HCSH resulted in increase in the rate.

This thesis advances the state of the art in modeling electric machines in electro-magnetic transient simulation programs, particularly in real-time digital simulators. A new tool, developed in this thesis, expands the application of real-time digital simulators to closed-loop testing of protection relays designed to protect synchronous machines during internal faults. To evaluate the inductances of synchronous machines, a winding function approach was developed in this thesis which is capable of taking into account both the actual distribution of windings and the shape of the pole-arc. Factors such as MMF drop in the iron and effects of slots are compensated by evaluating the effective permeance function of the machine using experimentally measured values of d-, q- and 0- axis inductances. In this winding function approach, the effects of magnetic saturation are also included by considering the actual distribution of magneto-motive force in each loading condition of the machine. The inductances of an experimental machine are evaluated using this approach and validated using the finite-element method and laboratory measurements. This thesis also proposes an embedded phase-domain approach for time-domain simulation of the machine model in electromagnetic transients programs. The approach significantly improves the numerical stability of the simulations. Special numerical techniques are introduced, which speed up the execution of the algorithm as needed for real-time simulation. The machine model is validated in healthy and faulted conditions using simulations and laboratory experiments. Effects of damper grid representation on simulating turn-to-turn faults are investigated. The capability of this new real-time synchronous machine model in closed-loop testing of synchronous machines ground- faults protection relays is clearly demonstrated.

This thesis advances the state of the art in modeling electric machines in electro-magnetic transient simulation programs, particularly in real-time digital simulators. A new tool, developed in this thesis, expands the application of real-time digital simulators to closed-loop testing of protection relays designed to protect synchronous machines during internal faults. To evaluate the inductances of synchronous machines, a winding function approach was developed in this thesis which is capable of taking into account both the actual distribution of windings and the shape of the pole-arc. Factors such as MMF drop in the iron and effects of slots are compensated by evaluating the effective permeance function of the machine using experimentally measured values of d-, q- and 0- axis inductances. In this winding function approach, the effects of magnetic saturation are also included by considering the actual distribution of magneto-motive force in each loading condition of the machine. The inductances of an experimental machine are evaluated using this approach and validated using the finite-element method and laboratory measurements. This thesis also proposes an embedded phase-domain approach for time-domain simulation of the machine model in electromagnetic transients programs. The approach significantly improves the numerical stability of the simulations. Special numerical techniques are introduced, which speed up the execution of the algorithm as needed for real-time simulation. The machine model is validated in healthy and faulted conditions using simulations and laboratory experiments. Effects of damper grid representation on simulating turn-to-turn faults are investigated. The capability of this new real-time synchronous machine model in closed-loop testing of synchronous machines ground- faults protection relays is clearly demonstrated.

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs.