Helmut-Schmidt-Universiẗat, Diplomarbeit--Hamburg, 2005.

Univ., Diss.--Mannheim, 2007.

Univ., Diss.--Bonn, 1999.

Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés. / For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.

E-crimes continue to generate grave challenges to the ICT regulatory agenda. Because e-crimes involve a wrongful appropriation of information online, it is enquired whether information is property which is capable of being stolen. This then requires an investigation to be made of the law of property. The basis for this scrutiny is to establish if information is property for purposes of the law. Following a study of the Roman-Dutch law approach to property, it is argued that the emergence of an information society makes real rights in information possible. This is the position because information is one of the indispensable assets of an information society. Given the fact that information can be the object of property, its position in the law of theft is investigated. This study is followed by an examination of the conventional risks that ICTs generate. For example, a risk exists that ICTs may be used as the object of e-crimes. Furthermore, there is a risk that ICTs may become a tool in order to appropriate information unlawfully. Accordingly, the scale and impact of e-crimes is more than those of the offline crimes, for example theft or fraud. The severe challenges that ICTs pose to an information society are likely to continue if clarity is not sought regarding: whether ICTs can be regulated or not, if ICTs can be regulated, how should an ICT regulatory framework be structured? A study of the law and regulation for regulatory purposes reveals that ICTs are spheres where regulations apply or should apply. However, better regulations are appropriate in dealing with the dynamics of these technologies. Smart-regulations, meta-regulations or reflexive regulations, self-regulations and co-regulations are concepts that support better regulations. Better regulations enjoin the regulatory industries, for example the state, businesses and computer users to be involved in establishing ICT regulations. These ICT regulations should specifically be in keeping with the existing e-authentication measures. Furthermore, the codes-based theory, the Danger or Artificial Immune Systems (the AIS) theory, the Systems theory and the Good Regulator Theorem ought to inform ICT regulations. The basis for all this should be to establish a holistic approach to e-authentication. This approach must conform to the Precautionary Approach to E-Authentication or PAEA. PAEA accepts the importance of legal rules in the ICT regulatory agenda. However, it argues that flexible regulations could provide a suitable framework within which ICTs and the ICT risks are controlled. In addition, PAEA submit that a state should not be the single role-player in ICT regulations. Social norms, the market and nature or architecture of the technology to be regulated are also fundamental to the ICT regulatory agenda. / Jurisprudence / LL. D.

Les substrats Silicium-sur-Isolant (SOI) représentent la meilleure solution pour obtenir des dispositifs microélectroniques ayant de hautes performances. Des méthodes de caractérisation électrique sont nécessaires pour contrôler la qualité SOI avant la réalisation complète de transistors. La configuration classique utilisée pour les mesures du SOI est le pseudo-MOFSET. Dans cette thèse, nous nous concentrons sur l'amélioration des techniques autour du Ψ-MOFSET, pour la caractérisation des plaques SOI et III-V. Le protocole expérimental de mesures statiques ID-VG a été amélioré par l'utilisation d'un contact par le vide en face arrière, permettant ainsi d'augmenter la stabilité des mesures. De plus, il a été prouvé que ce contact est essentiel pour obtenir des valeurs correctes de capacité avec les méthodes split-CV et quasi-statique. L'extraction des valeurs de Dit avec split-CV a été explorée, et un model physique nous a permis de démontrer que ceci n'est pas possible pour des échantillons SOI typiquement utilisés, à cause de la constante de temps reliée à la formation du canal. Cette limitation a été résolue un effectuant des mesures de capacité quasi-statique (QSCV). La signature des Dit a été mise en évidence expérimentalement et expliquée physiquement. Dans le cas d'échantillons passivés, les mesures QSCV sont plus sensibles à l'interface silicium-BOX. Pour les échantillons non passivés, un grand pic dû à des défauts d'interface apparait pour des valeurs d'énergie bien identifiées et correspondant aux défauts à l'interface film de silicium-oxyde natif. Nous présentons des mesures de bruit à basses fréquences, ainsi qu'un model physique démontrant que le signal émerge de régions localisées autour des contacts source et drain. / Silicon-on-insulator (SOI) substrates represent the best solution to achieve high performance devices. Electrical characterization methods are required to monitor the material quality before full transistor fabrication. The classical configuration used for SOI measurements is the pseudo-MOSFET. In this thesis, we focused on the enrichment of techniques in Ψ-MOSFET for the characterization of bare SOI and III-V wafers. The experimental setup for static ID-VG was improved using a vacuum contact for the back gate, increasing the measurement stability. Furthermore, this contact proved to be critical for achieving correct capacitance values with split-CV and quasi-static techniques (QSCV). We addressed the possibility to extract Dit values from split-CV and we demonstrated by modeling that it is impossible in typical sized SOI samples because of the time constant associated to the channel formation. The limitation was solved performing QSCV measurements. Dit signature was experimentally evidenced and physically described. Several SOI structures (thick and ultra-thin silicon films and BOX) were characterized. In case of passivated samples, the QSCV is mostly sensitive to the silicon film-BOX interface. In non-passivated wafers, a large defect related peak appears at constant energy value, independently of the film thickness; it is associated to the native oxide present on the silicon surface. For low-frequency noise measurements, a physical model proved that the signal arises from localized regions surrounding the source and drain contacts.

Alle laktierenden Ziegen aus 12 hessischen Milchziegen-Betriebe wurden über einen Zeitraum von 2 Jahren beprobt. 83,6 % der 2038 Hälftegemelksproben waren kulturell negativ. 10,7 % der bakteriologisch positiven Proben waren Koagulase-negative Staphylokokken. Zur KNS-Differenzierung wurden Kulturmorphologie, ID32 Staph-Test, in-vitro-Sensitivität gegenüber Antibiotika und die t-DNA-PCR angewandt. Keines dieser Verfahren konnte alleinig zur Identifizierung der KNS-Isolate erfolgreich angewandt werden, nur die Kombination der Verfahren war zielführend. Nachgewiesen wurden die Spezies S. caprae, S. epidermidis, S. simulans, S. hyicus, S. saprophyticus, S. chromogenes, S. lentus, S. xylosus und S. hominis. Weiterhin wurde nach Methoden gesucht, um die subklinische Mastitis der Ziege diagnostizieren zu können. Hier erscheint der Vergleich der Zellzahl beider Euterhälften einer Ziege geeignet, um eine subklinische Mastitis abgrenzen zu können. Aufgrund der erhöhten Zellzahl, der Erregernachweis in Reinkultur sowie des Vergleichs mit der kultur-bakteriologisch negativen Euterhälfte erscheint die ätiologische Bedeutung der nachgewiesenen KNS-Isolate als Mastitiserreger der Ziege wahrscheinlich. / All lactating goats out of 12 hessian Dairy-goat-farms were being tested over a period of 2 years. 83,6 % of 2038 half-milk-samples were bacteriological negative. 10,7 % of the bacteriological positive samples were Coagulase-negative staphylococci. For KNS-differentiation morphology of culture, ID 32 Staph Test, in-vitro-sensitivity against antibiotics and t-DNA-PCR were evaluated. None of these methods could be used alone to identify the CNS isolates, the combination of the methods led to results. The species S. caprae, S. epidermidis, S. simulans, S. hyicus, S. saprophyticus, S. chromogenes, S. lentus, S. xylosus and S. hominis were found. Further it was searched for methods to diagnose subclinical mastitis of goats. The comparison of cell amount of both udder halfs of a goat seems to be adequate to diagnose subclinical mastitis. Because of increased cell amount, proof of agent in pure culture and comparison with the bacteriological negative udder half the etiological impact of the detected CNS-Isolates as causative agents of goat-mastitis is likely.

Les potentialités du nitrure de gallium (GaN) et notamment de l'hétérostructure AlGaN/GaN, semiconducteur à large bande interdite, en font un matériau particulièrement intéressant en électronique de puissance, notamment pour des applications haute tension, haute température et haute fréquence. L'objectif de ce travail de thèse était de développer et d'optimiser l'étape d'isolation de la grille lors la réalisation de transistors MIS-HEMT de puissance sur hétérostructure AlGaN/GaN, le but étant de réduire les courants de fuite de grille sans perturber les propriétés du transistor. Après avoir évaluation, le choix s'est porté sur l'alumine Al2O3 déposé par ALD comme diélectrique de grille. L'étude s'est d'abord concentrée sur l'analyse de l'influence de traitements, chimiques ou plasma, sur la contamination de la surface d'AlGaN au travers d'analyses XPS et AFM. Puis, l'influence du diélectrique de grille a été évalué à travers la réalisation et la mesure électrique de dispositifs, diodes et transistors, en variant les méthodes de dépôt par ALD. Enfin, l'impact d'un recess par gravure ICP-RIE partielle ou complètes de la barrière d'AlGaN sous la grille a été étudiée. La réalisation d'un HEMT passe par l'étape critique du dépôt du diélectrique de grille sur le semiconducteur, et le contrôle de la qualité de l'interface " diélectrique/AlGaN " est donc une étape fondamentale car elle influe sur les propriétés électriques du composant. Ce contrôle comprend le traitement de surface du semiconducteur, mais aussi la nature et la technique de dépôt du diélectrique. Ainsi il apparaît à travers l'étude qu'un traitement de surface à l'ammoniaque à haute température est le plus efficaces pour retirer les contamination en oxydes natifs. Les mesures électriques, C(V) et Id(Vg), ont quant à elle montrés la supériorité de la PEALD par rapport à un dépôt thermique conventionnel. Ceci peut s'expliquer par le fait que le plasma oxygène qui entre jeu lors du dépôt de l'alumine par PEALD semble nettoyer la surface lors des premiers cycles, retirant notamment la contamination carbone. Cela permet d'avoir une meilleure interface entre l'alumine et le semi-conducteur, limitant les pièges à l'interface et dans l'oxyde. Cela a réduit de manière considérable les courants de fuite de grille, sans détériorer la qualité et la rapidité de la transition entre l'état on et off. De plus, les HEMTs réalisé étant de type normally-off, le recess de grille par gravure ICP-RIE a été implémenté afin de rendre moins négative la tension de pincement. Cela a été réalisé avec succès, notamment avec la réalisation d'un composant de type noramlly-off grâce à un recess total de la barrière d'AlGaN sous la grille. Des résultats à l'état de l'art ont été obtenus à travers une approche simple, et un processus de création de transistors robuste et hautement reproductible, avec une réduction importante des courants de fuite de grille et une pente sous le seuil record. Afin de compléter l'étude il conviendra par la suite de réaliser des études de fiabilité, notamment à travers des mesures dynamiques pour évaluer notamment les phénomènes de dégradation du Ron. / With its large band gap, Gallium Nitride (GaN) semiconductor is one of the most promising materials for new power devices generation thanks to its outstanding material properties for high voltage, temperature and frequency applications. The main objective of this thesis was the development and optimization of the insulating step taking place in the elaboration of MIS-HEMT transistors on an AlGaN/GaN heterstroctructure. In order to reduce gate leakage currents without degrading the device properties, alumina Al2O3 deposited by ALD was chosen as a gate dielectric. The study was first centered on the influence of surface treatments, chemical or plasma, regarding surface contamination. Their impact was analyzed through XPS and AFM. Secondly, electrical measures were performed on complete MIS-HEMT diodes and transistors to evaluate the influence of the alumina insulating layer depending on the ALD deposition method. Lastly, partial and full recess of the AlGaN barrier was studied via ICP-RIE etching. The gate dielectric deposition is one of the crucial steps intervening in the HEMT creation process. The quality and control at the Al2O2/AlGaN interface being paramount, it will directly influence the device's electric properties. This involves control ing the semiconductor surface, but also the nature and deposition technique of the dielectric. As such, an ammonia-based treatment at high temperature appears to be the most efficient in reducing native oxygen contamination. Regarding electric performances, C(V) and Id(Vg) measures showed the superiority of PEALD compared to traditional thermal ALD deposition. This can be explained by the fact that the oxygen plasma used as oxydant during the alumina deposition by PEALD seems to clean the surface during the first cycles, mostly by reducing carbon contamination. This allowed to achieve a better interface between the semiconductor and the insulting layer, thus limiting traps at the interface or in the oxyde. This allows to considerably reduce gate leakage currents, without degrading the quality and transition sharpness between the on and off state. Moreover, the realized HEMTs being normally-off, gate recess etching via ICP-RIE was implemented in order to make the threshold voltage less negative. This was successfully achieved, especially through the realization of a normally-off transistors thanks to a full recess of the AlGaN barrier under the gate. State of the art results were achieved through a simple approach, and a robust and highly reproducible transistor elaboration process, with great reduction of gate leakage currents and a record sub-threshold slope. In order to complete the study, it will be necessary in the future to proceed to viability studies, especially through dynamic electric evaluation, in order to evaluate for instance Ron degradation phenomenons.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / For many years VME has been the platform of choice for high-performance, real-time data acquisition systems. VME’s longevity has been made possible in part by timely enhancements which have expanded system bandwidth and allowed systems to support ever increasing throughput. One of the most recent ANSI-standard extensions of the VME specification defines RACEway, a system of dynamically switched, 160 Mbyte/second board-to-board interconnects. In typical systems RACEway increases the internal bandwidth of a VME system by an order of magnitude. Since this bandwidth is both scaleable and deterministic, it is particularly well suited to high-performance, real-time systems. The potential of RACEway for very high-performance (200 Mbps to 1 Gbps) real-time systems has been recognized by both the VME industry and a growing number of system integrators. This recognition has yielded many new RACEway-ready VME products from more than a dozen vendors. In fact many significant real-time data acquisition systems that consist entirely of commercial-off-the-shelf (COTS) RACEway products are being developed and fielded today. This paper provides an overview of RACEway technology, identifies the types of RACEway equipment currently available, discusses how RACEway can be applied in high-performance data acquisition systems, and briefly describes two systems that acquiring and capturing real-time data streams at rates from 200 Mbps to 1 Gbps using RACEway.

Sob o modelo de criptografia de chave pública baseada em identidades (ID-PKC), a própria identidade dos usuários é usada como chave pública, de modo a dispensar a necessidade de uma infra-estrutura de chaves públicas (ICP), na qual o gerenciamento de certificados digitais é complexo. Por outro lado, sistemas nesse modelo requerem uma entidade capaz de gerar chaves secretas. Essa entidade é conhecida por PKG (Private Key Generator); ela possui uma chave-mestra e mantém custódia das chaves secretas geradas a partir dessa chave-mestra. Naturalmente, a custódia de chaves é indesejável em muitas aplicações. O conceito de Criptografia de Chave Pública sem Certificado, ou Certificateless Public Key Cryptography (CL-PKC), foi proposto para que a custódia de chaves fosse eliminada, mantendo, porém, as características de interesse: a não necessidade de uma ICP e a eliminação de certificados digitais. CL-PKC deixa de ser um sistema baseado em identidades, pois é introduzida uma chave pública, gerada a partir de uma informação secreta do usuário. Nesta dissertação, apresentamos a construção de dois esquemas, um CL-PKE e um CL-PKS, baseados em emparelhamentos bilineares sobre curvas elípticas. Ambas propostas: (1) eliminam custódia de chaves; (2) dispensam certificados digitais; (3) são mais eficientes, sob certos aspectos, que esquemas anteriormente publicados; (4) e são seguros contra ataques adaptativos de texto cifrado escolhido (em CL-PKE) e contra ataques adaptativos de mensagem escolhida (em CL-PKS), sob o modelo de oráculos aleatórios. / Under the model of Identity Based Cryptography (ID-PKC), the public key can be the user's identity, therefore it does not require a Public Key Infrastructure (PKI) with its complex management of Digital Certificates. On the other hand, this system requires a Private Key Generator (PKG), a trusted authority who is in possession of a master key and can generate any of the private keys. In this way, PKG can exercise the so-called key escrow, which is undesirable in many applications. The concept of Certificateless Public Key Cryptography (CL-PKC) was proposed in order to remove the key escrow characteristic of IBC, while it does not require PKI neither Digital Certificates to certify the public keys. CL-PKC is no more an IBC because public keys are introduced, to bind the identities with its secret keys. In this thesis we construct two schemes, one CL-PKE and one CL-PKS, based on bilinear pairing functions which: (1) does not allow key escrow by the PKG; (2) does not require Digital Certificates; (3) is more efficient, in some aspects, than previously published CL-PKE and CL-PKS schemes; (4) and is secure in the sense that it is strong against adaptive chosen ciphertext attacks (in CL-PKE) and adaptive chosen message attacks (in CL-PKS), under Random Oracle Model.