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Abiotic transformation of compounds in the natural environment by metal oxides plays a significant a role in contaminant fate and behavior in soil. The ability of birnessite, ferrihydrite and green rust to abiotically transform insensitive munitions compounds (IMCs) parent (2,4 dinitroanisole [DNAN] and 3-nitro-1,2,4-triazol-5-one [NTO]), and daughter products (2-methoxy-5-nitro aniline [MENA], 2,4-diaminoanisole [DAAN]of DNAN; and 5-amino-1, 2, 4-triazol-3-one [ATO] of NTO) was studied in batch reactors under strictly controlled pH and ionic strength. The objectives of the study were to (i) assess the abiotic transformation potential of soluble DNAN, MENA, DAAN, NTO and ATO by birnessite, ferrihydrite and green rust, and (ii) identify inorganic reaction products. The study was carried out at metal oxide solid to IMC solution ratios (SSR) of 0.15, 1.5 and 15 g kg⁻¹ for birnessite and ferrihydrite and 10 g kg⁻¹ for green rust. Aqueous samples were collected at time intervals between 0 to 3 days after the reaction initiation and analyzed using HPLC with UV detection. Results indicated that DNAN was resistant to oxidation by birnessite and ferrihydrite at given solid to solution ratios. MENA was susceptible to rapid oxidation by birnessite (first order rate constant, 𝑘=1.36 h⁻¹ at 15 g kg⁻¹ SSR). The nitro groups from MENA largely mineralized to nitrite (NO₂⁻). In contrast, ferrihydrite did not oxidize MENA. DAAN was susceptible to oxidation by both birnessite and ferrihydrite, but about a six times higher oxidation rate was observed with birnessite (𝑘=1.18 h⁻¹) as compared to ferrihydrite (𝑘=0.22 h⁻¹) at an SSR of 1.5 g kg⁻¹. There was a complete loss of DAAN from solution after 5 min with birnessite at an SSR 15 g kg⁻¹ (𝑘≥90.5 h⁻¹). CO₂ evolution experiments indicate mineralization of 15 and 12 % of carbon associated with MENA and DAAN, respectively; under aerobic conditions with birnessite at an SSR of 15 g kg⁻¹. NTO was resistant to oxidation by birnessite and ferrihydrite at any SSR; however, there was slight initial loss from solution upon reaction with ferrihydrite at 0.15 and 1.5 g kg⁻¹ SSR and complete loss at 15 g kg⁻¹ SSR due to adsorption. ATO was susceptible to oxidation by birnessite and sorption by ferrihydrite. The first order rate constants (𝑘) for ATO with birnessite at 0.15 and 1.5 g kg⁻¹ SSR are 0.04 and 3.03 h⁻¹ respectively. There was complete loss of ATO from solution with birnessite at 15 g kg⁻¹ SSR (𝑘 ≥ 90.2 h⁻¹) within 5 min of reaction. Transformation products analysis revealed urea, CO₂ and N₂ as major reaction products with 44 % urea recovery and recovery of 51.5 % of ATO carbon as CO₂ and 47.8 % of ATO nitrogen as N₂ at 15 g kg⁻¹ SSR. The oxidation of ATO in the presence of birnessite was found to be independent of dissolved O₂. The results indicate that ATO, the major reductive (bio)transformation product of NTO, is readily oxidized by birnessite in soil. NTO was found strongly sorbed to ferrihydrite as compared to that of ATO. The results of the green rust experiment indicate rapid abiotic reduction of parent compounds NTO and DNAN to their reduced aminated daughter products. NTO was generally reductively transformed to 5-amino-1, 2, 4-triazol-3-one (ATO) within 10 min and completely reacted in 20 min. DNAN was rapidly transformed to its reduced daughter products MENA and 4-methoxy-5-nitroaniline (iMENA). The reduction occurred with a distinctive, staggered regioselectivity. Over the first 10 min, the para-nitro group of DNAN was selectively reduced, generating iMENA. Thereafter the ortho-nitro group was preferentially reduced, generating MENA. Both iMENA and MENA were subsequently transformed to the final reduction product DAAN within 1 day. X-ray absorption near edge spectroscopy data suggested oxidative transformation of green rust to lepidocrocite-like mineral forms, accounting for 94 % of the mineral products in the case of NTO reaction as compared to 62 % in the case of DNAN. The results taken as whole suggest that complete abiotic transformation of IMCs could be achieved by coupled stepwise green rust and birnessite treatments.

Afin de suivre le rythme effréné des évolutions des systèmes embarqués et des dispositifs portables, il s’avère aujourd’hui indispensable d’optimiser la gestion de l’énergie sans pour autant compromettre la performance et la robustesse des circuits. Dans ce contexte, cette thèse étudie de nouveaux dispositifs de gestion de l’énergie ainsi que leur mise en œuvre, en combinant deux approches: la logique asynchrone et les techniques de polarisation du substrat (Adaptive Body Biasing - ABB). Cette thèse comporte quatre contributions permettant la conception de circuits asynchrones énergétiquement plus efficaces. 1) Une unité arithmétique et logique (UAL) asynchrone quasi insensible aux délais (Quasi Delay Insensitive - QDI) a été conçue et utilisée pour mener une analyse comparative entre systèmes synchrones et asynchrones. Cette étude démontre notamment  la meilleure efficacité énergétique et la plus grande robustesse des circuits asynchrones QDI, surtout lorsqu’ils fonctionnent à basse tension. 2) Une cellule standard a été spécialement développée pour mettre en œuvre nos schémas d’adaptation dynamique du substrat (ABB) qui ajustent la tension de seuil (Vth) des transistors. En outre, cette cellule s’est révélée très utile pour la détection de fautes transitoires causées par des radiations environnementales. Cette cellule est en outre un élément clé pour exploiter la polarisation du substrat, un des intérêts majeurs de la technologie FD-SOI, et d’améliorer la fiabilité du système. 3) Trois stratégies de polarisation de substrat ont été évaluées. Ces stratégies reposent sur la détection automatique de l’activité des circuits asynchrones QDI et de la polarisation de multiples domaines dans le substrat (Body Biasing Domains - BBD). De plus, une méthode pour analyser l’efficacité énergétique des stratégies de polarisation pour les circuits asynchrones QDI a également été proposée dans le cadre de cette thèse. 4) Enfin, un flot de conception de circuits numériques intégrés a été proposé et développé. Ce flot, basé sur des cellules standards, permet d’exploiter des stratégies de polarisation (ABB) avec plusieurs domaines (BBD) en utilisant la cellule standard spécialement développée. Un testchip a été conçu et fabriqué pour valider notre flot de conception et évaluer l’efficacité de la cellule proposée. / Keeping the fast evolving pace of embedded systems of portable devices require ameliorations of power management techniques, without compromising the circuit performance and robustness. In this context, this thesis studies novel energy management schemes, and how to implement them, by using two main design approaches: asynchronous logic and adaptive body biasing (ABB) techniques. Four main contributions have been done, thus enabling the design of more energy efficient asynchronous circuits. 1) We contributed with the design of a Quasi-delay Insensitive (QDI) asynchronous ALU architecture, used in a comparative analysis of asynchronous versus synchronous systems. This first study has demonstrated the energy efficiency and robustness of QDI circuits, especially if operating at low power supply (Vdd ). 2) We proposed a new body built-in cell for implementing ABB schemes by tuning the circuit threshold voltage (Vth) on-the-fly; and detecting short-duration and long-duration transient faults (TF) caused by environmental radiation. The proposed cell is a key building block to fully benefit from body biasing features of the FD-SOI technology while enhancing system’s reliability. 3) We assessed three different ABB strategies - based on automatic activity detection and multiple body-biasing domains (BBDs) - for QDI asynchronous circuits. Furthermore, a methodology for analyzing energy efficiency of ABB strategies in QDI asynchronous circuits is also proposed in this work. 4) We developed a standard cell-based IC design flow to apply ABB strategies with multiple BBDs by using the proposed body built-in cells. A testchip has been designed and fabricated to validate the developed design flow and the efficacy of the body built-in cell.

Les analyses statiques ont pour but de déterminer les propriétés des programmes au moment de la compilation. Contrairement aux analyses dynamiques, le comportement exact du programme ne peut être connu. Par conséquent, on a recours à des approximations pour remédier à ce manque d'information. Malgré ces approximations, les analyses statiques permettent des optimisations et des transformations efficaces pour améliorer les performances des programmes. Parmi les premières analyses du processus d'optimisation figure l'analyse des pointeurs. Son but est d'analyser statiquement un programme en entrée et de fournir en résultat une approximation des emplacements mémoire vers lesquels pointent ses variables pointeurs. Cette analyse est considérée comme l'une des analyses de programmes les plus délicates et l'information qu'elle apporte est très précieuse pour un grand nombre d'autres analyses clientes. En effet, son résultat est nécessaire à d'autres optimisations, comme la propagation de constante, l'élimination du code inutile, le renommage des scalaires ainsi que la parallélisation automatique des programmes. L'analyse des pointeurs est très nécessaire pour l'exploitation du parallélisme présent dans les applications scientifiques écrites en C. Ceci est dû au fait que les tableaux, très présents dans ce type d'applications, sont accédés via les pointeurs. Il devient nécessaire d'analyser les dépendances entre les éléments de tableau dans le but de paralléliser les boucles. Le langage C présente beaucoup de difficultés lors de son analyse par la liberté qu'il offre aux utilisateurs pour gérer et manipuler la mémoire par le biais des pointeurs. Ces difficultés apparaissent par exemple lors de l'accès aux tableaux par pointeurs, l'allocation dynamique (via «malloc») ainsi que les structures de données récursives. L'un des objectifs principaux de cette thèse est de déterminer les emplacements mémoire vers lesquels les pointeurs pointent. Ceci se fait en assurant plusieurs dimensions comme : - la sensibilité au flot de contrôle, c'est-à-dire la mise à jour des informations d'un point programme à un autre ; - la non-sensibilité au contexte, c'est-à-dire l'utilisation de résumés au lieu de l'analyse du corps de la fonction à chaque appel ; - la modélisation des champs pointeurs des structures de données agrégées, dans laquelle chaque champ représente un emplacement mémoire distinct. D'autres aspects sont pris en compte lors de l'analyse des programmes écrits en C comme la précision des emplacements mémoire alloués au niveau du tas, l'arithmétique sur pointeurs ou encore les pointeurs vers tableaux. Notre travail permet l'amélioration des résultats des analyses clientes et en particulier il permet la parallélisation des boucles lorsqu'on accède aux éléments de tableaux via les pointeurs, la détection de code inutile ou le calcul du graphe de dépendances. Il est implémenté dans le compilateur parallélliseur PIPS (Parallélisation Interprocédurale de Programmes Scientifiques) et permet d'analyser, en particulier, les applications scientifiques de traitement du signal tout en assurant une analyse intraprocédurale précise et une analyse interprocédurale efficace via les résumés. / Static analysis algorithms strive to extract the information necessary for the understanding and optimization of programs at compile time. The potential values of the variables of type pointer are the most difficult information to determine. This information is often used to assess if two pointers are potential aliases, i.e. if they can point to the same memory area. An analysis of pointers, also called points-to analysis, may provide more precision to other analyses such as constant propagation, analysis of dependencies or analysis of live variables. The analysis of pointers is very important for the exploitation of parallelism in scientific C programs since the most important structures they manipulate are arrays, which are typically accessed by pointers. It is necessary to analyse the dependencies between arrays in order to exploit the parallelism between loops. C language is very hard to analyse since it allows to users to manipulate the memory through pointers. These difficulties arise for example when accessing arrays by pointers, dynamic allocation (via "malloc") and recursive data structures. Points-to analysis may also attempt to handle recursive data structures and other structures that are accessed by pointers. This work provides a points-to analysis which is : - flow-sensitive, by taking into account the order of execution of instructions ; - field-sensitive, since structure fields are treated as individual locations ; - context-insensitive, because functions summaries are computed to avoid re-analyzing functions bodies. Other issues such as heap modeling, pointer arithmetics and pointers to arrays are also taken into account while analyzing C programs. Our intraprocedural analysis provides precise results to client analyses, in particular it allows parallelization when accessing the array elements loops via pointers, detecting useless code or computing the dependency graph. while our interprocedural one allows to propagate them efficiently. Our work is implemented within the PIPS (Parallélisation Interprocédurale de Programmes Scientifiques) parallelizer, a framework designed to analyze, optimize and parallelize scientific and signal processing applications. Keywords : static analysis, points-to analysis, flow-sensitive, context-insensitive, field-sensitive.

This master thesis deals with the realization of a simulator based on asynchronous cellular automata simulating delay insensitive circuits. In connection with nanotechnology, cellular automata have several interesting properties, such as self-replication, regular structure and high parallelism that make them very useful as models for some types of nanocomputers. This text describes the relationship between cellular automata and nanotechnology. Emphasis is given to the possibility of using asynchronous timing mode. Asynchronous cellular arrays based on asynchronous cellular automata could prove to be a suitable architecture for future nanocomputer, which was the reason for implementation of this simulator. The simulator's functionality was verified by experiments.

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

To determine whether a weapon system meets the requirements set for insensitivity, the system is getting exposed for special tests. One of these tests shows how the system reacts when it ends up in a fire. This test is called the "Fast Cook-Off (FCO) Test", called FCO-test, and performed with a Sand Bed Burner (SBB). According to primary testing provision, the fuel for this test is used of jet fuel such as Jet A-1. A project at Bofors Test Center (BTC) is in progress to use an alternative fuel of Liquefied Petroleum Gas (LPG). This fuel is very advantageous compared to jet fuel in terms of environmental impact, work environment and testing costs. The aim of this thesis is to improve the existing test equipment considering fire over the entire surface and solve the problems with dropped gas flow and freezing of gas bottles. SBB works in the sense that the new petrol LPG streams into the SBB and expands in the free space below the sand bed before the gas will diffuse through the bed of sand and the fire engulfs the object. LPG is a condensable gas that requires oxygen. LPG exceed from liquid to gas phase and needs a large lateral surface to take up more energy which results in better evaporationto the phase transfer. Reaction products from complete combustion of LPG are only water vapor and carbon dioxide, the same as in your exhaled air. To solve these problems it was needed to change P11 composite bottles to P45 steel bottles to get a longer evaporation and larger lateral surface. Four flow inlets instead were used of one into SBB for a better stream in the free space under the sand bed. Propane regulators used to get a lower and more constant flow to avoid freezing. Compressed airconnected tothe SBB to geta mix between oxygen and LPG. The result shows in higherheat radiation efficiency even though the flow was settled down to 1/3 with the new propane regulators. In test 2 the value was 37 kW/m2 and in test 7 it was around 57 kW/m2. Because of a smaller flow and bigger steel bottles the freezing disappeared. Smaller grain of sand together with four inlets and compressed air gave a more complete combustion.

Enterprise Service Bus (ESB) est actuellement l'approche la plus prometteuse pour l'implémentation d'une architecture orientée services (SOA : Service-Oriented Architecture) par l'intégration des différentes applications isolées dans une plateforme centralisée. De nombreuses solutions d'intégration à base d'ESB on été proposées, elles sont soit open-source comme : Mule, Petals, ou encore Fuse, soit propriétaires tels que : Sonic ESB, IBM WebSphere Message Broker, ou Oracle ESB. Cependant, il n'en existe aucune en mesure de traiter, à la fois des aspects : d'intégration et de traitement massivement parallèle, du moins à notre connaissance. L'intégration du parallélisme dans le traitement est un moyen de tirer profit des technologies multicœurs/multiprocesseurs qui améliorent considérablement les performances des ESBs.Toutefois, cette intégration est une démarche complexe et soulève des problèmes à plusieurs niveaux : communication, synchronisation, partage de données, etc.Dans cette thèse, nous présentons l'étude d'une nouvelle architecture massivement parallèle de type ESB. / Enterprise service bus (ESB) is currently the most promising approach for business application integration in distributed and heterogeneous environments. It allows to deploy a service-oriented architecture (SOA) by the integration of all the isolated applications on a decentralized platform.Several commercial or open source ESB-based solutions have been proposed. However, to the best of our knowledge, none of these solutions has integrated the parallel processing. The integration of parallelism in the treatment allows to take advantage of the multicore/multiprocessor technologies and thus can improve greatly the ESB performance. However, this integration is difficult to achieve, and poses problems at multiple levels (communication, synchronization, etc). In this study, we present a new massively parallel ESB architecture that meets this challenge.

Multi-standard RF front-end is a critical part of legacy and future emerging mobile architectures, where the size, the efficiency, and the integration of the elements in the RF front-end will affect the network key performance indicators (KPIs). This chapter discusses power amplifier design for both handset and base station applications for 5G and beyond. Also, this chapter deals with filter-antenna design for 5G applications that include a synthesis-based approach, differentially driven reconfigurable planar filter-antenna, and an insensitive phased array antenna with air-filled slot-loop resonators.

<p>Minimum cycle mean (MCM) is an important concept in directed graphs. From clock period optimization, timing analysis to layout optimization, minimum cycle mean algorithms have found widespread use in VLSI system design optimization. With transistor size scaling to 10nm and below, complexities and size of the systems have grown rapidly over the last decade. Scalability of the algorithms both in terms of their runtime and memory usage is therefore important. </p> <p><br></p> <p>Among the few classical MCM algorithms, the algorithm by Young, Tarjan, and Orlin (YTO), has been particularly popular. When implemented with a binary heap, the YTO algorithm has the best runtime performance although it has higher asymptotic time complexity than Karp's algorithm. However, as an efficient implementation of YTO relies on data redundancy, its memory usage is higher and could be a prohibitive factor in large size problems. On the other hand, a typical implementation of Karp's algorithm can also be memory hungry. An early termination technique from Hartmann and Orlin (HO) can be directly applied to Karp's algorithm to improve its runtime performance and memory usage. Although not as efficient as YTO in runtime, HO algorithm has much less memory usage than YTO. We propose several improvements to HO algorithm. The proposed algorithm has comparable runtime performance to YTO for circuit graphs and dense random graphs while being better than HO algorithm in memory usage. </p> <p><br></p> <p>Minimum balancing of a directed graph is an application of the minimum cycle mean algorithm. Minimum balance algorithms have been used to optimally distribute slack for mitigating process variation induced timing violation issues in clock network. In a conventional minimum balance algorithm, the principal subroutine is that of finding MCM in a graph. In particular, the minimum balance algorithm iteratively finds the minimum cycle mean and the corresponding minimum-mean cycle, and uses the mean and cycle to update the graph by changing edge weights and reducing the graph size. The iterations terminate when the updated graph is a single node. Studies have shown that the bottleneck of the iterative process is the graph update operation as previous approaches involved updating the entire graph. We propose an improvement to the minimum balance algorithm by performing fewer changes to the edge weights in each iteration, resulting in better efficiency.</p> <p><br></p> <p>We also apply the minimum cycle mean algorithm in latency insensitive system design. Timing violations can occur in high performance communication links in system-on-chips (SoCs) in the late stages of the physical design process. To address the issues, latency insensitive systems (LISs) employ pipelining in the communication channels through insertion of the relay stations. Although the functionality of a LIS is robust with respect to the communication latencies, such insertion can degrade system throughput performance. Earlier studies have shown that the proper sizing of buffer queues after relay station insertion could eliminate such performance loss. However, solving the problem of maximum performance buffer queue sizing requires use of mixed integer linear programming (MILP) of which runtime is not scalable. We formulate the problem as a parameterized graph optimization problem where for every communication channel there is a parameterized edge with buffer counts as the edge weight. We then use minimum cycle mean algorithm to determine from which edges buffers can be removed safely without creating negative cycles. This is done iteratively in the similar style as the minimum balance algorithm. Experimental results suggest that the proposed approach is scalable. Moreover, quality of the solution is observed to be as good as that of the MILP based approach.</p><p><br></p>