Cette thèse porte sur la compréhension et le développement de matériaux innovants en tant que composant actif pour les mémoires résistives à changement de valence (VCM), qui constitue une sous-catégorie des mémoires résistives où des réactions d’oxydoréduction sont à l’origine du mécanisme de commutation résistive. Leur incorporation dans les circuits intégrés nécessite une tension (ou un courant) électrique pour lire et programmer la mémoire, cependant leurs fonctionnalités dépend essentiellement des propriétés chimiques des matériaux constituant la mémoire. Dans ce manuscrit nous étudions les propriétés du composé La2NiO4+δ, un conducteur mixte d’ions et d’électrons qui de par sa conduction d’ions oxydes dans le volume du matériau offre un terrain de jeu prometteur pour les VCMs. Nous avons pu obtenir des films minces de La2NiO4+δ fortement texturés sur des substrats monocristallins de SrTiO3 par dépôt chimique en phase vapeur à partir de l’injection pulsée de précurseurs métalorganiques (PiMOCVD). Des recuits sous atmosphère contrôlée ont permis de faire varier le contenu en oxygène et d’ajuster les propriétés semiconductrices-type p de La2NiO4+δ par un mécanisme d’auto-dopage. Une sur-stœchiométrie en oxygène dans la plage 0 ≤ δ ≤ 0.08 induit une variation de résistivité de 5.7 Ω.cm à 5.3x10-3 Ω.cm pour un recuit sous hydrogène ou sous oxygène, respectivement. Les films minces de La2NiO4+δ ont ensuite été utilisés comme base dans la conception d’hétérostructures métal/La2NiO4+δ/métal. Le rôle important de la jonction métal/oxyde sur les propriétés des VCMs de type interfaciales est discuté en détails. En particulier, un contact ohmique avec La2NiO4+δ est obtenu en utilisant un matériau d’électrode tel que le Pt ayant un travail de sortie élevé, alors qu’un contact rectifiant est obtenu avec Ti résultant de la présence d’une fine couche (~8 nm) de TiOx formée de manière spontanée à l’interface Ti/La2NiO4+δ. Une hétérojunction asymétrique Pt/La2NiO4+δ/Ti a été sélectionnée comme prototype afin d’évaluer les propriétés memristives de composants basés sur La2NiO4+δ. Un changement de résistance bipolaire a été mesuré ainsi qu’une possibilité de programmation largement multi-niveaux lorsque la mémoire est stimulée de manière pulsée. Les résultats prometteurs obtenus par ce premier prototype sont ensuite étendus pour la première fois à un système plus complexe de bicouches La2NiO4+δ/LaNiO3. Des propriétés de relaxation ont été mesurées, rendant ces mémoires intéressantes pour leur utilisation en tant que mémoire volatile pour un filtrage dynamique dans des applications neuromorphiques. / This thesis is focused on the understanding and development of novel materials for valence-change memories (VCMs), a type of resistive switching memories in which the memory storage mechanism is based on internal redox reactions. VCMs are in essence electrochemical systems. Their implementation in integrated electronic circuits relies on a voltage (or current) to measure and operate the memory, but their functionality is highly dependent on the chemical properties of the materials constituting the memory. In this work we present how the mixed ionic-electronic conducting La2NiO4+δ compound offers an interesting playground for VCM applications due to its intrinsic bulk oxygen-ion conducting properties. We have successfully prepared La2NiO4+δ in the form of highly oriented thin films on SrTiO3 single crystal substrates using pulsed-injection chemical vapour deposition (PiMOCVD). Post-annealing treatments in oxidizing/reducing atmospheres allow tuning the oxygen content and the p-type semiconducting properties of La2NiO4+δ due to a self-doping mechanism. The obtained oxygen over-stoichiometry in the 0 ≤ δ ≤ 0.08 range induced a variation of the film resistivity between 5.7 Ω.cm and 5.3x10-3 Ω.cm for hydrogen or oxygen-annealed samples, respectively. The optimized La2NiO4+δ thin films have been used as a base for the microfabrication of metal/La2NiO4+δ/metal heterostructures. The important role of the metal/oxide junction in interface-type VCMs is discussed in detail. In particular, an ohmic contact is obtained with La2NiO4+δ when using a high work function metal such as Pt, while rectifying contact properties are obtained when using Ti due to the presence of a spontaneously-formed TiOx interlayer (~8 nm) at the Ti/L2NO4 interface. An asymmetric Pt/La2NiO4+δ/Ti heterojunction has been selected as a first prototype to assess the memory capabilities of a La2NiO4+δ-based memristive device. A continuous bipolar analogue-type memory behaviour has been measured, together with strong multilevel programing capabilities when operated in pulsed mode. In addition, the promising results offered by this prototypical device have been extended for the first time to La2NiO4+δ/LaNiO3 bilayers, showing memory relaxation properties, which are potentially interesting for short-term memory and filtering applications in neuromorphic-based computational hardware.

Future computing will require significant development in new computing device paradigms. This is motivated by CMOS devices reaching their technological limits, the need for non-Von Neumann architectures as well as the energy constraints of wearable technologies and embedded processors. The first device proposal, an energy-efficient voltage-controlled domain wall device for implementing an artificial neuron and synapse is analyzed using micromagnetic modeling. By controlling the domain wall motion utilizing spin transfer or spin orbit torques in association with voltage generated strain control of perpendicular magnetic anisotropy in the presence of Dzyaloshinskii-Moriya interaction (DMI), different positions of the domain wall are realized in the free layer of a magnetic tunnel junction to program different synaptic weights. Additionally, an artificial neuron can be realized by combining this DW device with a CMOS buffer. The second neuromorphic device proposal is inspired by the brain. Membrane potential of many neurons oscillate in a subthreshold damped fashion and fire when excited by an input frequency that nearly equals their Eigen frequency. We investigate theoretical implementation of such “resonate-and-fire” neurons by utilizing the magnetization dynamics of a fixed magnetic skyrmion based free layer of a magnetic tunnel junction (MTJ). Voltage control of magnetic anisotropy or voltage generated strain results in expansion and shrinking of a skyrmion core that mimics the subthreshold oscillation. Finally, we show that such resonate and fire neurons have potential application in coupled nanomagnetic oscillator based associative memory arrays.

Engineers often view variability as undesirable and seek to minimize it, such as when they employ transistor-matching techniques to improve circuit and system performance. Biology, however, makes no discernible attempt to avoid this variability, which is particularly evident in biological nervous systems whose neurons exhibit marked variability in their cellular properties. In previous studies, this heterogeneity has been shown to have mixed consequences on network rhythmicity, which is essential to locomotion and other oscillatory neural behaviors. The systems that produce and control these stereotyped movements have been optimized to be energy efficient and dependable, and one particularly well-studied rhythmic network is the central pattern generator (CPG), which is capable of generating a coordinated, rhythmic pattern of motor activity in the absence of phasic sensory input. Because they are ubiquitous in biological preparations and reveal a variety of physiological behaviors, these networks provide a platform for studying a critical set of biological control paradigms and inspire research into engineered systems that exploit these underlying principles. We are directing our efforts toward the implementation of applicable technologies and modeling to better understand the combination of these two concepts---the role of heterogeneity in rhythmic networks of neurons. The central engineering theme of our work is to use digital and analog platforms to design and build Hodgkin--Huxley conductance-based neuron models that will be used to implement a half-center oscillator (HCO) model of a CPG. The primary scientific question that we will address is to what extent this heterogeneity affects the rhythmicity of a network of neurons. To do so, we will first analyze the locations, continuities, and sizes of bursting regions using single-neuron models and will then use an FPGA model neuron to study parametric and topological heterogeneity in a fully-connected 36-neuron HCO. We found that heterogeneity can lead to more robust rhythmic networks of neurons, but the type and quantity of heterogeneity and the population-level metric that is used to analyze bursting are critical in determining when this occurs.

Le cerveau humain est composé d’un grand nombre de réseaux neuraux interconnectés, dont les neurones et les synapses en sont les briques constitutives. Caractérisé par une faible consommation de puissance, de quelques Watts seulement, le cerveau humain est capable d’accomplir des tâches qui sont inaccessibles aux systèmes de calcul actuels, basés sur une architecture de type Von Neumann. La conception de systèmes neuromorphiques vise à réaliser une nouvelle génération de systèmes de calcul qui ne soit pas de type Von Neumann. L’utilisation de mémoire non-volatile innovantes en tant que synapses artificielles, pour application aux systèmes neuromorphiques, est donc étudiée dans cette thèse. Deux types de technologies de mémoires sont examinés : les mémoires à changement de phase (Phase-Change Memory, PCM) et les mémoires résistives à base d’oxyde (Oxide-based resistive Random Access Memory, OxRAM). L’utilisation des dispositifs PCM en tant que synapses de type binaire et probabiliste est étudiée pour l’extraction de motifs visuels complexes, en évaluant l’impact des conditions de programmation sur la consommation de puissance au niveau du système. Une nouvelle stratégie de programmation, qui permet de réduire l’impact du problème de la dérive de la résistance des dispositifs PCM est ensuite proposée. Il est démontré qu’en utilisant des dispositifs de tailles réduites, il est possible de diminuer la consommation énergétique du système. La variabilité des dispositifs OxRAM est ensuite évaluée expérimentalement par caractérisation électrique, en utilisant des méthodes statistiques, à la fois sur des dispositifs isolés et dans une matrice complète de mémoire. Un modèle qui permets de reproduire la variabilité depuis le niveau faiblement résistif jusqu’au niveau hautement résistif est ainsi développé. Une architecture de réseau de neurones de type convolutionnel est ensuite proposée sur la base de ces travaux éxperimentaux. La tolérance du circuit neuromorphique à la variabilité des OxRAM est enfin démontrée grâce à des tâches de reconnaissance de motifs visuels complexes, comme par exemple des caractères manuscrits ou des panneaux de signalisations routières. / The human brain is made of a large number of interconnected neural networks which are composed of neurons and synapses. With a low power consumption of only few Watts, the human brain is able to perform computational tasks that are out of reach for today’s computers, which are based on the Von Neumann architecture. Neuromorphic hardware design, taking inspiration from the human brain, aims to implement the next generation, non-Von Neumann computing systems. In this thesis, emerging non-volatile memory devices, specifically Phase-Change Memory (PCM) and Oxide-based resistive memory (OxRAM) devices, are studied as artificial synapses in neuromorphic systems. The use of PCM devices as binary probabilistic synapses is studied for complex visual pattern extraction applications, evaluating the impact of the PCM programming conditions on the system-level power consumption.A programming strategy is proposed to mitigate the impact of PCM resistance drift. It is shown that, using scaled devices, it is possible to reduce the synaptic power consumption. The OxRAM resistance variability is evaluated experimentally through electrical characterization, gathering statistics on both single memory cells and at array level. A model that allows to reproduce OxRAM variability from low to high resistance state is developed. An OxRAM-based convolutional neural network architecture is then proposed on the basis of this experimental work. By implementing the computation of convolution directly in memory, the Von Neumann bottleneck is avoided. Robustness to OxRAM variability is demonstrated with complex visual pattern recognition tasks such as handwritten characters and traffic signs recognition.

L'objectif principal de cette thèse est le développement d'algorithmes événementiels pour la détection et le suivi d'objets. Ces algorithmes sont spécifiquement conçus pour travailler avec une sortie produite par des caméras neuromorphiques. Ce type de caméras sont un nouveau type de capteurs bio inspirés, dont le principe de fonctionnement s'inspire de la rétine: chaque pixel est indépendant et génère des événements de manière asynchrone lorsqu'un changement de luminosité suffisamment important est détecté à la position correspondante du plan focal. Cette nouvelle façon d'encoder l'information visuelle requiert de nouvelles méthodes pour la traiter. D'abord, un suiveur (tracker) plan est décrit. Cet algorithme associe à un objet une série de formes simples reliées par des ressorts. Le système mécanique virtuel résultant est mis à jour pour chaque événement. Le chapitre suivant présente un algorithme de détection de lignes et de segments, pouvant constituer une caractéristique (feature) événementielle de bas niveau. Ensuite, deux méthodes événementielles pour l'estimation de la pose 3D sont présentées. Le premier de ces algorithmes 3D est basé sur l'hypothèse que l'estimation de la pose est toujours proche de la position réelle, et requiert donc une initialisation manuelle. Le deuxième de ces algorithmes 3D est conçu pour surmonter cette limitation. Toutes les méthodes présentées mettent à jour l'estimation de la position (2D ou 3D) pour chaque événement. Cette thèse montre que la vision événementielle permet de reformuler une vaste série de problèmes en vision par ordinateur, souvent donnant lieu à des algorithmes plus simples mais toujours précis. / The main goal of this thesis is the development of event-based algorithms for visual detection and tracking. This algorithms are specifically designed to work on the output of neuromorphic event-based cameras. This type of cameras are a new type of bioinspired sensors, whose principle of operation is based on the functioning of the retina: every pixel is independent and generates events asynchronously when a sufficient amount of change is detected in the luminance at the corresponding position on the focal plane. This new way of encoding visual information calls for new processing methods. First, a part-based shape tracking is presented, which represents an object as a set of simple shapes linked by springs. The resulting virtual mechanical system is simulated with every incoming event. Next, a line and segment detection algorithm is introduced, which can be employed as an event-based low level feature. Two event-based methods for 3D pose estimation are then presented. The first of these 3D algorithms is based on the assumption that the current estimation is close to the true pose of the object, and it consequently requires a manual initialization step. The second of the 3D methods is designed to overcome this limitation. All the presented methods update the estimated position (2D or 3D) of the tracked object with every incoming event. This results in a series of trackers capable of estimating the position of the tracked object with microsecond resolution. This thesis shows that event-based vision allows to reformulate a broad set of computer vision problems, often resulting in simpler but accurate algorithms.

This thesis proposes a novel set of generic and compact biologically plausible VLSI (Very Large Scale Integration) neural circuits, suitable for implementing a parallel VLSI network that closely resembles the function of a small-scale neocortical network. The proposed circuits include a cortical neuron, two different long-term plastic synapses and four different short-term plastic synapses. These circuits operate in accelerated-time, where the time scale of neural responses is approximately three to four orders of magnitude faster than the biological-time scale of the neuronal activities, providing higher computational throughput in computing neural dynamics. Further, a novel biological-time cortical neuron circuit with similar dynamics as of the accelerated-time neuron is proposed to demonstrate the feasibility of migrating accelerated-time circuits into biological-time circuits. The fabricated accelerated-time VLSI neuron circuit is capable of replicating distinct firing patterns such as regular spiking, fast spiking, chattering and intrinsic bursting, by tuning two external voltages. It reproduces biologically plausible action potentials. This neuron circuit is compact and enables implementation of many neurons in a single silicon chip. The circuit consumes extremely low energy per spike (8pJ). Incorporating this neuron circuit in a neural network facilitates diverse non-linear neuron responses, which is an important aspect in neural processing. Two of the proposed long term plastic synapse circuits include spike-time dependent plasticity (STDP) synapse, and dopamine modulated STDP synapse. The short-term plastic synapses include excitatory depressing, inhibitory facilitating, inhibitory depressing, and excitatory facilitating synapses. Many neural parameters of short- and long- term synapses can be modified independently using externally controlled tuning voltages to obtain distinct synaptic properties. Having diverse synaptic dynamics in a network facilitates richer network behaviours such as learning, memory, stability and dynamic gain control, inherent in a biological neural network. To prove the concept in VLSI, different combinations of these accelerated-time neural circuits are fabricated in three integrated circuits (ICs) using a standard 0.35 µm CMOS technology. Using first two ICs, functions of cortical neuron and STDP synapses have been experimentally verified. The third IC, the Cortical Neural Layer (CNL) Chip is designed and fabricated to facilitate cortical network emulations. This IC implements neural circuits with a similar composition to the cortical layer of the neocortex. The CNL chip comprises 120 cortical neurons and 7 560 synapses. Many of these CNL chips can be combined together to form a six-layered VLSI neocortical network to validate the network dynamics and to perform neural processing of small-scale cortical networks. The proposed neuromorphic systems can be used as a simulation acceleration platform to explore the processing principles of biological brains and also move towards realising low power, real-time intelligent computing devices and control systems.

Les architectures d’ordinateur classiques sont optimisées pour le traitement déterministe d’informations pré-formatées et ont donc des difficultés avec des données naturelles bruitées (images, sons, etc.). Comme celles-ci deviennent nombreuses, de nouveaux circuits neuromorphiques (inspirés par le cerveau) tels que les réseaux de neurones émergent. Des nano-dispositifs, appelés memristors, pourraient permettre leur implémentation sur puce avec une haute efficacité énergétique et en s’approchant de la haute connectivité synaptique du cerveau.Dans ce travail, nous étudions des memristors basés sur des jonctions tunnel ferroélectriques qui sont composées d’une couche ferroélectrique ultramince entre deux électrodes métalliques. Nous montrons que le renversement de la polarisation de BiFeO3 induit des changements de résistance de quatre ordres de grandeurs et établissons un lien direct entre les états de domaines mixtes et les niveaux de résistance intermédiaires.En alternant les matériaux des électrodes, nous révélons leur influence sur la barrière électrostatique et les propriétés dynamiques des memristors. Des expériences d’impulsion unique de tension montrent un retournement de polarisation ultra-rapide. Nous approfondissons l’étude de cette dynamique par des mesures d’impulsions cumulées. La combinaison de leur analyse avec de l’imagerie par microscopie à force piézoélectrique nous permet d’établir un modèle dynamique du memristor. Suite à la démonstration de la spike-timing-dependent plasticity, une règle d’apprentissage importante, nous pouvons prédire le comportement de notre synapse artificielle. Ceci représente une avance majeure vers la réalisation de réseaux de neurones sur puce dotés d’un auto-apprentissage non-supervisé. / Classical computer architectures are optimized to process pre-formatted information in a deterministic way and therefore struggle to treat unorganized natural data (images, sounds, etc.). As these become more and more important, the brain inspires new, neuromorphic computer circuits such as neural networks. Their energy-efficient hardware implementations will greatly benefit from nanodevices, called memristors, whose small size could enable the high synaptic connectivity degree observed in the brain.In this work, we concentrate on memristors based on ferroelectric tunnel junctions that are composed of an ultrathin ferroelectric film between two metallic electrodes. We show that the polarization reversal in BiFeO3 films can induce resistance contrasts as high as 10^4 and how mixed domain states are connected to intermediate resistance levels.Changing the electrode materials provides insights into their influence on the electrostatic barrier and dynamic properties of these memristors. Single-shot switching experiments reveal very fast polarization switching which we further investigate in cumulative measurements. Their analysis in combination with piezoresponse force microscopy finally allows us to establish a model describing the memristor dynamics under arbitrary voltage signals. After the demonstration of an important learning rule for neural networks, called spike-timing-dependent plasticity, we successfully predict new, previously unexplored learning curves. This constitutes an important step towards the realization of unsupervised self-learning hardware neural networks.

<div>Neuromorphic computing has gained tremendous interest because of its ability to overcome the limitations of traditional signal processing algorithms in data intensive applications such as image recognition, video analytics, or language translation. The new computing paradigm is built with the goal of achieving high energy efficiency, comparable to biological systems.</div><div>To achieve such energy efficiency, there is a need to explore new neuro-mimetic devices, circuits, and architecture, along with new learning algorithms. To that effect, we propose two main approaches:</div><div><br></div><div>First, we explore an energy-efficient hardware implementation of a bio-plausible Spiking Neural Network (SNN). The key highlights of our proposed system for SNNs are 1) addressing connectivity issues arising from Network On Chip (NOC)-based SNNs, and 2) proposing stochastic CMOS binary SNNs using biased random number generator (BRNG). On-chip Power Line Communication (PLC) is proposed to address the connectivity issues in NOC-based SNNs. PLC can use the on-chip power lines augmented with low-overhead receiver and transmitter to communicate data between neurons that are spatially far apart. We also propose a CMOS '<i>stochastic-bit</i>' with on-chip stochastic Spike Timing Dependent Plasticity (sSTDP) based learning for memory-compressed binary SNNs. A chip was fabricated in 90 nm CMOS process to demonstrate memory-efficient reconfigurable on-chip learning using sSTDP training. </div><div><br></div><div>Second, we explored coupled oscillatory systems for distance computation and convolution operation. Recent research on nano-oscillators has shown the possibility of using coupled oscillator networks as a core computing primitive for analog/non-Boolean computations. Spin-torque oscillator (STO) can be an attractive candidate for such oscillators because it is CMOS compatible, highly integratable, scalable, and frequency/phase tunable. Based on these promising features, we propose a new coupled-oscillator based architecture for hybrid spintronic/CMOS hardware that computes multi-dimensional norm. The hybrid system composed of an array of four injection-locked STOs and a CMOS detector is experimentally demonstrated. Energy and scaling analysis shows that the proposed STO-based coupled oscillatory system has higher energy efficiency compared to the CMOS-based system, and an order of magnitude faster computation speed in distance computation for high dimensional input vectors.</div>

<div> <div> <div> <p>Process variations and increasing leakage current are major challenges toward memory realization in deeply-scaled CMOS devices. Spintronic devices recently emerged as one of the leading candidates for future information storage due to its potential for non-volatility, high speed, low power and good endurance. In this thesis, we start with the basic concepts and applications of three spintronic devices, namely spin or- bit torque (SOT) based spin-valves, SOT-based magnetic tunnel junctions and the magnetic skyrmion (MS) for both logic and machine learning hardware. </p> <p>We propose a new Spin-Orbit Torque based Domino-style Spin Logic (SOT-DSL) that operates in a sequence of Preset and Evaluation modes of operations. During the preset mode, the output magnet is clocked to its hard-axis using spin Hall effect. In the evaluation mode, the clocked output magnet is switched by a spin current from the preceding stage. The nano-magnets in SOT-DSL are always driven by orthogonal spins rather than collinear spins, which in turn eliminates the incubation delay and allows fast magnetization switching. Based on our simulation results, SOT-DSL shows up to 50% improvement in energy consumption compared to All-Spin Logic. Moreover, SOT-DSL relaxes the requirement for buffer insertion between long spin channels, and significantly lowers the design complexity. This dissertation also covers two applications using MS as information carriers. MS has been shown to possess several advantages in terms of unprecedented stability, ultra-low depinning current density, and compact size. </p><p><br></p><p>We propose a multi-bit MS cell with appropriate peripheral circuits. A systematic device-circuit-architecture co-design is performed to evaluate the feasibility of using MS-based memory as last-level caches for general purpose processors. To further establish the viability of skyrmions for other applications, a deep spiking neural network (SNN) architecture where computation units are realized by MS-based devices is also proposed. We develop device architectures and models suitable for neurons and synapses, provide device-to-system level analysis for the design of an All-Spin Spiking Neural Network based on skyrmionic devices, and demonstrate its efficiency over a corresponding CMOS implementation.</p> <div> <div> <div> <p><br></p><p>Apart from the aforementioned applications such as memory storage elements or logic operation, this research also focuses on the implementation of spin-based device to solve combinatorial optimization problems. Finding an efficient computing method to solve these problems has been researched extensively. The computational cost for such optimization problems exponentially increases with the number of variables using traditional von-Neumann architecture. Ising model, on the other hand, has been proposed as a more suitable computation paradigm for its simple architecture and inherent ability to efficiently solve combinatorial optimization problems. In this work, SHE-MTJs are used as a stochastic switching bit to solve these problems based on the Ising model. We also design an unique approach to map bi-prime factorization problem to our proposed device-circuit configuration. By solving coupled Landau- Lifshitz-Gilbert equations, we demonstrate that our coupling network can factorize up to 16-bit binary numbers. </p> </div> </div> </div> </div> </div> </div>

Cette thèse porte sur l’implémentation d’algorithmes événementiels, en utilisant, dans un premier temps, des données provenant d’une rétine artificielle, mimant le fonctionnement de la rétine humaine, pour ensuite évoluer vers tous types de signaux événementiels. Ces signaux événementiels sont issus d’un changement de paradigme dans la représentation du signal, offrant une grande plage dynamique de fonctionnement, une résolution temporelle importante ainsi qu’une compression native du signal. Sera notamment étudiée la réalisation d’un dispositif de création de cartes de profondeur monoculaires à haute fréquence, un algorithme de tri cellulaire en temps réel, ainsi que l’apprentissage non supervisé pour de la reconnaissance de formes. Certains de ces algorithmes (détection de flot optique, construction de cartes de profondeur en stéréovision) seront développés en parallèle sur des plateformes de simulation neuromorphiques existantes (SpiNNaker, TrueNorth), afin de proposer une chaîne de traitement de l’information entièrement neuromorphique, du capteur au calcul, à faible coût énergétique. / This thesis is about the implementation of neuromorphic algorithms, using, as a first step, data from a silicon retina, mimicking the human eye’s behavior, and then evolve towards all kind of event-based signals. These eventbased signals are coming from a paradigm shift in the data representation, thus allowing a high dynamic range, a precise temporal resolution and a sensor-level data compression. Especially, we will study the development of a high frequency monocular depth map generator, a real-time spike sorting algorithm for intelligent brain-machine interfaces, and an unsupervised learning algorithm for pattern recognition. Some of these algorithms (Optical flow detection, depth map construction from stereovision) will be in the meantime developed on available neuromorphic platforms (SpiNNaker, TrueNorth), thus allowing a fully neuromorphic pipeline, from sensing to computing, with a low power budget.