Η ψηφιακή τεχνολογία έχει διεισδύσει πλήρως στην περιοχή της Ακουστικής και της Τεχνολογίας Ήχου, όπως επίσης και σε όλους σχεδόν τους κλάδους της σύγχρονης επιστήμης και της τεχνολογίας. Στον τομέα των ηλεκτρονικών για ηχητικές εφαρμογές, ιδιαίτερα καθοριστικό ρόλο κατέχουν οι ενι- σχυτές. Σκοπός της εργασίας αυτής, είναι να παρουσιάσει το λειτουργικό μοντέλο ενός ψηφιακού ενι- σχυτή Class-D για ηχητικά σήματα, το οποίο προσομοιώθηκε και λειτούργησε σε περιβάλλον Matlab & Simulink. Στο τέλος παρουσιάζονται τα αποτελέσματα χρήσιμων μετρήσεων για σημαντικούς δεί- κτες της ηλεκτροακουστικής όπως η Απόκριση Συχνότητας, Total Harmonic Distortion(THD), Total Harmonic Distortion plus Noise (THD+N) ως προς τη συχνότητα και ως προς την ισχύ, από όπου βγαίνουν συμπεράσματα σχετικά με την ποιότητα και την απόδοση της συγκεκριμένης τεχνολογίας υλοποίησης. / DigitalTechnology has been fully into Acousctics and Audio Technology,as in virtually all branches of modern science and technology.In audio electronics applications, amplifiers have a significant role. The purpose of this thesis is to present the functional model of a digital Class-D amplifier for audio signals, which has been simulated and run in Matlab & Simulink environment. Finally the results of measurements relating to some important electroacoustics indexes like Frequency Response, Total Harmonic Distortion (THD), Total Harmonic Distortion plus Noise (THD+N), relative to the audio signal’s frequency and power, are presented and lead to some conclusions concerning the quality and efficiency of this implementation technology.

A new generation of electronic devices has emerged requiring micro-watt-level power supply to operate. Thanks to micro-power processors and sensors, micro-power sources have become an attractive option for industry and research. This work is interested in micro-power sources that harvest vibrational energy by deploying electrostatic, electromagnetic, and piezoelectric transduction techniques. The output power of vibrational energy harvesters is in AC form, whereas electronic loads require known DC power supply to operate. Thus, there is a need for AC-DC conversion between harvesters and electronic loads to get DC power out of AC. Traditional full-wave bridge rectifiers and center-tapped transformer rectifiers are not feasible in micro-watt-level harvesters. Low output power undermines the power efficiency of those traditional rectifiers. Thus, novel, low power, high efficiency conversion circuits are required instead of traditional rectifiers. This goal is particularly challenging when it comes to electromagnetic energy harvesters since their output voltage is much lower than that of electrostatic and piezoelectric harvesters. In this work, we studied four different full-wave rectifiers; a silicon diode bridge rectifier, a Schottky diode bridge rectifier, a passive MOSFET rectifier, an an active MOSFET rectifier. Out of simulation results, we found the voltage and power efficiency of each rectifier. We found that MOSFET-type rectifiers are better than diode type rectifiers in terms of voltage and power efficiency. Both full-wave MOSFET rectifiers have about 99% voltage and power efficiency. There is only a small difference in power and voltage efficiency between the two MOSFET rectifier types below 600mV input voltage amplitude. Since active MOSFET rectifier has extra components and need of external DC supply to power its active devices, we concluded it was not good option for small scale harvester systems. We implemented the passive MOSFET rectifier, tested its performance in rectifying the output of an electromagnetic harvester, and analyzed its effects on the harvester performance. When we connected the MOSFET rectifier to the harvester it doubled the optimum load resistance from 24 Ohm to 48 Ohm. We also studied the rectifier effect on harvester's natural frequency, and it does not change much the natural frequency which means our rectifier acts like resistance, and we also calculated the power efficiency based on harvester test and we have maximum 74% power efficiency.

The power density of a switching converter is dependent on the size of the power circuit components. Converters are operated in the hundreds of kHz to achieve high power density since the size of the converter reactive components decrease as frequency increases. Most present day low power (<200W) DC-DC converters operate at switching frequencies up to 500kHz. Some research has been conducted on converters that can operate above 500kHz up to 4MHz. In the near future, most DC-DC switching converters for communications and computers will operate at switching frequencies of 1-10MHz in order to achieve greater power density and improved transient response. To meet the next generation requirements of these applications, four new ideas are proposed in this thesis. The first contribution is a new current source gate drive circuit for power MOSFETs. The circuit provides a nearly constant gate current to reduce switching transition times and therefore switching loss in power MOSFETs. In addition, it can recover a portion of the gate energy normally dissipated in a conventional driver. Demonstrated loss reduction of 24.8% at 10V/5A load are presented in comparison to a conventional voltage source driver for a boost converter switching at 1MHz. The second contribution is a new high efficiency 1MHz synchronous buck voltage regulator using an improved current source driver. The proposed circuit achieves short rise and fall times to reduce switching loss in the buck HS MOSFET. It also recovers a portion of the SR gate energy, enabling a loss reduction of 24% at 1.3V/30A load in comparison to a conventional driver. In the third contribution, a new switching loss model is proposed for synchronous buck voltage regulators. The model uses simple closed form equations to calculate the rise and fall times and piecewise linear approximations of the HS MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss. The final contribution is a new variable frequency digital control method for resonant converters, which is suitable for future applications switching at 10MHz. The proposed method uses frequency dithering to reduce the clock frequency demands of the digital controller. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-02-28 10:56:06.732

Recent trend of minimization in microprocessors has introduced increasing self-heating effects in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-consistent 3D models of FinFET and MOSFET basic logic gates, and simulated steady-state thermal transport for the worst heating case scenario. Incorporating size-dependent effective thermal conductivity of thin films instead of bulk values, these simulations provide a more accurate prediction of temperature rise in the logic gates. Results of our simulations predict higher temperature rise in FinFETs, compared to MOSFETs. Existence of buried oxide layer and confined geometry of FinFET structure are determined to be the most contributing to this higher temperature rise. To connect the results of our simulations to higher scale simulations, we proposed an equivalent thermal conductivity for each basic logic gate. These values were tested and found to be independent of the magnitude of chosen boundary conditions, as well as heat generation rate.

Recent trend of minimization in microprocessors has introduced increasing self-heating effects in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-consistent 3D models of FinFET and MOSFET basic logic gates, and simulated steady-state thermal transport for the worst heating case scenario. Incorporating size-dependent effective thermal conductivity of thin films instead of bulk values, these simulations provide a more accurate prediction of temperature rise in the logic gates. Results of our simulations predict higher temperature rise in FinFETs, compared to MOSFETs. Existence of buried oxide layer and confined geometry of FinFET structure are determined to be the most contributing to this higher temperature rise. To connect the results of our simulations to higher scale simulations, we proposed an equivalent thermal conductivity for each basic logic gate. These values were tested and found to be independent of the magnitude of chosen boundary conditions, as well as heat generation rate.

<p>Patients undergoing cardiac catheterization are potentially at risk of radiation-induced health effects from the interventional fluoroscopic X-ray imaging used throughout the clinical procedure. The amount of radiation exposure is highly dependent on the complexity of the procedure and the level of optimization in imaging parameters applied by the clinician. For cardiac catheterization, patient radiation dosimetry, for key organs as well as whole-body effective, is challenging due to the lack of fixed imaging protocols, unlike other common X-ray based imaging modalities. </p><p>Pediatric patients are at a greater risk compared to adults due to their greater cellular radio-sensitivities as well as longer remaining life-expectancy following the radiation exposure. In terms of radiation dosimetry, they are often more challenging due to greater variation in body size, which often triggers a wider range of imaging parameters in modern imaging systems with automatic dose rate modulation. </p><p>The overall objective of this dissertation was to develop a comprehensive method of radiation dose estimation for pediatric patients undergoing cardiac catheterization. In this dissertation, the research is divided into two main parts: the Physics Component and the Clinical Component. A proof-of-principle study focused on two patient age groups (Newborn and Five-year-old), one popular biplane imaging system, and the clinical practice of two pediatric cardiologists at one large academic medical center. </p><p>The Physics Component includes experiments relevant to the physical measurement of patient organ dose using high-sensitivity MOSFET dosimeters placed in anthropomorphic pediatric phantoms. </p><p>First, the three-dimensional angular dependence of MOSFET detectors in scatter medium under fluoroscopic irradiation was characterized. A custom-made spherical scatter phantom was used to measure response variations in three-dimensional angular orientations. The results were to be used as angular dependence correction factors for the MOSFET organ dose measurements in the following studies. Minor angular dependence (< ±20% at all angles tested, < ±10% at clinically relevant angles in cardiac catheterization) was observed.</p><p>Second, the cardiac dose for common fluoroscopic imaging techniques for pediatric patients in the two age groups was measured. Imaging technique settings with variations of individual key imaging parameters were tested to observe the quantitative effect of imaging optimization or lack thereof. Along with each measurement, the two standard system output indices, the Air Kerma (AK) and Dose-Area Product (DAP), were also recorded and compared to the measured cardiac and skin doses – the lack of correlation between the indices and the organ doses shed light to the substantial limitation of the indices in representing patient radiation dose, at least within the scope of this dissertation.</p><p>Third, the effective dose (ED) for Posterior-Anterior and Lateral fluoroscopic imaging techniques for pediatric patients in the two age groups was determined. In addition, the dosimetric effect of removing the anti-scatter grid was studied, for which a factor-of-two ED rate reduction was observed for the imaging techniques. </p><p>The Clinical Component involved analytical research to develop a validated retrospective cardiac dose reconstruction formulation and to propose the new Optimization Index which evaluates the level of optimization of the clinician’s imaging usage during a procedure; and small sample group of actual procedures were used to demonstrate applicability of these formulations.</p><p>In its entirety, the research represents a first-of-its-kind comprehensive approach in radiation dosimetry for pediatric cardiac catheterization; and separately, it is also modular enough that each individual section can serve as study templates for small-scale dosimetric studies of similar purposes. The data collected and algorithmic formulations developed can be of use in areas of personalized patient dosimetry, clinician training, image quality studies and radiation-associated health effect research.</p> / Dissertation

This thesis presents novel battery pack designs and control methods to be used with battery packs enhanced with power electronics. There are two areas of focus: 1) intelligent battery packs that are constructed out of many hot swappable modules and 2) smart cells that form the foundation of a completely decentralised battery management system (BMS). In both areas, the concept of active loading/charging is introduced. Active loading/charging balances the cells in a battery pack by loading each cell in proportion to its capacity. In this way, the state of charge of all cells in a series string remain synchronized at all times and all of the energy storage potential from every cell is utilized, despite any differences in capacity there may be. Experimental results from the intelligent battery show how the capacity of a pack of variably degraded cells can be increased by 46% from 97 Wh to 142 Wh using active loading/charging. Engineering design challenges of building a practical intelligent battery pack are addressed. Start up and shut down procedures, and their respective circuits, were carefully designed to ensure zero current draw from the battery cells in the off state, yet also provide a simple mechanism for turning on. Intra-pack communication was designed to provide adequate information flow and precise control. Thus, two intra-pack networks were designed: a real time communication network, and a data communication network. The decentralised control algorithms of the smart cell use a small filtering inductor as a multi-purpose sensor. By analysing the voltage across this filtering inductor, the switching actions of a string of smart cells can be optimised. Experimental results show that the optimised switching actions reduce the output voltage ripple by 83% and they synchronize the terminal voltages of the smart cells, and by extension, their states of charge. This forms the basis of a decentralised BMS that does not require any communication between cells or with a centralised controller, but can still achieve cell balancing through active loading/charging.

A l’heure où la miniaturisation des technologies CMOS sur substrat massif atteint des limites, la technologie FDSOI (silicium sur isolant totalement déserté) s’impose comme une alternative pour l’industrie en raison de ses meilleures performances. Dans cette technologie, l’utilisation d’un substrat SOI ultramince améliore le comportement des transistors MOSFETs et garantit leur intégrité électrostatique pour des dimensions en deçà de 28nm. Afin de lui intégrer de nouvelles fonctionnalités, il devient nécessaire de développer des applications dites « haute tension » comme les convertisseurs DC/DC, les régulateurs de tension ou encore les amplificateurs de puissance. Cependant les composants standards de la technologie CMOS ne sont pas capables de fonctionner sous les hautes tensions requises. Pour répondre à cette limitation, ces travaux portent sur le développement et l’étude de transistors MOS haute tension en technologie FDSOI. Plusieurs solutions sont étudiées à l’aide de simulations numériques et de caractérisations électriques : l’hybridation du substrat (gravure localisée de l’oxyde enterré) et la transposition sur le film mince. Une architecture innovante sur SOI, le Dual Gound Plane EDMOS, est alors proposée, caractérisée et modélisée. Cette architecture repose sur la polarisation d’une seconde grille arrière pour offrir un compromis RON.S/BV prometteur pour les applications visées. / Nowadays the scaling of bulk silicon CMOS technologies is reaching physical limits. In this context, the FDSOI technology (fully depleted silicon-on-insulator) becomes an alternative for the industry because of its superior performances. The use of an ultra-thin SOI substrate provides an improvement of the MOSFETs behaviour and guarantees their electrostatic integrity for devices of 28nm and below. The development of high-voltage applications such DC/DC converters, voltage regulators and power amplifiers become necessary to integrate new functionalities in the technology. However, the standard devices are not designed to handle such high voltages. To overcome this limitation, this work is focused on the design of a high voltage MOSFET in FDSOI. Through simulations and electrical characterizations, we are exploring several solutions such as the hybridization of the SOI substrate (local opening of the buried oxide) or the implementation in the silicon film. An innovative architecture on SOI, the Dual Ground Plane EDMOS, is proposed, characterized and modelled. It relies on the biasing of a dedicated ground plane introduced below the device to offer promising RON.S/BV trade-off for the targeted applications.

A miniaturização de dispositivos tecnológicos levou à percepção de novas classes de efeitos devidos ao con namento quântico e à mudança na proporção entre número de átomos presentes na superfície e no volume de estruturas que atingem a escala nanométrica, levando à noção de nanociência e nanotecnologia. Dentre os desa os impostos por essas áreas emergentes encontram-se os desa os para os métodos analíticos, em particular para os métodos baseados em feixes de íons, que tiveram um papel fundamental na tecnologia do silício. O uso de feixes de íons para a caracterização de nanoestruturas não é muito difundido devido a limitações na resolução espacial e no dano causado pelos íons energéticos incidentes nas nanoestruturas. Nesta tese é apresentado o estado da arte das aplicações da análise por feixes de íons na nanotecnologia e são descritos avanços direcionados à adoção de métodos analíticos de feixes de íons para as nanociências. Serão abordados os principais métodos de per lometria com alta resolução em profundidade, em especí co a per lometria utilizando reações nucleares com ressonâncias estreitas em suas curvas de seção de choque (RNRA, do inglês Resonant Nuclear Reaction Analysis ) e espalhamento de íons de energias intermediárias (MEIS do inglês Medium Energy Ion Scattering ). Uma vez que os modelos convencionais, baseados em uma aproximação Gaussiana, não são adequados para descrever o espectro de espalhamento de íons correspondente a estruturas nanométricas, neste trabalho foram desenvolvidos modelos que descrevem adequadamente os processos de perda de energia dos íons na matéria, viabilizando a adoção sistemática de espalhamento de íons de energias intermediárias para a análise de nanoestruturas. Aplica ções recentes de RNRA e MEIS para eletrodos de porta metálicos e dielétricos com alta constante dielétrica sendo incorporados à tecnologia MOSFET atual são apresentadas como avaliação dos métodos. / Device miniaturization revealed a new class of e ects due to quantum con nement and a di erent ration between the number of surface and bulk atoms as compared to macroscopic structures, giving rise to nanoscience and nanotechnology. Among the challenges imposed by these emerging areas are those related to the analytical techniques for material science, especially for ion beam analysis techniques (IBA). These techniques played a key role in the development of silicon technology. However, ion beam analysis is not of widespread use for nanostructure characterization due to limitation on the spatial resolution and also the damage caused by the energetic impinging ions at the target nanostructures. This thesis present state of the art applications of ion beam analysis for nanotechnology, describing advanced aimed at a more systematic use of analytical techniques based on ion beams for nanosciences. Detailed description of resonant nuclear reaction analysis (RNRA) medium energy ion scattering (MEIS) are presented, followed by the development of advanced ion energy loss models for high resolution depth pro ling using MEIS. The evaluation of RNRA e MEIS are presented based on recent applications for metal gates and high-k gate dielectrics of latest generation Metal-Oxide-Semiconductor Field-E ect Transistor (MOSFET) devices.

Frente à crescente necessidade de que novas tecnologias sejam capazes de operar com confiabilidade em ambientes hostis, a análise dos efeitos da radiação ionizante em dispositivos semicondutores se tornou um ramo de pesquisa em contínua ascensão, contribuindo para o desenvolvimento de tecnologias estratégicas e promovendo o aprimoramento científico e o desenvolvimento tecnológico da humanidade. Por outro lado, a atual tecnologia CMOS de fabricação de circuitos integrados apresenta sinais de limitação, em grande parte, devido às características físicas inerentes ao seu princípio de funcionamento, sendo necessário, portanto, que dispositivos com novos mecanismos de operação e geometrias sejam desenvolvidos. Dentre eles, transistores de tunelamento induzido por efeito de campo (TFET) se destacam por apresentarem menor corrente de dreno quando desligados e a possibilidade de se atingir inclinações de sublimiar abaixo do limite teórico estabelecido por dispositivos MOSFET de 60 mV/déc à temperatura ambiente, permitindo-se a redução da tensão de alimentação dos transistores para cerca de 0,5 V. Buscando contribuir com as necessidades destas duas áreas de pesquisa, neste projeto de mestrado, foi analisado o comportamento de TFETs de silício com porta tripla, fabricados sobre lâmina SOI (silício sobre isolante), submetidos a até 10 Mrad(Si) de dose acumulada total enquanto não polarizados, gerada por uma fonte de prótons de 600 keV de energia. Em uma análise inicial, após exposição de dispositivos de 1 µm de largura de aleta a uma dose de 1 Mrad(Si), foi possível observar uma redução no nível corrente de dreno de estado ligado do dispositivo (ION ? 300 pA) de até 10%, não associada à uma alteração da corrente de porta. Além disso, o efeito da radiação nesses transistores reduz de 10% para 2% quando se aumenta o comprimento do canal de 150 nm para 1 µm. As razões para ambos os fenômenos foram discutidas com base na competição entre os efeitos de divisão da corrente de dreno na primeira e segunda interfaces e do aumento da resistência de canal em dispositivos mais longos. Para uma análise em função da dose acumulada total, dispositivos SOI TFET e SOI MOSFET, ambos de porta tripla, foram caracterizados eletricamente 14 dias após cada etapa de irradiação. De maneira geral, dispositivos de ambas as tecnologias, com largura de aleta igual a 40 nm, apresentaram baixa susceptibilidade aos efeitos cumulativos da radiação ionizante. No entanto, quando considerados dispositivos com largura de aleta muito maior que a altura da aleta (WFIN = 1 µm), nos quais a influência das portas laterais sobre o acoplamento eletrostático do canal é praticamente inexistente, transistores túnel-FET se destacaram positivamente. Esses dispositivos se mostraram resistentes aos efeitos de dose ionizante total (TID) mesmo para doses de 5 Mrad(Si), enquanto os transistores SOI MOSFET apresentaram uma variação gradual de seus parâmetros a cada dose acumulada. Um exemplo disso é a variação observada na inclinação de sublimiar, de 32,5% nos transistores SOI MOSFET e 5,6% nos transistores SOI TFET. Somente após 10 Mrad(Si) de irradiação por prótons é que os TFETs de aleta larga apresentaram variações mais significativas em sua curva de transferência (ID x VG). Tanto para a configuração como tipo P quanto para a configuração como tipo N, notou-se um deslocamento de até 80 mV da curva de transferência do dispositivo para a esquerda, provocado, segundo análise via simulações, pelas cargas fixas positivas geradas pela irradiação no óxido enterrado do dispositivo. Adicionalmente, foi possível observar um aumento da corrente de tunelamento assistido por armadilhas (TAT) nesses dispositivos, provocada pelo aumento da densidade de estados de interface causada também pelos efeitos de TID. O aumento de TAT foi reconhecido como o principal responsável pela degradação de 23,3% da inclinação de sublimiar dos TFETs, com WFIN igual 1 µm, após 10 Mrad(Si). Apesar das mudanças observadas, foi possível se sugerir, através da comparação com transistores SOI MOSFET de dimensões equivalentes, que transistores de tunelamento induzido por efeito de campo podem, futuramente, se tornar referência no quesito imunidade aos efeitos de dose ionizante total. / In light of the increasing need for new technologies to be able to operate reliably in harsh environments, the analysis of the effects of ionizing radiation on semiconductor devices has become a continually rising field of research, contributing to the development of strategic technologies and promoting scientific improvement and technological development of humankind. On the other hand, the current CMOS technology for the manufacture of integrated circuits shows signs of limitation, mostly, due to the physical characteristics inherent to its operating principle, thus, it is necessary that devices with new operating mechanisms and geometries be developed. Among them, tunnel field-effect transistors (TFET) stand out because of its lower OFF state current and the possibility of reaching subthreshold swing below the theoretical limit established by MOSFET devices of 60 mV/dec at room temperature, allowing to reduce transistors supply voltage to about 0.5 V. In order to contribute with both areas, the behavior of silicon based triple gate TFETs fabricated on a SOI (silicon-on-insulator) substrate and exposed to a total cumulative dose of 10 Mrad (Si) (while not biased) generated by a 600 keV proton beam was analyzed. In an initial analysis after exposure of 1 µm width devices to 1 Mrad(Si), it was possible to observe an ON state current reduction (ION ? 300 pA) up to 10%, not associated to a gate current change. Beyond that, irradiation effects on these devices reduce from 10% to 2% with the channel length increasing from 150 nm to 1 µm. The reasons behind these phenomena were discussed based on the competition between a high channel resistance present in longer devices and the TFET drain current reduction due to the irradiation. For a total cumulative dose analysis, triple gate SOI TFET and triple gate SOI MOSFET devices were characterized 14 days after each irradiation phase. In general, devices of both technologies, with 40 nm fin width, presented low susceptibility to the cumulative effects of ionizing radiation. However, for devices with fin width larger than fin height (WFIN = 1 µm) in which the influence of side gates on the electrostatic coupling of the channel is weak, tunnel-FET transistors have stood out. These devices were resistant to the effects of total ionizing dose (TID) even for doses as high as 5 Mrad(Si), while SOI MOSFET transistors showed a gradual variation of their parameters at each accumulated dose. The variation observed for the subthreshold swing, for example, was about 32.5% for SOI MOSFET devices and 5.6% for SOI TFET devices. TFETs with wider fin have shown significant variations on its transfer characteristic (ID x VG) only after 10 Mrad(Si) of proton irradiation. For both P-type and N-type configurations, it was observed a shift of the transfer curve to the left up to 80 mV caused by, according to simulations, the positive fixed charges generated in the buried oxide by irradiation. In addition, it was possible to observe a trap assisted tunneling (TAT) current increase caused by interface states promoted by TID effects. The increase of TAT was recognized as the main responsible for the degradation of 23.3% of the subthreshold swing of the TFETs after 10 Mrad(Si). In spite of the observed changes, it was possible to suggest, through comparison with SOI MOSFET devices of equivalent dimensions, which tunnel field-effect transistors may become a reference when considering immunity against total ionizing dose effects.