PMOS and NMOS mobility characteristics of the dual channel (strained Si/strained Ge) heterostructure have been reviewed. It is shown that the dual channel heterostructure can provide substantially enhanced mobilities for both electrons and holes. However, germanium interdiffusion from the germanium rich buried layer into the underlying buffer layer could potentially reduce the hole mobility enhancements. / Singapore-MIT Alliance (SMA)

Dans le contexte actuel d'optimisation des performances des dispositifs de microélectronique, le transistor MOSFET, brique de base, est soumis à des contraintes géométriques telles que son architecture même est remise en cause. L'augmentation du nombre de grille afin d'accentuer le contrôle électrostatique de la grille sur le canal a mis en avant des architectures ultimes telles que le nanofil dont la grille enrobe totalement le canal. Dans ce travail, une étude du nanofil de silicium a été réalisée afin d'estimer les potentialités de cette architecture au niveau transistor jusqu'à l'étude de petits circuits. Pour cela, un modèle analytique en courant a été mis en place et implémenté en Verilog-A afin de simuler des petits circuits dans un environnement de type ELDO. Toutefois, les paramètres du modèle telles que les masses effectives de transport (ou de confinement) ou le transport dans le film sont la clé de la prédictibilité au niveau circuit. C'est pourquoi des simulations avancées de type liaisons fortes ou Kubo-Greenwood ont été développées afin d'étudier finement l'évolution des caractéristiques du nanofil notamment vis-à-vis de son intégration géométriques. Issues de ces approches numériques, des expressions analytiques ont été établies afin d'inclure dans le modèle toute la physique observée en amont. Des effets comme l'évolution de la structure de bande ou l'impact des mécanismes d'interaction ont ainsi pu être apportés jusqu'au niveau circuit. Les résultats en courant acquièrent une certaine pertinence en créant un lien entre simulations numériques et données expérimentales.

Today, micro- and nano-electronic devices are becoming more complex and advanced as the dimensions are shrinking. It is therefore a very challenging task to develop new device technologies with performance that can be predicted. This thesis focuses on advanced measurement techniques and TCAD simulations in order to characterize and understand the device physics of advanced semiconductor devices. TCAD simulations were made on a novel MOSFET device with asymmetric source and drain structures. The results showed that there exists an optimum range of implantation doses where the device has a significantly higher figure-of-merit regarding speed and voltage capability, compared to a symmetric MOSFET. Furthermore, both 2D and 3D simulations were used to develop a resistive model of the substrate noise coupling. Of particular interest to this thesis is the random dopant fluctuation (RDF). The result of RDF can be characterized using very advance and reliable measurement techniques. In the thesis an ultra-high precision parametric mismatch measurement system was designed and implemented. The best ever reported performance on short-term repeatability of the measurements was demonstrated. A new bipolar parametric mismatch phenomenon was also revealed using the measurement system. A complete simulation platform, called SiSPET (Simulated Statistical Parameter Extraction Tool), was developed and integrated into the framework of a commercial TCAD environment. A special program for randomization of the doping was developed and proven to provide RDF effects in agreement measurement. The SiSPET system was used to investigate how different device models were able to take RDF effects into account. The RDF effects were translated in to parameter fluctuations using the developed extraction routines. It was shown that the basic MOSFET fluctuation model could be improved by including the field dependenent mobility. However, if a precise description of the fluctuations is required an advanced compact-model, such as MOS Model 11 should be used.

In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models. Although 3D device simulation can be used to extract such parasitics, it is expensive and does not consider the effects of nearby interconnect and devices in a layout. Conventional rule-based layout parasitic extraction (LPE) tools which are used for interconnect extraction are inaccurate in modeling 3D effects near devices. In this thesis, we propose a methodology which combines 3D field solver based extraction with the ability to exclude specific parasitics from among the parameters in the SPICE model. We use this methodology to extract parasitics due to fringing fields and sidewall capacitances in MOSFETs, bipolar transistors and FinFETs in advanced process nodes. We analyze the importance of considering layout and process variables in device extraction by comparing with standard SPICE models. The results are validated by circuit simulation using predictive technology models and test chips. We also demonstrate the versatility of this flow by modeling the capacitance contributions of the raised gate profile in nanoscale FinFETs.

Today, the silicon technology is well established for RF-applications (f~1-100 GHz), with emphasis on the lower frequencies (f < 5 GHz). The field of RF power devices is extensive concerning materials and devices. One of the important RF-devices is the silicon LDMOS transistor. A large extent of the research presented in the thesis concerns studies of this device, which have resulted in increased understanding of the device behavior and improved performance. The thesis starts with a brief survey of the RF-field, including the LDMOS transistor, followed by a description of the methods used in the investigations; simulations, modeling and measurements. Specific results presented in the appended papers are also briefly summarized. A new concept for LDMOS transistors, which allows for both high frequency and high voltage operation, has been developed and characterized. World-record performance in terms of output power density was obtained: over 1 W/mm at 50 V and 3.2 GHz. Further understanding and improvements of the device are achieved using simulations and modeling. For determination of model parameters a new general parameter extraction technique was developed. The method has been successfully used for a large variety of high-frequency devices, and has been frequently used in the modeling work in this thesis. Important properties of RF-power devices are the device linearity and power efficiency. Extensive studies regarding the efficiency were conducted using numerical simulations and modeling of the off-state output resistance, which is correlated to the efficiency. The results show that significant improvements can be obtained for devices on both bulk- and SOI-substrates, using thin high-resistivity substrates and very low-resistivity SOI-substrates, respectively. Finally a new approach to drastically reduce substrate crosstalk by using very low-resistivity SOI substrate is proposed. Experimentally, a reduction of 20-40 dB was demonstrated in the GHz range compared to high-resistivity SOI substrate.

This thesis investigates the reactive formation of Ni mono-gernanosilicide, NiSi1-uGeu, for contact metallization of future CMOS devices where Si1-xGex can be present in the gate, source and drain of a MOSFET. Although the investigation has been pursued with a strong focus on materials aspects, issues related to process integration in MOSFETs both on conventional bulk Si and ultra-thin body SOI have been taken into consideration. The thesis work has taken a balance between experimental studies and theoretical calculations. The interaction between Ni films and Si1-xGex substrates, polycrystalline (poly) as in the gate or single-crystal (sc) as in the source/drain, leads to the formation of a ternary solid solution NiSi1-uGeu with the MnP structure in a wide range of temperature from 450 to 850oC. A linear variation of the lattice parameters of the NiSi1-uGeu with u is determined. A number of key observations are made: (1) the agglomeration of NiSi1-uGeu on Si1-xGex at a lower temperature compared to that of NiSi on Si, (2) the absence of NiSi2 up to 850 oC when Ge is present, and (3) a substantial Ge out-diffusion from the NiSi1-xGex and a precipitation of Ge-richer SiGe around the NiSi1-uGeu grains. These observations are interpreted referring to the ternary phase diagram for the Ni-Si-Ge system presented in this work. Possible factors influencing the morphological stability of NiSi1-uGeu films on Si1-xGex are discussed: (1) mechanical strain in the epitaxial Si1-xGex, (2) the favorable formation of NiSi at the expense of NiGe, (3) grain growth in poly-Si1-xGex, and (4) grain grooving in NiSi1-uGeu on sc-Si1-xGex. Energetically, the former two factors have been found to play a comparable, yet major role in the morphological instability of NiSi1-uGeu. The inter-diffusion of Si and Ge in NiSi1-uGeu and Si1-xGex provides the kinetic pathway for the morphological evolution. On Si1-xGex epitaxially grown on Si(100), a strong preferential orientation of the resulting NiSi1-uGeu film is found; NiSi films formed on Si show no specific film texturing. Furthermore, layer sequence and layer thickness of Si/SiGe or SiGe/Si are found to strongly affect the film texture in the resulting NiSi1-uGeu. Epitaxy of NiSi on NiSi1-uGeu, and vice versa, occurs across the compositional boundary, which confirms Ni as the dominant diffusion species during germanosilicide formation. The presence of Ge reduces the contact resistivity for NiSi1-uGeu on p-tyep Si1-xGex, as expected. For poly-Si1-xGex doped by B to 1020cm-3, a contact resistivity of 9x10-8 Ωcm2, 5 times lower than for the corresponding NiSi/Si contact, is obtained. On n-type Si1-xGex doped by As to 1020 cm-3, the opposite is true regarding the effect of Ge and a contact resistivity of 2x10-5 Ωcm2, 20 times higher than for the corresponding NiSi/Si contact, is obtained. When formed in the source/drain regions of a MOSFET fabricated on ultra-thin body SOI, a severe lateral growth of NiSi and Ni2Si into the channel region is revealed if the initial Ni thickness is too thick and if the silicidation conditions are not carefully controlled. This leads to a Schottky contact S/D MOSFET due to the consumption of the entire source/drain. In order to realize a low source/drain resistance for MOSFETs on ultra-thin SOI, satisfying the Roadmap recommendation for the 45-nm technology node, simplified calculations have been performed and an elevated source/drain structure is clearly shown to be advantageous. / QC 20101005

A novel MOSFET gas sensor for the investigation has been developed. Its configuration resembles a"normally on"n-type thin-film transistor (TFT) with a gas sensitive metal oxide as a channel. The device used in the experiments only differs from common TFTs in the gate configuration. In order to allow gas reactions with the SnO2-surface, the gate is buried under the semiconducting layer. Without any gate voltage, the device works as a conventional metal oxide gas sensor. Applied gate voltages affect the channel carrier concentration and surface potential of the metal oxide, thus causing a change in sensitivity. The results of the gas measurements are in accordance with the electric adsorption effect, which was postulated by Fedor Wolkenstein 1957, and arises the possibility to operate a semiconductor gas sensor at relatively low temperatures and, thereby, be able to integrate CMOS electronics for processing of measurements at the same chip.

A new generation of electronic devices has emerged requiring micro-watt-level power supply to operate. Thanks to micro-power processors and sensors, micro-power sources have become an attractive option for industry and research. This work is interested in micro-power sources that harvest vibrational energy by deploying electrostatic, electromagnetic, and piezoelectric transduction techniques. The output power of vibrational energy harvesters is in AC form, whereas electronic loads require known DC power supply to operate. Thus, there is a need for AC-DC conversion between harvesters and electronic loads to get DC power out of AC. Traditional full-wave bridge rectifiers and center-tapped transformer rectifiers are not feasible in micro-watt-level harvesters. Low output power undermines the power efficiency of those traditional rectifiers. Thus, novel, low power, high efficiency conversion circuits are required instead of traditional rectifiers. This goal is particularly challenging when it comes to electromagnetic energy harvesters since their output voltage is much lower than that of electrostatic and piezoelectric harvesters. In this work, we studied four different full-wave rectifiers; a silicon diode bridge rectifier, a Schottky diode bridge rectifier, a passive MOSFET rectifier, an an active MOSFET rectifier. Out of simulation results, we found the voltage and power efficiency of each rectifier. We found that MOSFET-type rectifiers are better than diode type rectifiers in terms of voltage and power efficiency. Both full-wave MOSFET rectifiers have about 99% voltage and power efficiency. There is only a small difference in power and voltage efficiency between the two MOSFET rectifier types below 600mV input voltage amplitude. Since active MOSFET rectifier has extra components and need of external DC supply to power its active devices, we concluded it was not good option for small scale harvester systems. We implemented the passive MOSFET rectifier, tested its performance in rectifying the output of an electromagnetic harvester, and analyzed its effects on the harvester performance. When we connected the MOSFET rectifier to the harvester it doubled the optimum load resistance from 24 Ohm to 48 Ohm. We also studied the rectifier effect on harvester's natural frequency, and it does not change much the natural frequency which means our rectifier acts like resistance, and we also calculated the power efficiency based on harvester test and we have maximum 74% power efficiency.

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.

A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to replace the conventional PMOSFET for solving the problem of width compensation. Also, we carefully investigate and analyze the non-conventional CMOS characteristics with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load. According to the results, our proposed novel CMOS inverter has correct logic behavior and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL CMOS. In addition, because of the N-type output drain node and the SOI structure, our proposed CMOS does not need any physical isolation technique, thereby improving the packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1 % reduction in the total area when compared with the SOI-based CMOS. More importantly, due to the reduced process steps, the cost reduction can be achieved. We therefore believe that a high packing density novel CMOS inverter with reduced process steps can become one of the contenders for future CMOS scaling.