No description available.

在統計學上我們經常會遭遇到如下的問題： minimze subject to 其中 和Ｃ都是已知。 上述非線性規劃（NONLINEAR PROGRAMING）問題的最佳解，是相當複雜的，以致於我 們無法用簡單的式子，將其解明確的表示出來。 RAO-GHANGURDE （１９７２）在“從有限母體抽樣的貝氏最佳解”這一篇文章中，對 這種非線性規劃問題，提出一個反覆演算的解法，來解決這類問題，由於，我們無法 看出其演算法的立論根據何在，收斂結果的精確性有多高，於是，本文在ｋ＝２及ｋ ＝３的情形下，由直覺的幾何觀點，提出了另一個求最佳解的方法，來驗證RAO-GHAN GURED 反覆演算法的類確性。 最後，本論文將上述非線性規劃問題的解法，應用到下面兩個例子上： （ａ）在 COCHRAN的“抽樣技巧”（ SAMPLING TECHNIQUES）這一本書裡，有關雙重 抽樣（DOUBLE SAMPLING ）的理論中，也遭遇到要解決這一類問題，但由他的公式， 所計算出來的解，並不一定會萬足所需要的限制條件。 （ｂ）在SMITH-SEDRASK （１９８２）的“推估魚群年齡成份的貝氏最佳解“和JINN -SMITH-SEDRASK（１９８７）的“推估魚群年齡成份的貝氏最佳雙重抽樣”這兩篇的 文章中，同樣的也遭遇到這一類的問題。

Les technologies CMOS représentent aujourd’hui plus de 90% du marché des capteurs d’images : elles permettent d’intégrer des systèmes intelligents dans une seule puce (SoC = System-On-Chip) et ouvrent la voie à l’intégration d’algorithmes de plus en plus complexes dans les dernières générations de capteurs. Des techniques telles que la reconstruction grande dynamique nécessitent d’acquérir plusieurs images avec un même capteur et de les recombiner. Ces nouvelles contraintes nécessitent d’augmenter drastiquement le débit d’images pour des capteurs de tailles conséquentes (Jusqu'à 30 Mpixels), ainsi que d’augmenter la résolution du convertisseur analogique numérique (jusqu’à 14 bits). Cela crée une demande forte en techniques de conversion analogique-numérique. Ces techniques doivent obéir en même temps aux contraintes de performance notamment la vitesse, la résolution, le faible bruit, la faible consommation et l'intégrabilité mais aussi aux contraintes de qualité d'image impactées directement par la chaine de conversion analogique-numérique en plus de la technologie du pixel. D'ici découle une double problématique pour le sujet:- Etudier et déterminer les limites atteignables en termes de performance sur les différents axes précités.- Gestion du fonctionnement massivement parallèle lié à la structure inhérente des capteurs d'image en vue d'avoir une qualité d'image irréprochable. / CMOS technologies represent nowadays more than 90% of image sensors market given their features namely the possibility of integrating entire intelligent systems on the same chip (SoC = System-On-Chip). Thereby, allowing the implementation of more and more complex algorithms in the new generations of image sensors.New techniques have emerged like high dynamic range reconstruction which requires the acquisition of several images to build up one, thus multiplying the frame rate.These new constraints require a drastic increase of image rate for sensors ofconsiderable size (Up to 30 Mpix and more). At the same time, the ADCresolution has to be increased to be able to extract more details (until 14 bits).With all these demanding specifications, analog-to-digital conversion capabilities have to be boosted as far as possible.These capabilities can be distinguished into two main research axes representing the pillars of the PhD work, namely:+ The study of the reachable limits in terms of performance: Speed, Resolution,Low Noise, Low power consumption and small design pitch.+ The management of the highly parallel operation linked to the structure of animage sensor. Solutions have to be found so as to avoid image artefacts andpreserve the image quality.

[pt] Nesta tese é proposta a incorporação da estratégia de amostragem dupla, já utilizada em inspeção de lotes, ao gráfico de controle de np (número de defeituosos), com o objetivo de aumentar a sua eficiência, ou seja, reduzir o número médio de amostras até a detecção de um descontrole (NMA1), sem aumentar o tamanho médio de amostra (TMA) nem reduzir o número médio de amostras até um alarme falso (NMA0). Alternativamente, este esquema pode ser usado para reduzir o custo de amostragem do gráfico de np, uma vez que para obter o mesmo NMA1 que um gráfico de np com amostragem simples, o gráfico com amostragem dupla requererá menor tamanho médio de amostra. Para vários valores de p0 (fração defeituosa do processo em controle) e p1 (fração defeituosa do processo fora de controle), foi obtido o projeto ótimo do gráfico, ou seja, aquele que minimiza NMA1, tendo como restrições um valor máximo para TMA e valor mínimo para NMA0. O projeto ótimo foi obtido para vários valores dessas restrições. O projeto consiste na definição dos dois tamanhos de amostra, para o primeiro e o segundo estágios, e de um conjunto de limites para o gráfico. Para cada projeto ótimo foi também calculado o valor de NMA1 para uma faixa de valores de p1, além daquele para o qual o projeto foi otimizado. Foi feita uma comparação de desempenho entre o esquema desenvolvido e outros esquemas de monitoramento do número de defeituosos na amostra: o clássico gráfico de np (com amostragem simples), o esquema CuSum, o gráfico de controle de EWMA e o gráfico np VSS (gráfico adaptativo, com tamanho de amostra variável). Para a comparação, foram obtidos os projetos ótimos de cada um desses esquemas, sob as mesmas restrições e para os mesmos valores de p0 e p1. Assim, uma contribuição adicional dessa tese é a análise e otimização do desempenho dos esquemas CuSum, EWMA e VSS para np. O resultado final foi a indicação de qual é o esquema de controle de processo mais eficiente para cada situação. O gráfico de np com amostragem dupla aqui proposto e desenvolvido mostrou ser em geral o esquema mais eficiente para a detecção de aumentos grandes e moderados na fração defeituosa do processo, perdendo apenas para o gráfico VSS, nos casos em que p0, o tamanho (médio) de amostra e o aumento em p0 (razão p1/p0) são todos pequenos. / [en] In this thesis, it is proposed the incorporation of the double-sampling strategy, used in lot inspection, to the np control chart (control chart for the number nonconforming), with the purpose of improving its efficiency, that is, reducing the out-of-control average run length (ARL1), without increasing the average sample size (ASS) or the in-control average run length (ARL0). Alternatively, this scheme can be used to reduce the np chart sampling costs, since that in order to get the same ARL1 of the single-sampling np chart, the doublesampling chart will require smaller average sample size. For a number of values of p0 (in-control defective rate of the process) and p1 (out-of-control defective rate of the process), the optimal chart designs were obtained, namely the designs that minimize ARL1, subject to maximum ASS and minimum ARL0 constraints. Optimal designs were obtained for several values of these constraints. The design consists of two sample sizes, for the first and second stages, and a set of limits for the chart. For each optimal design the value of ARL1 was also computed for a range of p1 values besides the one for which the design ARL1 was minimized. A performance comparison was carried out between the proposed scheme and the classical (single-sampling) np chart, the CuSum np scheme, the EWMA np control chart and the VSS np chart (the variable sample size control chart). For comparison, optimal designs for each scheme were considered, under same constraints and values of p0 and p1. An additional contribution of this thesis is the performance analysis and optimization of the np CuSum, EWMA and VSS schemes. The final result is the indication of the most efficient process control scheme for each situation. The double-sampling np control chart here proposed and developed has proved to be in general the most efficient scheme for the detection of large and moderate increases in the process fraction defective, being only surpassed by the VSS chart in the cases in which p0, the (average) sample size and the increase in p0 (p1/p0 ratio) are all small.

This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.

<p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p>

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.