The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing. The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible. The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.

In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers. The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.

The trend toward higher-level circuit integration is the result of demand for lower cost and smaller feature size. The goal of this trend is to have a single-chip solution, in which analog and digital circuits are placed on the same die with advanced CMOS technology. The complete integration of a system may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. Although advanced fabrication technology benefits digital circuits, it poses great challenges for analog circuits. For instance, the scaling of CMOS devices degrades important analog performance such as output resistance, lowering amplifier gain. Simply lowering the power supply voltage in analog circuits does not necessarily result in lower power dissipation. The many design constraints common to the design of analog circuits makes it difficult to curb their power consumption. This is especially true for already complicated analog systems like ADCs; reducing their appetite for power requires careful analysis of system requirements and special strategies. This thesis describes a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers and so on. The ADC is designed in a 90nm CMOS technology with a 1.2V supply voltage.

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.

The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.

This thesis is composed of three independent parts, which are respectively focused on three different applications. 1. A Circuit Design of Fast Bipolar Inner Product Processor for Neural Associative Memory Networks¡G A novel and high-speed realization of the bipolar-valued inner product processor for associative memory networks is presented. The proposed design is verified to speed up the inner product computation compared with prior works. 2. An Area-Saving 8-bit A/D Converter Using A Binary Search Scheme¡G A fast and area-saving analog-to-digital converter using DFFs and a digital-to-analog converter is proposed. This design provides a reasonably fast solution for the embedded ADC with the area penalty growing linearly with the data length. 3. A Smart Battery Monitor Emulator System¡G An efficient smart battery monitor emulator system is designed by using the bq2018 IC of Benchmarq company. This system is aimed to improve the battery monitoring efficiency such that the exact remaining power and time of the battery can be estimated.

The main goal of this thesis is to study the saturation problem arisen from the integrator in a sigma- delta analog- to- digital modulator , especially when the order of the circuit is higher than two .Signal passes through each stage of integrators yield saturation problem. This situation will miss some part of messages .Unable to deliver datas accurately to next stage of the integrator , the output digital signals will be incorrect and can't be recovered to original analog signals . Hence, this thesis proposes an anti-wind-up method by taking sliding mode control theory to avoid integrator saturation. After that, we are going to design and implement two third order sigma-delta modulators based on this method. Simulation and experiment results show the validity of the method and the significant improvement of avoiding saturation problem, and guarantee the designed circuits can translate signals to terminal accurately .

<p>Denna avhandling behandlar analog-digitalomvandling. I synnerhet behandlas postkorrektion av analog-digitalomvandlare (A/D-omvandlare). A/D-omvandlare är i praktiken behäftade med vissa fel som i sin tur ger upphov till distorsion i omvandlarens utsignal. Om felen har ett systematiskt samband med utsignalen kan de avhjälpas genom att korrigera utsignalen i efterhand. Detta verk behandlar den form av postkorrektion som implementeras med hjälp av en tabell ur vilken korrektionsvärden hämtas.</p><p>Innan en A/D-omvandlare kan korrigeras måste felen i den mätas upp. Detta görs genom att estimera omvandlarens överföringsfunktion. I detta arbete behandlas speciellt problemet att skatta kvantiseringsintervallens mittpunkter. Det antas härvid att en referenssignal finns tillgänglig som grund för skattningen. En skattare som baseras på sorterade data visas vara bättre än den vanligtvis använda skattaren baserad på sampelmedelvärde.</p><p>Nästa huvudbidrag visar hur resultatet efter korrigering av en A/D-omvandlare kan predikteras. Omvandlaren antas här ha en viss differentiell olinjäritet och insignalen antas påverkad av ett slumpmässigt brus. Ett postkorrektionssystem, implementerat med begränsad precision, korrigerar utsignalen från A/D-omvandlaren. Ett utryck härleds som beskriver signal-brusförhållandet efter postkorrektion. Förhållandet visar sig bero på den differentiella olinjäritetens varians, det slumpmässiga brusets varians, omvandlarens upplösning samt precisionen med vilken korrektionstermerna beskrivs.</p><p>Till sist behandlas indexering av korrektionstabeller. Valet av metod för att indexera en korrektionstabell påverkar såväl tabellens storlek som förmågan att beskriva och korrigera dynamiska fel. I avhandlingen behandlas i synnerhet tillståndsmodellbaserade metoder, det vill säga metoder där tabellindex bildas som en funktion utav flera på varandra följande sampel. Allmänt gäller att ju fler sampel som används för att bilda ett tabellindex, desto större blir tabellen, samtidigt som förmågan att beskriva dynamiska fel ökar. En indexeringsmetod som endast använder en delmängd av bitarna i varje sampel föreslås här. Vidare så påvisas hur valet av indexeringsbitar kan göras optimalt, och experimentella utvärderingar åskådliggör att tabellstorleken kan reduceras avsevärt utan att fördenskull minska prestanda mer än marginellt.</p><p>De teorier och resultat som framförs här har utvärderats med experimentella A/D-omvandlardata eller genom datorsimuleringar.</p> / <p>Analog-to-digital conversion and quantization constitute the topic of this thesis. Post-correction of analog-to-digital converters (ADCs) is considered in particular. ADCs usually exhibit non-ideal behavior in practice. These non-idealities spawn distortions in the converters output. Whenever the errors are systematic, it is possible to mitigate them by mapping the output into a corrected value. The work herein is focused on problems associated with post-correction using look-up tables. All results presented are supported by experiments or simulations.</p><p>The first problem considered is characterization of the ADC. This is in fact an estimation problem, where the transfer function of the converter should be determined. This thesis deals with estimation of quantization region midpoints, aided by a reference signal. A novel estimator based on order statistics is proposed, and is shown to have superior performance compared with the sample mean traditionally used.</p><p>The second major area deals with predicting the performance of an ADC after post-correction. A converter with static differential nonlinearities and random input noise is considered. A post-correction is applied, but with limited (fixed-point) resolution in the corrected values. An expression for the signal-to-noise and distortion ratio after post-correction is provided. It is shown that the performance is dependent on the variance of the differential nonlinearity, the variance of the random noise, the resolution of the converter and the precision of the correction values.</p><p>Finally, the problem of addressing, or indexing, the correction look-up table is dealt with. The indexing method determines both the memory requirements of the table and the ability to describe and correct dynamically dependent error effects. The work here is devoted to state-space--type indexing schemes, which determine the index from a number of consecutive samples. There is a tradeoff between table size and dynamics: more samples used for indexing gives a higher dependence on dynamic, but also a larger table. An indexing scheme that uses only a subset of the bits in each sample is proposed. It is shown how the selection of bits can be optimized, and the exemplary results show that a substantial reduction in memory size is possible with only marginal reduction of performance.</p>

In this thesis, a time-based oversampling sigma-delta analog-to-digital converter (ADC) architecture is introduced. This system uses time, instead of voltage, as the analog variable for it quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital pulse. The sigma-delta loop integrator, comparator, and subtractor are all time-based circuits and implemented by using only digital gates. The only voltage-based circuit is voltage-to-time Converter (VTC) which requires only a current source. No amplifier is required in the entire circuit. As a proof of concept, the simulation results for a prototype ADC incorporating this time-based sigma-delta ADC architecture is presented. / text

The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In the complete measurement unit, in which the ADC is part of, different sensors will be measured. One set of these sensors are three strain gauges with weak output signals which are to be pre-amplified before being converted. The focus of the application for the ADC has been these sensors as they were considered a limiting factor. The report describes theory for the algorithmic and incremental converter as well as a hybrid converter utilizing both of the two converter structures. All converters are based on one operational amplifier and they operate in repetitive fashions to obtain power efficient designs on a small chip area although at low conversion rates. Two converters have been designed and implemented to different degrees of completeness. One is a 13 bit algorithmic (or cyclic) converter which uses a switching scheme to reduce the problem of capacitor mismatch. This converter was implemented at transistor level and evaluated separately and to some extent also with sub-components. The second converter is a hybrid converter using both the operation of the algorithmic and incremental converter to obtain 16 bits of resolution while still having a fairly high sample rate.