Le volume des convertisseurs électroniques de puissance devient lié, dans une part importante aux composants passifs qui le constituent. En particulier, les condensateurs de découplage constituent une part non négligeable de ce volume. En outre, les évolutions technologiques des composants passifs et particulièrement la densité d'énergie des condensateurs de découplage s'accroit beaucoup moins vite que la densité de puissance des composants actifs auxquels ils sont associés (transistors de puissance). D'autre part, la technologie à film plastique utilisée représente une masse non recyclable qu'il est essentiel de minimiser. Leur rôle est néanmoins fondamental pour le fonctionnement de l'ensemble. Une réduction trop importante de leur valeur conduit à une augmentation de perturbations conduites et rayonnées, voire à une instabilité non contrôlée du bus de tension du véhicule. Cette instabilité, pouvant générer des surtensions importantes, pourrait conduire à une destruction du variateur. Dans certains cas, cette démarche de dimensionnement est compliquée par le fait que d'autres systèmes abonnés au bus source de tension continue participent également aux perturbations conduites, en particulier un deuxième variateur triphasé à découpage. Dans ce cas, un partage du même condensateur de découplage peut-être envisagé. Ceci dit, on est confronté à deux problèmes couplés : - D'une part, le dimensionnement des condensateurs reste lié au courant efficace (du point de vue de l'auto échauffement aussi bien que de l'ondulation de tension qui est également liée à la capacité, autre critère dimensionnant) qu'ils seront amenés à supporter. Il est donc souhaitable de mettre en œuvre des stratégies de réduction de ce courant. - D'autre part, la faible résistance série a tendance à réduire de manière importante le facteur d'amortissement de l'impédance de bus continu vue par l'entrée de l'onduleur. Il convient alors de s'assurer de la maîtrise de la résonance du bus dans une telle situation. Ce travail de recherche explore deux approches complémentaires permettant de minimiser la taille des condensateurs requis et de maîtriser les ondulations de tension à l'entrée du convertisseur : - Développer une stratégie de modulation aussi satisfaisante que possible pour le pilotage d'un onduleur triphasé classique à deux niveaux et trois bras de pont. La contrainte supplémentaire, liée aux risques de résonnance du bus continu, doit être analysée et sera un des objectifs des travaux proposés. - Etudier l’impact que peut avoir une stratégie de modulation sur l’ensemble de la chaine de traction électrique. Des contraintes additionnelles liées à la stratégie de modulation d'un variateur de vitesse automobile sont aussi prises en comptes comme par exemple : - La compensation des effets non-linéaires qui sont dus au comportement de l’onduleur de tension ; - La minimisation du stress exercé sur le condensateur de découplage partagé de manière commune entre deux onduleurs de tension, en termes d’ondulation de tension à ses bornes et de la valeur efficace du courant absorbé. Les résultats théoriques ont été validés expérimentalement sur deux bancs de tests : un premier dédié pour des essais à faible puissance sur une charge passive et un deuxième, monté au site de Lardy de Renault, dédié pour des essais à haute puissance sur une charge réaliste. / The volume of the electronic power converters becomes linked, in a large part, to the passive component which constitute it. In particular, the decoupling capacitors are a significant part of this volume. Moreover, the technological evolutions of the passive components and in particular the energy density of the decoupling capacitors increase much less rapidly than the power density of the active components to which they are associated. On the other hand, the plastic film technology used represents a non-recyclabl mass which it is essential to minimize. The role of the film capacitor is nevertheless fundamental for the functioning of the whole inverter. Too much reduction of their value leads to an increase in conducted and radiated disturbances, or to an uncontrolled instability of the vehicle DC bus voltage. This instability, which can generate significant overvoltages, could lead to a destruction of the switching power devices of the voltage source inverter. In some cases, this design approach could become complicated when other systems could be connected t the same DC voltage source bus, such as a second voltage source inverter. Hence, the same DC link capacitor is shared between the two inverters. Thus, it becomes much solicited and conducted disturbances may be generated. That said, we are confronted with two coupled problems. On the one hand, the design of the capacitors remains linked to the RMS current. It is therefore desirable to implement strategies to reduce this current. On the other hand, the low series resistance tends to reduce significantly the damping factor of the DC bus impedance seen by the input of the inverter. Hence, it is then necessary to ensure control of the resonance of the bus in such a situation. This research explores two complementary approaches to minimize the size of the required capacitors an to control the voltage ripples at the input of the converter: - Develop a P WM strategy that is as satisfactory as possible for controlling a conventional two-level three-phase inverter. The additional constraint, related to the resonance risks of the DC bus, must be analyzed and is one of the objectives of the proposed works. - Study the impact of P WM strategies on the entire electrical traction chain. Additional constraints related to the P WM strategy are also taken into account such as - Compensation for non-linear effects due to the behavior of the voltage inverter; - Minimization of the stress exerted on the decoupling capacitor commonly shared between two voltage source inverters in terms of voltage ripple across its terminals and the rms value of the absorbed current. Theoretical and simulation results have been validated experimentally on two test benches: one dedicated for low power tests on a passive load and the second one, mounted at the Lardy site of Renault, dedicated for hi h ower tests on a dynamic electrical machine.

Os inversores multiníveis podem se beneficiar de filtros de saída reduzidos devido ao menor conteúdo harmônico do sinal sintetizado, dado que suas saídas possuem menores diferenças de tensão durante seu chaveamento. Sua desvantagem é causada pelo elevado número de chaves controladas normalmente necessário para seu funcionamento, e seus circuitos auxiliares. No objetivo de reduzir o número de chaves utilizadas em um inversor de sete níveis, uma nova topologia para um inversor de sete níveis de tensão é apresentada, construída a partir de duas fontes de tensão assimétricas conectadas em série e seis chaves semicondutoras. Este trabalho analisa os princípios de operação desta topologia e a lógica de chaveamento necessária para seu funcionamento. O arranjo proposto não oferece a possibilidade de redução de tensão sobre as chaves, conforme apresentado nas topologias clássicas de inversores com ponto neutro grampeado a diodo ou capacitor e de células em série, mas reduz a quantidade dos componentes necessários para a composição dos sete níveis, sendo possível utilizá-lo em inversores de baixa tensão, devido à seu menor tamanho e complexidade. O estudo apresenta a estrutura resultante em forma de um inversor monofásico por modulação de largura de pulso com disposição das portadoras em oposição de fase, com sete níveis igualmente espaçados, utilizando apenas seis chaves e duas fontes de tensão com alimentação assimétrica, em que a principal fonte tem o dobro da tensão da outra fonte. O funcionamento da topologia é verificado em simulação e implementação de protótipo de 860W. Uma outra versão também é apresentada analiticamente, com melhor grampeamento da tensão, utilizando oito chaves comandadas com uma lógica mais simplificada. Por fim, algumas propostas são sugeridas para a geração dos dois barramentos de tensão necessários. / Multilevel inverters can benefit from reduced output filters due to the lower harmonic content of the synthesized signal, since their outputs have lower voltage differences during their switching. Its disadvantage is caused by the high number of controlled switches and its auxiliary circuits normally required for its operation. In order to reduce the number of switches used in a seven-level inverter, a new topology for a seven level and its auxiliary circuits inverter is presented, constructed from two asymmetrical voltage sources connected in series and six semiconductor switches. This work analyzes the principles of operation of this topology and the switching logic required for its operation. The proposed arrangement does not offer the possibility of voltage reduction on the switches, as presented in the classical inverters topologies with diode or capacitor clamping or the series connected cells, but it reduces the amount of components necessary for the composition of the seven levels, being possible to use it in low voltages inverters, due to its smaller size and complexity. The study presents the resulting structure in the form of a single-phase inverter, using the pulse-width modulation with phase-contrast carriers technique, with seven equally spaced levels, using only six switches and two voltage sources with asymmetrical voltages, in which the main source has double the voltage of the other. The operation of the topology is checked with simulation and an implementation of a 860W prototype. Another version is also presented analytically, with better voltage clamping, using eight keys controlled with a more simplified logic. Finally, some proposals are suggested for the generation of the two necessary voltage rails.

Os sistemas fotovoltaicos tem se difundido mundialmente como uma tecnologia de energia limpa que pode ser utilizada na maior parte do planeta Terra. Isto o torna um sistema muito interessante para geração distribuída. A peça fundamental para o aproveitamento da energia fotovoltaica na geração distribuída é o inversor conectado a rede elétrica. Assim o rendimento deste equipamento influencia diretamente no aproveitamento da energia gerada pelos painéis fotovoltaicos e consequentemente no tempo em que o sistema se paga. O comportamento sazonal da geração de energia, onde o inversor trabalha na maior parte do tempo entre 10% e 90% da capacidade, principalmente em sistemas sem rastreamento, não permite que o inversor seja avaliado somente pelo seu rendimento em plena carga, mas pela curva de rendimento completa em toda faixa de operação. O método proposto para a melhora do rendimento do sistema em baixas potências é a utilização de inversores de baixa potência conectados a rede elétrica em paralelo trabalhando de maneira escalonada. Assim, em baixas potências o rendimento é mais elevado que se fosse utilizado um único inversor. Neste trabalho são avaliados também as consequências do paralelismo na taxa de distorção harmônica da corrente e as vantagens de ampliação na vida útil dos equipamentos e o recurso de redundância. Foram implementados 4 inversores de 300W de saída, na topologia ponte completa com frequência de comutação e amostragem de 21,6kHz, controlados cada um por um DSC 56F8014 da Freescale, e um dispositivo para monitoração dos inversores utilizando um microcontrolador PIC18F4520. Todos os dispositivos possuem interface de comunicação UART isolada com protocolo LIN. Os inversores foram testados em operação com modo de compartilhamento de potência contínuo, onde todos os inversores operam com parcelas identicas de potência, e no modo escalonado, onde os inversores entram em operação sob a demanda da potência a ser processada. Os resultados apresentam uma melhora de 3,7% no rendimento entre o sistema de compartilhamento de potência contínuo e escalonado, avaliados pelo rendimento ponderado do sistema (IEC-61836). / Photovoltaic systems have been spreading globally as a clean energy technology that can be used in most of the planet Earth. This makes it a very interesting system for distributed generation. The key to the use of photovoltaics in distributed generation inverter is connected to the power grid. Thus the performance of this equipment directly influences the use of energy generated by the photovoltaic panels and consequently the time that the system pays for itself. The seasonal behavior of power generation, where the drive works most of the time between 10% and 90% of capacity, especially in systems without tracking, does not allow the drive to be evaluated not only by their performance at full load, but the full yield curve throughout the operating range. The proposed method improves the system performance at low power is the use of low power inverters connected in parallel to mains electricity working in installments. Thus, in the low power output is higher than if a single drive were used. This work also evaluated the consequences of parallelism in the rate of harmonic current distortion and benefits of expanding the life of the equipment and the use of redundancy . We implemented four inverters 300W output full bridge topology with switching frequency of 21.6 kHz and sampling, each controlled by a Freescale 56F8014 DSC, and a device for monitoring the inverters using a PIC18F4520 microcontroler. All devices have isolated communication interface UART with LIN protocol. The inverters were tested in operation mode continuous power sharing , where all the inverters operate with identical plots power, and staggered where the inverters come into operation upon the demand of power being processed. The results show an improvement of 3,7% in revenue sharing system between the power and continued staggered valued at weighted yield of the system (IEC-61836). / 5000

Neste trabalho é proposto o desenvolvimento de um novo microinversor de estágio único para aplicação em sistemas fotovoltaicos. A topologia apresentada é baseada na combinação do conversor Cuk com uma estrutura de indutores chaveados para obtenção de um maior ganho estático e um circuito inversor em ponte completa conectado à rede. A estrutura de indutores chaveados apresentada nesse trabalho reduz esforços de tensão e corrente nas chaves semicondutoras. Com o objetivo de facilitar o controle, a etapa CC do microinversor opera em modo de condução descontínua (DCM). Para injetar corrente senoidal com baixa distorção harmônica à rede, é aplicado às chaves semicondutoras da etapa CC uma modulação por largura de pulso senoidal (SPWM). As chaves semicondutoras do circuito inversor em ponte completa são comandadas na frequência da rede, reduzindo perdas por chaveamento. Por se tratar de uma topologia inédita, são apresentados os modos de operação e a análise matemática do conversor CC-CC Cuk com alto ganho estático. Posteriormente, são realizadas a análise teórica e a estratégia de controle do microinversor proposto. Os resultados experimentais são expostos para discutir o funcionamento da topologia proposta, através de simulações e da implementação de um protótipo de 180 W. / The development of a novel single stage microinverter is proposed. The presented topology is based on the combination of the Cuk converter with a switched inductor structure to obtain a higher static gain, and a full-bridge inverter circuit. The presented switched inductor structure reduces voltage and current stresses on the power switches. In order of simplify the control, the stage CC of the microinverter operate in discontinuous conduction mode (DCM). To inject sinusoidal current with low harmonic distortion to the grid, a sinusoidal pulse width modulation (SPWM) is applied in the power switches. The switches of the full-bridge invertes are commanded in low frequency, in order to reduce switching losses. Operation modes and math analysis of the novel CC-CC converter are presented. Moreover, the math analysis and control strategy of proposed microinverter topology are exposed. Furthermore, experimental results are performed to analyze the proposed topology operation, by software simulations and implementation of a 180 W prototype.

Os sistemas fotovoltaicos tem se difundido mundialmente como uma tecnologia de energia limpa que pode ser utilizada na maior parte do planeta Terra. Isto o torna um sistema muito interessante para geração distribuída. A peça fundamental para o aproveitamento da energia fotovoltaica na geração distribuída é o inversor conectado a rede elétrica. Assim o rendimento deste equipamento influencia diretamente no aproveitamento da energia gerada pelos painéis fotovoltaicos e consequentemente no tempo em que o sistema se paga. O comportamento sazonal da geração de energia, onde o inversor trabalha na maior parte do tempo entre 10% e 90% da capacidade, principalmente em sistemas sem rastreamento, não permite que o inversor seja avaliado somente pelo seu rendimento em plena carga, mas pela curva de rendimento completa em toda faixa de operação. O método proposto para a melhora do rendimento do sistema em baixas potências é a utilização de inversores de baixa potência conectados a rede elétrica em paralelo trabalhando de maneira escalonada. Assim, em baixas potências o rendimento é mais elevado que se fosse utilizado um único inversor. Neste trabalho são avaliados também as consequências do paralelismo na taxa de distorção harmônica da corrente e as vantagens de ampliação na vida útil dos equipamentos e o recurso de redundância. Foram implementados 4 inversores de 300W de saída, na topologia ponte completa com frequência de comutação e amostragem de 21,6kHz, controlados cada um por um DSC 56F8014 da Freescale, e um dispositivo para monitoração dos inversores utilizando um microcontrolador PIC18F4520. Todos os dispositivos possuem interface de comunicação UART isolada com protocolo LIN. Os inversores foram testados em operação com modo de compartilhamento de potência contínuo, onde todos os inversores operam com parcelas identicas de potência, e no modo escalonado, onde os inversores entram em operação sob a demanda da potência a ser processada. Os resultados apresentam uma melhora de 3,7% no rendimento entre o sistema de compartilhamento de potência contínuo e escalonado, avaliados pelo rendimento ponderado do sistema (IEC-61836). / Photovoltaic systems have been spreading globally as a clean energy technology that can be used in most of the planet Earth. This makes it a very interesting system for distributed generation. The key to the use of photovoltaics in distributed generation inverter is connected to the power grid. Thus the performance of this equipment directly influences the use of energy generated by the photovoltaic panels and consequently the time that the system pays for itself. The seasonal behavior of power generation, where the drive works most of the time between 10% and 90% of capacity, especially in systems without tracking, does not allow the drive to be evaluated not only by their performance at full load, but the full yield curve throughout the operating range. The proposed method improves the system performance at low power is the use of low power inverters connected in parallel to mains electricity working in installments. Thus, in the low power output is higher than if a single drive were used. This work also evaluated the consequences of parallelism in the rate of harmonic current distortion and benefits of expanding the life of the equipment and the use of redundancy . We implemented four inverters 300W output full bridge topology with switching frequency of 21.6 kHz and sampling, each controlled by a Freescale 56F8014 DSC, and a device for monitoring the inverters using a PIC18F4520 microcontroler. All devices have isolated communication interface UART with LIN protocol. The inverters were tested in operation mode continuous power sharing , where all the inverters operate with identical plots power, and staggered where the inverters come into operation upon the demand of power being processed. The results show an improvement of 3,7% in revenue sharing system between the power and continued staggered valued at weighted yield of the system (IEC-61836). / 5000

Neste trabalho é proposto o desenvolvimento de um novo microinversor de estágio único para aplicação em sistemas fotovoltaicos. A topologia apresentada é baseada na combinação do conversor Cuk com uma estrutura de indutores chaveados para obtenção de um maior ganho estático e um circuito inversor em ponte completa conectado à rede. A estrutura de indutores chaveados apresentada nesse trabalho reduz esforços de tensão e corrente nas chaves semicondutoras. Com o objetivo de facilitar o controle, a etapa CC do microinversor opera em modo de condução descontínua (DCM). Para injetar corrente senoidal com baixa distorção harmônica à rede, é aplicado às chaves semicondutoras da etapa CC uma modulação por largura de pulso senoidal (SPWM). As chaves semicondutoras do circuito inversor em ponte completa são comandadas na frequência da rede, reduzindo perdas por chaveamento. Por se tratar de uma topologia inédita, são apresentados os modos de operação e a análise matemática do conversor CC-CC Cuk com alto ganho estático. Posteriormente, são realizadas a análise teórica e a estratégia de controle do microinversor proposto. Os resultados experimentais são expostos para discutir o funcionamento da topologia proposta, através de simulações e da implementação de um protótipo de 180 W. / The development of a novel single stage microinverter is proposed. The presented topology is based on the combination of the Cuk converter with a switched inductor structure to obtain a higher static gain, and a full-bridge inverter circuit. The presented switched inductor structure reduces voltage and current stresses on the power switches. In order of simplify the control, the stage CC of the microinverter operate in discontinuous conduction mode (DCM). To inject sinusoidal current with low harmonic distortion to the grid, a sinusoidal pulse width modulation (SPWM) is applied in the power switches. The switches of the full-bridge invertes are commanded in low frequency, in order to reduce switching losses. Operation modes and math analysis of the novel CC-CC converter are presented. Moreover, the math analysis and control strategy of proposed microinverter topology are exposed. Furthermore, experimental results are performed to analyze the proposed topology operation, by software simulations and implementation of a 180 W prototype.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

Multilevel inverters are very popular for medium and high-voltage induction motor (IM) drive applications. They have superior performance compared to 2-level inverters such as reduced harmonic content in output voltage and current, lower common mode voltage and dv/dt, and lesser voltage stress on power switches. To get nearly sinusoidal current waveforms, the switching frequency of the conventional inverters have to be in¬creased. This will lead to higher switching losses and electromagnetic interference. The problem in using lower switching frequency is the introduction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching. Dodecagonal voltage space-vector based multilevel inverters have been proposed as an improvement over the conventional hexagonal space vector based inverters. They achieve complete elimination of 5th and 7th order harmonics throughout the modulation range. The linear modulation range is also extended by about 6.6%, since the dodecagon is closer to circle than a hexagon. The previous works on dodecagonal voltage space vector based VSI fed drives used voltage controlled PWM (VC-PWM). Although these controllers are more popular, they have inferior dynamic performance when compared to current controlled PWM (CC¬PWM). VSIs using current controlled PWM have excellent dynamic response, inherent short-circuit protection and are simple to implement. The conventional CC-PWM tech¬niques have large switching frequency variation and large current ripple in steady-state. xix As a result, there has been significant research interest to achieve current controlled VSI fed IM drives with constant switching frequency. Two current error space vector (CESV) based hysteresis controllers for dodecagonal voltage space-vector based VSI fed induction motor drives are proposed in this work. The proposed controllers achieve nearly constant switching frequency at steady state operation, similar to VC-SVPWM based VSI fed IM drives. They also have fast dynamic response while at the same time achieving complete elimination of fifth and seventh order harmonics for the entire modulation range, due to dodecagonal voltage vector switching. The first work proposes a nearly constant switching frequency current error space vector (CESV) based hysteresis controller for an IM drive with single dodecagonal voltage space vectors. Parabolic boundaries computed offline are used in the proposed controller. An open-end winding induction motor is fed from two inverters with asymmetrical DC link voltages, to generate the dodecagonal voltage space vectors. The drive scheme is first studied at different frequencies with a space vector based PWM (SVPWM) control, to obtain the current error space vector boundaries. The CESV boundary at each frequency can be approximated with four parabolas. These parabolic boundaries are used in the proposed controller to limit the CESV trajectory. Due to symmetries in the parabolas only two set of parabola parameters, at different frequencies, need to be stored. A generalized next vector selection logic, valid for all sectors and rotation direction, is used in the proposed controller. For this an axis transformation is done in all sectors, to bring the CESV trajectory to the first sector. The sector information is obtained from the estimated fundamental stator phase voltage. The proposed controller is extensively studied using vector control at different frequencies and transient conditions. This controller maintains nearly constant switching frequency at steady state operation, similar to VC-SVPWM inverters, while at the same time achieving better dynamic performance and complete elimination of 5th and 7th order harmonics throughout the modulation range. In the second work the nearly constant switching frequency current hysteresis con¬troller is extended to multilevel dodecagonal voltage space-vector based IM drives, with online computation of CESV boundaries. The multilevel dodecagonal space-vector dia¬gram has different types of triangles, and the previously proposed methods for multilevel hexagonal VSI based current hysteresis controllers cannot be used directly. The CESV trajectory of the VC-SVPWM, obtained for present triangular region, is used as the reference trajectory of the proposed controller. The CESV reference boundaries are com¬puted online, using switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages, which are found out from the stator current error ripple and the parameters of the induction motor. Whenever the actual current error space vector crosses the reference CESV tra¬jectory, an appropriate vector that will force it along the reference trajectory is switched. Extensive study of the proposed controller using vector control is done at different fre¬quencies and transient conditions. This controller has all the advantages of multilevel switching like low dv/dt, lesser electromagnetic interference, lower switch voltage stress and lesser harmonic distortion, in addition to all the dynamic performance advantages of the previous controller. The third work proposes an elegant 5th and 7th order harmonic suppression tech¬nique for open end winding split-phase induction motors, using capacitor fed inverters. Split-phase induction motors have been proposed to reduce the torque and flux ripples of conventional three-phase IM. But these motors have high 5th and 7th order harmonics in the stator windings due to lack of back-emf for these frequencies. A space-vector harmonic analysis of the split-phase IM is conducted and possible 5th and 7th order harmonic sup¬pression techniques studied. A simple harmonic suppression scheme is proposed, which requires the use of only capacitor fed inverters. A PWM scheme that can maintain the capacitor voltage as well as suppress the 5th and 7th order harmonics is also proposed. To test the performance of the proposed scheme, an open-loop v/f control is used on an open-end winding split-phase induction motor under no-load condition. Synchronized PWM with two samples per sector was used, for frequencies above 10 Hz. The har¬monic spectra of the phase voltages and currents were computed and compared with the traditional SVPWM scheme, to highlight the harmonic suppression. The concepts were initially simulated in Matlab/Simulink. Experimental verifica¬tion was done using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control tech¬niques presented shall still remain applicable. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the first work the output pins of the DSP was directly used to drive the inverter switches through a dead-band circuit. For the other two works, DSP outputs the sector information and the PWM signals. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. An FPGA (XC3S200) was used to translate the sector information and the PWM signals to IGBT gate signal logic. A constant dead-time of 1.5 µs was also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. The phase currents and DC bus voltages were measured using hall-effect sensors. An incremental shaft position encoder was also connected to the motor to measure the angular velocity. The switches were realized using 1200 V, 75 A IGBT half bridge modules.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.