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INTRODUÇÃO: A gagueira do desenvolvimento é uma patologia caracterizada por rupturas involuntárias no fluxo de fala, causadas por déficits no processamento neuromotor para a fala. Estes sintomas têm como consequência uma variedade de reações fisiológicas, comportamentais, cognitivas e emocionais para a pessoa que gagueja. O objetivo geral deste trabalho foi investigar os efeitos do tratamento fonoaudiológico para gagueira baseado em dispositivos de alteração de feedback auditivo, e compará-los aos efeitos do tratamento tradicional, baseado em estratégias comportamentais. MÉTODOS: Esta tese foi desenvolvida no formato de compilação de artigos científicos. Foram compilados três artigos, dois já publicados em periódicos com indexação na base de dados Web of Science e um terceiro artigo já submetido para publicação, em processo de revisão por pares. Foi incluída ainda uma análise crítica das contribuições dos artigos compilados para a área da Fonoaudiologia. RESULTADOS: Os estudos analisados não apresentaram diferenças significativas entre os resultados das duas abordagens terapêuticas investigadas; ambos os protocolos terapêuticos alcançaram melhora pós-tratamento, medida por meio da performance da fluência de fala e da qualidade de vida auto referida. CONCLUSÕES: Os dispositivos de alteração do feedback auditivo podem ser utilizados como recurso no tratamento da gagueira em adultos / INTRODUCTION: Developmental stuttering is a pathology characterized by involuntary disruptions in speech flow and is caused by deficits in neuromotor processing involved in speech production. These symptoms result in a variety of physiological, behavioral, cognitive and emotional consequences to the person who stutters. This study aimed to investigate the effects of a therapeutic approach for stuttering treatment based on altered auditory feedback devices, and to compare them with a traditional behavioral therapeutic approach. METHODS: This thesis is a compilation of two papers published in peerreviewed scientific journals indexed in the Web of Science database, and one unpublished manuscript, submitted to a scientific journal and currently awaiting review by peers. A critical analysis of the contributions of the compiled papers to the Speech-Language Pathology field was performed. RESULTS: The results presented in the analyzed papers did not show differences between the outcomes of the two therapeutic approaches; both protocols achieved improvements, as measured by speech fluency performance and selfreported quality of life. CONCLUSIONS: Altered auditory feedback devices may be used as a resource for the treatment of adults who stutter

I noticed that the workers had the same itinerary when emptying trashcans, meanwhile trashcans needed urgently to be emptied. Traditionally, ETSU maintenance operate on daily routes to pick trash on designated time, regardless the level of the containers. This leads to overflown trashcan in busy areas or during rush hours in certain areas. This overflown trashcan result in an unclean environment for the community and an unpleasant look of our beautiful campus. The time, resources and labor invested in collecting the trash could be saved. Therefore, I decided to use the Internet of Things (IoT) to create a device that will optimize trash collection, to reduce costs and pollution. The Eco-Smart Can will contain a renewable source of energy such as the solar panel. Furthermore, it will have a compactor as well to decrease the trash volume. The system in the Eco-Smart can will give prior information of the trash level to maintenance facility so that they can empty the trash in a timely manner and preserve the environment.

Memristor is a novel passive electronic device and a promising candidate for new generation non-volatile memory and analog computing. Analog computing based on memristors has been explored in this study. Due to the lack of commercial electrical testing instruments for those emerging devices and crossbar arrays, we have designed and built testing circuits to implement analog and parallel computing operations. With the setup developed in this study, we have successfully demonstrated image processing functions utilizing large memristor crossbar arrays. We further designed and experimentally demonstrated the first memristor based field programmable analog array (FPAA), which was successfully configured for audio equalizer and frequency classifier demonstration as exemplary applications of such memristive FPAA (memFPAA).

Over the past few years, the size of semiconductor devices has been shrinking whereas the density of transistors has exponentially increased. Thus, thermal management has become a serious concern as device performance and reliability is greatly affected by heat. An understanding of thermal transport properties at device level along with predictive modelling can lead us to design of new systems and materials tailored according to the thermal conductivity. In our work we first review different models used to calculate thermal conductivity and examine their accuracy using the experimentally measured thermal conductivity for Si. Our results suggest that empirically calculated rates used in thermal conductivity calculations do not capture the scaling behavior for three phonon scattering mechanism properly. This directly affects the estimation of the thermal conductivity and therefore we need to capture them more accurately. Also, we observe that at low temperature the Callaway and the improved Callaway model show good agreement where boundary scattering is dominant, whereas at high temperature iterative and RTA models show good agreement where three-phonon scattering is dominant. Therefore, their lies a need for a model which can characterize K properly at low and high temperature. Second, we then calculate the three phonon scattering rates using first-principles and combine them into the Callaway model. Through our work we successfully build a hybrid model which can be used to describe thermal conductivity of Si for a temperature range of 10K to 425K which captures the thermal conductivity accurately. We also show that in case of Si the improved Callaway model and Callaway model both perform equally well.

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.

CuI is a p-type transparent conductive semiconductor with unique optoelectronic properties, including wide band gap (3.1 eV), high hole mobility (>40 cm2 V−1 s−1 in bulk), and large room-temperature exciton binding energy (62 meV). The difficulty in epitaxy of CuI is the main obstacle for its application in advanced solid-state electronic devices. Herein, room-temperature heteroepitaxial growth of CuI on various substrates with well-defined in-plane epitaxial relations is realized by reactive sputtering technique. In such heteroepitaxial growth the formation of rotation domains is observed and hereby systematically investigated in accordance with existing theoretical study of domain-epitaxy. The controllable epitaxy of CuI thin films allows for the combination of p-type CuI with suitable n-type semiconductors with the purpose to fabricate epitaxial thin film heterojunctions. Such heterostructures have superior properties to structures without or with weakly ordered in-plane orientation. The obtained epitaxial thin film heterojunction of p-CuI(111)/n-ZnO(00.1) exhibits a high rectification up to 2 × 109 (±2 V), a 100-fold improvement compared to diodes with disordered interfaces. Also a low saturation current density down to 5 × 10−9 Acm−2 is formed. These results prove the great potential of epitaxial CuI as a promising p-type optoelectronic material.

This research focused on the development of new metal triimine complexes of Pt(II), Pd(II), and Ni(II) for use in three types of molecular electronic devices: dye sensitized solar cells (DSSCs), organic light-emitting diodes (OLEDs), and organic field effect transistors (OFETs). Inorganic complexes combine many advantages of their chemical and photophysical properties and are processable on inexpensive and large area substrates for various optoelectronic applications. For DSSCs, a series of platinum (II) triimine complexes were synthesized and evaluated as dyes for nanocrystalline oxide semiconductors. Pt (II) forms four coordinate square planar complexes with various co-ligands and counterions and leads to spanning absorption across a wide range in the UV-Vis-NIR regions. When those compounds were applied to the oxide semiconductors, they led to photocurrent generation thus verifying the concept of their utility in solar cells. In the OLEDs project, a novel pyridyl-triazolate Pt(II) complex, Pt(ptp)2 was synthesized and generated breakthrough OLEDs. In the solution state, the electronic absorption and emission of the square planar structure results in metal-to-ligand charge transfer (MLCT) and an aggregation band. Tunable photoluminescence and electroluminescence colors from blue to red wavelengths have been attained upon using Pt(ptp)2 under different experimental conditions and OLED architectures. In taking advantage of these binary characteristics for both monomer and excimer emissions, cool and warm white OLEDs suitable for solid-state lighting have been fabricated. The OFETs project represented an extension of the study of pyridyl-triazolate d8 metal complexes due to their electron-transporting behavior and n-type properties. A prescreening step by using thermogravimetric calorimetry has demonstrated the stability of all three M(ptp)2 and M(ptp)2(py)2 compounds and their amenability to sublimation. Preliminary current-voltage measurements from simple diodes has achieved unidirectional current from a Pt(ptp)2 neat layer and demonstrated its n-type semiconducting behavior.

With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner. However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic. Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.

The famous Moore's law states: Since the invention of the integrated circuit, the number of transistors that can be placed on an integrated circuit has increased exponentially, doubling approximately every two years. As a result of the downscaling of the size of the transistor, quantum effects have become increasingly important while affecting significantly the device performances. Nowadays, at the nanometer scale, inter-atomic interactions and quantum mechanical properties need to be studied extensively. Device and material simulations are important to achieve these goals because they are flexible and less expensive than experiments. They are also important for designing and characterizing new generation of electronic device such as silicon nanowire or carbon nanotube (CNT) transistors. Several modeling methods have been developed and applied to electronic structure calculations, such as: Hartree-Fock, density functional theory (DFT), empirical tight-binding, etc. For transport simulations, most of the device community focuses on studying the stationary problem for obtaining characteristics such as I-V curves. The non-equilibrium transport problem is then often addressed by solving a multitude of time-independent Schrodinger-type equation for all possible energies. On the other hand, for many other electronic applications including high-frequency electronics response (e.g. when a time-dependent potential is applied to the system), the description of the system behavior necessitate insights on the time dependent electron dynamics. To address this problem, it is then necessary to solve a time-dependent Schrodinger-type equation. In this thesis, we will focus on solving time-dependent problems with application to CNTs. We will be identifying all the numerical difficulties and propose new effective modeling and numerical schemes to address the current limitations in time-dependent quantum simulations. we will point out that two numerical errors may occur: an integration error and the anti-commutation issue error; the direct computation above being mathematically equivalent to performing the integration of the time dependent Hamiltonian using a rectangle numerical quadrature formula along the total simulation times. After careful study and many numerical experiments, we found that the Gaussian quadrature scheme provides a good trade off between computational consumption and numerically accuracy, meanwhile unitary, stability and time reversal properties are well preserved. The new Gaussian quadrature integration scheme uses (i) much fewer points in time to approximate the integral of the Hamiltonian, (ii) ordered exponential to factorize the time evolution operator, (iii) FEM discretize techniques (iv) and at last, the FEAST eigenvalue solver to diagonalize and solve each exponential.