Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

La théorie, la conception, l'optimisation et la caractérisation d'amplificateurs distribués en technologie TBDH InP 0,7 µm, pour les systèmes de communications optiques à 100 Gbit/s, sont présentés. Nous montrons comment l'exploitation adaptée du concept d'amplificateur distribué avec une technologie de transistors bipolaires à produit vitesse-amplitude élevé a permis la réalisation d'un driver de modulateur électro-optique fournissant une amplitude différentielle d'attaque de 6,2 et 5,9 Vpp, à 100 et 112 Gbit/s, respectivement, avec une qualité de signal élevée. Ce circuit établit ainsi le record de produit vitesse-amplitude à 660 Gbit/s.V sur tranche et 575 Gbit/s.V en module hyperfréquence. Dans le cadre du projet Européen POLYSYS, il a été associé à un laser accordable et un modulateur pour la réalisation d'un module transmetteur optoélectronique compact, démontrant des performances avançant l'état de l'art des communications optiques courtes distances à 100 Gbit/s. / The theory, design, optimisation and characterisation of distributed amplifiers in 0.7-µm InP DHBT technology, for 100-Gbit/s optical communication systems, are presented. We show how the appropriate implementation of the distributed amplifier concept in a bipolar transistors technology with high swing-speed product has enabled the realisation of an electro-optic modulator driver with 6.2- and 5.9-Vpp differential driving amplitude at 100 and 112 Gb/s, respectively, with a high signal quality. This circuit thus establishes the swing-speed product record at 660 Gb/s.V on wafer and at 575 Gb/s.V in a microwave module. In the frame of the European project POLYSYS, it has been co-packaged with a tunable laser and a modulator to realise a compact optoelectronic transmitter module, which has demonstrated performances advancing the state of the art of short reach 100-Gb/s optical communications.

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

Le travail presente dans ce memoire a pour objet principal l'etude des phenomenes de bruit du fond electrique basse frequence dans des transistors pour applications micro-ondes de type effet de champ (HEMT) sur SiGe et GaN ainsi que de type bipolaire a heterojonction (TBH) a base de silicium-germanium (SiGe). Dans un premier chapitre nous rappelons les caracteristiques et proprietes essentielles des sources de bruit en exces que l'on rencontre generalement dans ce type de composants et proposons une description des bancs de mesure de bruit mis en oeuvre. Dans les deuxieme et troisieme chapitres, nous proposons une analyse detaillee de l'evolution du bruit observe en fonction de la frequence, de la polarisation, et de la geometrie sur des HEMTs des deux familles technologiques SiGe et GaN. Nous avons en particulier etudie les deux generateurs de bruit en courant en entree et en sortie respectivement iG et iD ainsi que leur correlation. Ceci nous a permis, en nous appuyant aussi sur l'analyse des caracteristiques statiques des transistors, d'identifier les diverses sources de bruit en exces presentes dans ces composants et de faire des hypotheses sur leurs origines. Le dernier chapitre est consacre aux TBHs a base de SiGe. Dans une premiere partie nous etablissons comment varie le bruit basse frequence de TBHs, fabriques par un premier constructeur, en fonction de la polarisation, de la geometrie et de la fraction molaire de germanium. Dans une seconde partie nous mettons en evidence, d'apres nos observations effectuees sur des TBHs fabriques par un second constructeur, l'impact important sur le bruit BF de stress thermiques appliques sur ce type de composants.

Der thermische Widerstand ist eine wichtige Kenngröße von Silicium-Germanium-Hetero-Bipolartransistoren (SiGe-HBTs). Bisher kam es bei der quantitativen Bestimmung der thermischen Widerstände von SiGe-HBTs zu deutlichen Abweichungen zwischen Simulation und Messung. Der Unterschied zwischen Simulation und Messung betrug bei den untersuchten HBTs mehr als 30 Prozent. Diese Arbeit widmet sich der Aufklärung und Beseitigung der möglichen Ursachen hierfür. Zu diesem Zweck werden als erstes die Messmethoden analysiert. Es zeigt sich, dass die bisher verwendete Extraktionsmethode sensitiv auf den Early-Effekt (Basisweitenmodulation) reagiert. Im Rahmen der Untersuchungen wurde ein neues Extraktionsverfahren entwickelt. Die neue Extraktions­methode ist unempfindlich gegenüber dem Early-Effekt. Mit Bauelemente­simulationen wird erstmalig die Wirkung des Seebeck-Effektes (Thermospannungen) auf die elektrisch extrahierten thermischen Widerstände demonstriert. Der Seebeck-Effekt bewirkt, dass die elektrisch extrahierten thermischen Widerstände der untersuchten HBTs nahezu 10 Prozent kleiner als die erwarteten Werte sind. Dieser Effekt wurde bisher nicht beachtet und wird hier erstmals nachgewiesen. Weiterhin wird die Abhängigkeit des thermischen Widerstandes vom Arbeitspunkt untersucht. Dabei hat sich gezeigt, dass bis zu einer Basis-Emitter-Spannung von 0,91 Volt die geometrische Form des Wärme abgebenden Gebietes unabhängig vom Arbeitspunkt ist. Anhand von Messungen wird gezeigt, dass die Dotierung die spezifische Wärmeleitfähigkeit von Silicium reduziert. Die Abnahme wird für Dotierungen größer als 1*1019 cm‑3 deutlich sichtbar. Ist die Dotierung größer als 1*1020 cm‑3, beträgt die Abnahme der spezifischen Wärmeleitfähigkeit mehr als 75 Prozent. Mithilfe einer Simulatorkalibrierung wird die spezifische Wärmeleitfähigkeit als Funktion der Dotierung bestimmt. Die erhaltene Funktion kann künftig beim thermischen Entwurf von HBTs verwendet werden. Somit können zukünftig genauere Vorhersagen zum thermischen Widerstand der HBTs gemacht werden. Dies ermöglicht zuverlässigere Aussagen darüber, wie Änderungen des Transistordesigns zur Minimierung des thermischen Widerstandes beitragen. / The thermal resistance is an important parameter of silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Until now, the quantitative determination of the thermal resistance showed significant differences between measurements and simulations. The difference between simulation and measurement of the investigated HBTs was more than 30 percent. This thesis devotes the clarification and elimination of potential sources for it. For this purpose, the measurement methods are analyzed at first. It is shown, that the currently used extraction method is sensitive to the Early effect (basewidth modulation). A now extraction method was developed, which is not sensitive to the Early effect. For the first time, the influence of the Seebeck effect (thermoelectric voltages) on the electrically extracted thermal resistance is shown by device simulations. The Seebeck effect leads to a 10 percent lower extracted thermal resistances compared to the expected values of the investigated HBTs. This effect was not taken into account up to now and is demonstrated here for the first time. Furthermore, the dependence of the thermal resistance on the operating point was investigated. The results show that the shape of the heat source is independent of the operating point if the base emitter voltage is smaller than 0.91 volt. The thermal conductivity of silicon is decreased by increasing doping concentrations. This is shown by measurements. The reduction of the thermal conductivity is well observable for doping concentrations higher than 1*1019 cm‑3. For doping concentration higher than 1*1020 cm‑3 the reduction amounts to more than 75 percent. The thermal conductivity was determined as a function of the doping concentration with the aid of a simulator calibration. This function can be used in the future thermal design of HBTs. It facilitates the optimization of the HBTs with respect to a minimal thermal resistance.

The field of infrared (IR) detector technology has shown vast improvements in terms of speed and performance over the years. Specifically the dynamic range (DR) and sensitivity of detectors showed significant improvements. The most commonly used technique of implementing these IR detectors is the use of charge-coupled devices (CCD). Recent developments show that the newly investigated bipolar complementary metal-oxide semiconductor (BiCMOS) devices in the field of detector technology are capable of producing similar quality detectors at a fraction of the cost. Prototyping is usually performed on low-cost silicon wafers. The band gap energy of silicon is 1.17 eV, which is too large for an electron to be released when radiation is received in the IR band. This means that silicon is not a viable material for detection in the IR band. Germanium exhibits a band gap energy of 0.66 eV, which makes it a better material for IR detection. This research is aimed at improving DR and sensitivity in IR detectors. CCD technology has shown that it exhibits good DR and sensitivity in the IR band. CMOS technology exhibits a reduction in prototyping cost which, together with electronic design automation software, makes this an avenue for IR detector prototyping. The focus of this research is firstly on understanding the theory behind the functionality and performance of IR detectors. Secondly, associated with this, is determining whether the performance of IR detectors can be improved by using silicon germanium (SiGe) BiCMOS technology instead of the CCD technology most commonly used. The Simulation Program with Integrated Circuit Emphasis (SPICE) was used to realise the IR detector in software. Four detectors were designed and prototyped using the 0.35 µm SiGe BiCMOS technology from ams AG as part of the experimental verification of the formulated hypothesis. Two different pixel structures were used in the four detectors, which is the silicon-only p-i-n diodes commonly found in literature and diode-connected SiGe heterojunction bipolar transistors (HBTs). These two categories can be subdivided into two more categories, which are the single-pixel-single-amplifier detectors and the multiple-pixel-single-amplifier detector. These were needed to assess the noise performance of different topologies. Noise influences both the DR and sensitivity of the detector. The results show a unique shift of the detecting band typically seen for silicon detectors to the IR band, accomplished by using the doping feature of HBTs using germanium. The shift in detecting band is from a peak of 250 nm to 665 nm. The detector still accumulates radiation in the visible band, but a significant portion of the near-IR band is also detected. This can be attributed to the reduced band gap energy that silicon with doped germanium exhibits. This, however, is not the optimum structure for IR detection. Future work that can be done based on this work is that the pixel structure can be optimised to move the detecting band even more into the IR region, and not just partially. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted

A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures. / Dissertation (MEng)--University of Pretoria, 2012. / Electrical, Electronic and Computer Engineering / unrestricted

Der thermische Widerstand ist eine wichtige Kenngröße von Silicium-Germanium-Hetero-Bipolartransistoren (SiGe-HBTs). Bisher kam es bei der quantitativen Bestimmung der thermischen Widerstände von SiGe-HBTs zu deutlichen Abweichungen zwischen Simulation und Messung. Der Unterschied zwischen Simulation und Messung betrug bei den untersuchten HBTs mehr als 30 Prozent. Diese Arbeit widmet sich der Aufklärung und Beseitigung der möglichen Ursachen hierfür. Zu diesem Zweck werden als erstes die Messmethoden analysiert. Es zeigt sich, dass die bisher verwendete Extraktionsmethode sensitiv auf den Early-Effekt (Basisweitenmodulation) reagiert. Im Rahmen der Untersuchungen wurde ein neues Extraktionsverfahren entwickelt. Die neue Extraktions­methode ist unempfindlich gegenüber dem Early-Effekt. Mit Bauelemente­simulationen wird erstmalig die Wirkung des Seebeck-Effektes (Thermospannungen) auf die elektrisch extrahierten thermischen Widerstände demonstriert. Der Seebeck-Effekt bewirkt, dass die elektrisch extrahierten thermischen Widerstände der untersuchten HBTs nahezu 10 Prozent kleiner als die erwarteten Werte sind. Dieser Effekt wurde bisher nicht beachtet und wird hier erstmals nachgewiesen. Weiterhin wird die Abhängigkeit des thermischen Widerstandes vom Arbeitspunkt untersucht. Dabei hat sich gezeigt, dass bis zu einer Basis-Emitter-Spannung von 0,91 Volt die geometrische Form des Wärme abgebenden Gebietes unabhängig vom Arbeitspunkt ist. Anhand von Messungen wird gezeigt, dass die Dotierung die spezifische Wärmeleitfähigkeit von Silicium reduziert. Die Abnahme wird für Dotierungen größer als 1*1019 cm‑3 deutlich sichtbar. Ist die Dotierung größer als 1*1020 cm‑3, beträgt die Abnahme der spezifischen Wärmeleitfähigkeit mehr als 75 Prozent. Mithilfe einer Simulatorkalibrierung wird die spezifische Wärmeleitfähigkeit als Funktion der Dotierung bestimmt. Die erhaltene Funktion kann künftig beim thermischen Entwurf von HBTs verwendet werden. Somit können zukünftig genauere Vorhersagen zum thermischen Widerstand der HBTs gemacht werden. Dies ermöglicht zuverlässigere Aussagen darüber, wie Änderungen des Transistordesigns zur Minimierung des thermischen Widerstandes beitragen. / The thermal resistance is an important parameter of silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Until now, the quantitative determination of the thermal resistance showed significant differences between measurements and simulations. The difference between simulation and measurement of the investigated HBTs was more than 30 percent. This thesis devotes the clarification and elimination of potential sources for it. For this purpose, the measurement methods are analyzed at first. It is shown, that the currently used extraction method is sensitive to the Early effect (basewidth modulation). A now extraction method was developed, which is not sensitive to the Early effect. For the first time, the influence of the Seebeck effect (thermoelectric voltages) on the electrically extracted thermal resistance is shown by device simulations. The Seebeck effect leads to a 10 percent lower extracted thermal resistances compared to the expected values of the investigated HBTs. This effect was not taken into account up to now and is demonstrated here for the first time. Furthermore, the dependence of the thermal resistance on the operating point was investigated. The results show that the shape of the heat source is independent of the operating point if the base emitter voltage is smaller than 0.91 volt. The thermal conductivity of silicon is decreased by increasing doping concentrations. This is shown by measurements. The reduction of the thermal conductivity is well observable for doping concentrations higher than 1*1019 cm‑3. For doping concentration higher than 1*1020 cm‑3 the reduction amounts to more than 75 percent. The thermal conductivity was determined as a function of the doping concentration with the aid of a simulator calibration. This function can be used in the future thermal design of HBTs. It facilitates the optimization of the HBTs with respect to a minimal thermal resistance.

Les procédés bipolaires semi-conducteurs complémentaires à oxyde de métal (BiCMOS) peuvent être considérés comme étant la solution la plus généralepour les produits RF car ils combinent la fabrication sophistiquée du CMOSavec la vitesse et les capacités de conduction des transistors bipolaires silicium germanium(SiGe) à hétérojonction (HBT). Les HBTs, réciproquement, sontles principaux concurrents pour combler partiellement l'écart de térahertzqui décrit la plage dans laquelle les fréquences générées par les transistors etles lasers ne se chevauchent pas (environ 0.3 THz à 30 THz). A_n d'évaluerles capacités de ces dispositifs futurs, une méthodologie de prévision fiable estsouhaitable. L'utilisation d'un ensemble hétérogène d'outils et de méthodes desimulations permet d'atteindre successivement cet objectif et est avantageusepour la résolution des problèmes. Plusieurs domaines scientifiques sont combinés, tel que la technologie de conception assistée par ordinateur (TCAO),la modélisation compacte et l'extraction des paramètres.Afin de créer une base pour l'environnement de simulation et d'améliorerla confirmabilité pour les lecteurs, les modèles de matériaux utilisés pour lesapproches hydrodynamiques et de diffusion par conduction sont introduits dèsle début de la thèse. Les modèles physiques sont principalement fondés surdes données de la littérature basées sur simulations Monte Carlo (MC) ou dessimulations déterministes de l'équation de transport de Boltzmann (BTE).Néanmoins, le module de TCAO doit être aussi étalonné sur les données demesure pour une prévision fiable des performances des HBTs. L'approchecorrespondante d'étalonnage est basée sur les mesures d'une technologie depointe de HBT SiGe pour laquelle un ensemble de paramètres spécifiques àla technologie du modèle compact HICUM/L2 est extrait pour les versionsdu transistor à haute vitesse, moyenne et haute tension. En s'aidant de cesrésultats, les caractéristiques du transistor unidimensionnel qui sont généréesservent de référence pour le profil de dopage et l'étalonnage du modèle. Enélaborant des comparaisons entre les données de références basées sur les mesureset les simulations, la thèse fait progresser l'état actuel des prévisionsbasées sur la technologie CAO et démontre la faisabilité de l'approche.Enfin, une technologie future de 28nm performante est prédite en appliquantla méthodologie hétérogène. Sur la base des résultats de TCAO, leslimites de la technologie sont soulignées. / Bipolar complementary metal-oxide-semiconductor (BiCMOS) processescan be considered as the most general solution for RF products, as theycombine the mature manufacturing tools of CMOS with the speed and drivecapabilities of silicon-germanium (SiGe) heterojunction bipolar transistors(HBTs). HBTs in turn are major contenders for partially filling the terahertzgap, which describes the range in which the frequencies generated bytransistors and lasers do not overlap (approximately 0.3THz to 30 THz). Toevaluate the capabilities of such future devices, a reliable prediction methodologyis desirable. Using a heterogeneous set of simulation tools and approachesallows to achieve this goal successively and is beneficial for troubleshooting.Various scientific fields are combined, such as technology computer-aided design(TCAD), compact modeling and parameter extraction.To create a foundation for the simulation environment and to ensure reproducibility,the used material models of the hydrodynamic and drift-diffusionapproaches are introduced in the beginning of this thesis. The physical modelsare mainly based on literature data of Monte Carlo (MC) or deterministicsimulations of the Boltzmann transport equation (BTE). However, the TCADdeck must be calibrated on measurement data too for a reliable performanceprediction of HBTs. The corresponding calibration approach is based onmeasurements of an advanced SiGe HBT technology for which a technology specific parameter set of the HICUM/L2 compact model is extracted for thehigh-speed, medium-voltage and high-voltage transistor versions. With thehelp of the results, one-dimensional transistor characteristics are generatedthat serve as reference for the doping profile and model calibration. By performingelaborate comparisons between measurement-based reference dataand simulations, the thesis advances the state-of-the-art of TCAD-based predictionsand proofs the feasibility of the approach.Finally, the performance of a future technology in 28nm is predicted byapplying the heterogeneous methodology. On the basis of the TCAD results,bottlenecks of the technology are identified. / Bipolare komplementäre Metall-Oxid-Halbleiter (BiCMOS) Prozesse bietenhervorragende Rahmenbedingungen um Hochfrequenzanwendungen zurealisieren, da sie die fortschrittliche Fertigungstechnik von CMOS mit derGeschwindigkeit und Treiberleistung von Silizium-Germanium (SiGe) Heterostruktur-Bipolartransistoren (HBTs) verknüpfen. Zudem sind HBTs bedeutendeWettbewerber für die teilweise Überbrückung der Terahertz-Lücke, derFrequenzbereich zwischen Transistoren (< 0.3 THz) und Lasern (> 30 THz).Um die Leistungsfähigkeit solcher zukünftigen Bauelemente zu bewerten, isteine zuverlässige Methodologie zur Vorhersage notwendig. Die Verwendungeiner heterogenen Zusammenstellung von Simulationstools und Lösungsansätzenerlaubt es dieses Ziel schrittweise zu erreichen und erleichtert die Fehler-_ndung. Verschiedene wissenschaftliche Bereiche werden kombiniert, wie zumBeispiel der rechnergestützte Entwurf für Technologie (TCAD), die Kompaktmodellierungund Parameterextraktion.Die verwendeten Modelle des hydrodynamischen Simulationsansatzes werdenzu Beginn der Arbeit vorgestellt, um die Simulationseinstellung zu erläuternund somit die Nachvollziehbarkeit für den Leser zu verbessern. Die physikalischenModelle basieren hauptsächlich auf Literaturdaten von Monte Carlo(MC) oder deterministischen Simulationen der Boltzmann-Transportgleichung(BTE). Für eine zuverlässige Vorhersage der Eigenschaften von HBTs muss dieTCAD Kon_guration jedoch zusätzlich auf der Grundlage von Messdaten kalibriertwerden. Der zugehörige Ansatz zur Kalibrierung beruht auf Messungeneiner fortschrittlichen SiGe HBT Technologie, für welche ein technologiespezifischer HICUM/L2 Parametersatz für die high-speed, medium-voltage undhigh-voltage Transistoren extrahiert wird. Mit diesen Ergebnissen werden eindimensionaleTransistorcharakteristiken generiert, die als Referenzdaten fürdie Kalibrierung von Dotierungspro_len und physikalischer Modelle genutztwerden. Der ausführliche Vergleich dieser Referenz- und Messdaten mit Simulationengeht über den Stand der Technik TCAD-basierender Vorhersagenhinaus und weist die Machbarkeit des heterogenen Ansatzes nach.Schlieÿlich wird die Leistungsfähigkeit einer zukünftigen Technologie in28nm unter Anwendung der heterogenen Methodik vorhergesagt. Anhand derTCAD Ergebnisse wird auf Engpässe der Technologie hingewiesen.