In the present work, the plasma repair for damaged ultra-low-k (ULK) materials, newly developed at the Fraunhofer ENAS, is studied with density functional theory (DFT) and molecular dynamic (MD) methods to obtain new insights into this repair mechanism. The ULK materials owe their low dielectric constant (k-value) to the insertion of k-value lowering methyl groups. During the manufacturing process, the ULK materials are damaged and their k-values increase due to the adsorbtion of hydroxyl groups (OH-damage) and hydrogen atoms (H-damage) that replaced themethyl groups. The first investigation point is the creation of repair fragments. For this purpose the silylation molecules bis(dimethylamino)-dimethylsilane (DMADMS) and octamethylcyclotetrasiloxane (OMCTS) are fragmented. Here, only fragmentation reactions that lead to repair fragments that contain one silicon atom and at least one methyl group were considered. It is shown that the repair fragments that contain three methyl groups are preferred, especially in a methyl rich atmosphere. The effectivity of the obtained repair fragments to cure an OH- and H-damage are investigated with two model systems. The first system consists of an assortment of small ULK-fragments, which is used to scan through the wide array of possible repair reactions. The second system is a silicon oxide cluster that investigates whether the presence of a cluster influences the reaction energies. In both model systems, repair fragments that contain three methyl groups or two oxygen atoms are found to be most effective. Finally, the quantum chemical results are compared to experimental findings to get deeper insight into the repair process.

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.

No description available.

The ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated circuit (ULSI) devices. In order to reduce the time delay, it is necessary to introduce a wiring metal with low resistivity and a high quality insulating film with a low dielectric constant which leads to a reduction of the wiring capacitance. Boron carbon nitride (BCN) films are prepared by reactive magnetron sputtering from a B4C target and deposited to make metal-insulator-metal (MIM) sandwich structures using aluminum as the top and bottom electrodes. BCN films are deposited at various N2/Ar gas flow ratios, substrate temperatures and process pressures. The electrical characterization of the MIM devices includes capacitance vs. voltage (C-V), current vs voltage, and breakdown voltage characteristics. The above characterizations are performed as a function of deposition parameters.

Printed circuit board manufacturing involves subtractive copper (Cu) etching where fine features are developed with a specific spatial resolution and etch profile of the Cu interconnects. A UV-Vis ATR metrology, to characterize the chemical transitions, has been developed to monitor the state of the bath by an in-situ measurement. This method provides a direct correlation of the Cu etch bath and was able to predict a 35% lower etch rate that was not predicted by the three current monitoring methods (ORP, specific gravity, and conductivity). Application of this UV-Vis ATR probe confirmed that two industrial etch baths, in identical working conditions, confirmed a difference in Cu2+ concentration by the difference of the near IR 860nm peak. The scope of this probe allowed chemically specific monitoring of the Cu etch bath to achieve a successful regeneration for repeated use. Interlayer dielectrics (ILDs) provide mechanical and electrical stability to the 3D electrical interconnects found in IC devices. It is particularly important that the structural support is created properly in the multilayered architecture to prevent the electrical cross signaling in short range distances. A combined multiple internal reflection and transmission FTIR has been employed for the characterization of silicon oxycarbonitride (SiOCN) films. These dielectric low-k films incorporate various functional groups bonded to silicon and require chemical bonding insight in the transformation and curing process. Distinct SiOx bonding patterns were differentiated, and the structure of the films can be predicted based on the amount of Si network and caged species. Further optimization of the FTIR analysis must minimize interference from moisture that can impact the judgement of peak heights. To accommodate this, a high-quality glove box was designed for dry air feedthrough to achieve a 95% moisture reduction during analysis, where less than 0.1 mAbs of moisture is detected in the spectra (without additional correction). The glove box allows for the rapid analysis of multiple sample throughput to outpace alternative characterization methods while retaining low spectral noise and a dry environment for 24/7 analysis. There is a great need to identify new catalysts that are suitable for tackling current economic demands, one of which is the nitrogen reduction reaction (NRR). The development of the surface enhanced infrared absorption spectroscopy (SEIRAS) has been applied to characterize the NRR mechanisms on the vanadium oxynitride electrocatalyst. Electrochemical measurements demonstrate NRR activity that is up to three times greater in the presence of N2 than the control Ar. FTIR operando suggests that a considerable number of intermediates were formed and continued to increase in absorbing value under an applied potential of -0.8 V vs Ag/AgCl. XPS results of the post-NRR film suggest a restricting of the film where vanadium oxynitride films are prone to instabilities under the possible MvK mechanism. After 90 minutes of NRR, the NH3 generated was approximately 0.01 ppm was calculated for through the salicylate colorimetric method. On-going efforts are focusing on optimizing the vanadium oxynitride film by the tuning of the oxynitride ratios and crystalline properties to promote the formation of V≡N: during the nitrogen reduction reaction.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.

Résumé: Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al[indice inférieur 2]O[indice inférieur 3], H[florin]O[indice inférieur 2] et TiO[indice inférieur 2]) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les Matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Abstract: Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al[subscript 2]O[subscript 3], H[florin]O[subscript 2] and TiO[subscript 2]), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to démonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al2O3, HfO2 et TiO2) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al2O3, HfO2 and TiO2), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to demonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

In multi-level Co/low-k based interconnect systems of ultralarge-scale integrated electronic devices the removal of plasma etch residues by common plasma cleaning processes has been shown to alter material properties like k-value and leakage current of the low-k dielectric. Besides the development of less damaging plasma processes their substitution by wet cleaning steps is in the focus of research and development. With further decreasing feature dimensions the development of wet cleaning processes has to include wetting issues like the non-wetting of small features due to the surface energy of the liquid or pattern collapse effects of low-k dielectric trenches due to high capillary forces This work at first focuses on the determination of the surface energetic character of common cleaning solutions for PERR and differently etched or ashed low-k dielectric surfaces by contact angle analysis, to outline which combinations of solid and liquid will be critical regarding their wetting behavior. Besides the determination of the wetting behavior the contact angle analysis turned out to be a fast and sensible analytic tool to understand the surface modifications introduced by different plasma processes and can help to understand the mechanisms of plasma damage of low-k dielectric surfaces. The analysis showed that especially polymerizing plasma etch processes produce a low-energetic low-k dielectric surface with a negligible polar energy contributions, which inhibits their wetting by high energetic water based cleaning solutions, which actually are favored by semiconductor manufacturers. The strategy to overcome these wetting issues followed in the present work is the reduction of the surface energy of the cleaning liquids by the application of surfactants. Several types of surfactants have been applied to the cleaning liquids and the compatibility of the surfactant solutions to BEOL materials like low-k dielectrics, copper and diffusion barriers as well as their dynamic behavior has been studied. The analysis showed that choosing the appropriate rinsing solution after the cleaning process is essential to ensure its compatibility to porous low-k dielectrics. Optical, electrical and structural data indicated that DIW rinse in most of the cases was not able to remove residual surfactant species within the material, while for an IPA rinse most of the residual surfactants have been removed. Considering the data received for compatibility to low-k materials, copper and barriers, the dynamic behavior of the surfactant solutions as well as influences of increased bath temperature and long term stability a general advice about surfactant selection and processing of surfactant aided solutions within BEOL is given. / In mehrlagigen Kupfer/low-k basierten Metallisierungssystemen hochintegrierter elektronischer Bauelemente kann die Entfernung von Residuen nach der Plasmastrukturierung des Dielektrikums mittels herkömmlicher Plasmareinigungsprozesse zur Schädigung der Isolatorschicht und damit zum Ansteigen der relativen Dielektrizitätszahl sowie der Leckströme führen. Neben der Entwicklung schädigungsarmer Plasmaprozesse stellt der Ersatz dieser Prozesse durch Nassreinigungsschritte zur Ätzresiduenentfernung eine vielversprechende Alternative dar. Mit stetig abnehmenden Strukturabmaßen ist bei der Entwicklung dieser Nassreinigungsprozesse neben der Materialkompatibilität auch das Benetzungsverhalten der Reinigungsflüssigkeit von entscheidender Bedeutung, da die Oberflächenenergie der Reinigungslösung das Eindringen dieser in kleinste Strukturen verhindern und es durch hohe Kapillarkräfte zum Kollaps von Grabenstrukturen im Dielektrikum kommen kann. In der vorliegenden Arbeit wurde zunächst mittels Kontaktwinkelanalyse die Oberflächenenergie verschieden prozessierter low-k Dielektrikaschichten sowie herkömmlicher Lösungen zur Entfernung von Ätzresiduen untersucht, um hinsichtlich ihres Benetzungsverhaltens besonders kritische Materialkombinationen aufzuzeigen. Neben der Bestimmung des Benetzungsverhaltens hat sich die Kontaktwinkelanalyse zur Oberflächenenergieberechnung als schnelle und empfindliche Methode zur Analyse der Auswirkung von Plasmaprozessen auf die Oberfläche von low-k Dielektrika erwiesen. Die Untersuchungen haben gezeigt, dass besonders polymerisierende Plasmaprozesse eine niederenergetische Oberfläche erzeugen, welche von den derzeit in der Halbleiterfertigung bevorzugten hochenergetischen wasserbasierten Reinigungslösungen nur schlecht benetzt wird. Um diesem Effekt entgegenzuwirken wurde in der vorliegenden Arbeit die Senkung der Oberflächenenergie der Reinigungslösungen durch Zugabe von Tensiden untersucht. Es wurden mehrere Tenside unterschiedlichen Typs den Reinigungsflüssigkeiten zugemischt und die Kompatibilität dieser Lösungen mit low-k Dielektrika, Kupferschichten und Diffusionsbarrieren untersucht sowie ihr dynamisches Verhalten analysiert. Dabei hat sich gezeigt, dass die Auswahl der geeigneten Spüllösung nach dem eigentlichen Reinigungsprozess von entscheidender Bedeutung ist. Optische, elektrische sowie strukturelle Daten deuten darauf hin, dass bei Verwendung einer Spülung mit deionisiertem Wasser in den meisten Fällen Tensidrückstände im porösen Dielektrikum verbleiben. Eine Spülung mit Isopropanol war hingegen in der Lage, einen Großteil dieser Tensidrückstände zu entfernen. Unter Einbeziehung der Daten zur Materialkompatibilität und dem dynamischen Verhalten der Tensidlösungen bei Raumtemperatur und erhöhter Badtemperatur sowie ihrer Langzeitstabilität konnte schließlich eine Prozessempfehlung für die Verwendung der benetzungsoptimierten Reinigungslösungen in der BEOL-Prozessierung gefunden werden.

In multi-level Co/low-k based interconnect systems of ultralarge-scale integrated electronic devices the removal of plasma etch residues by common plasma cleaning processes has been shown to alter material properties like k-value and leakage current of the low-k dielectric. Besides the development of less damaging plasma processes their substitution by wet cleaning steps is in the focus of research and development. With further decreasing feature dimensions the development of wet cleaning processes has to include wetting issues like the non-wetting of small features due to the surface energy of the liquid or pattern collapse effects of low-k dielectric trenches due to high capillary forces This work at first focuses on the determination of the surface energetic character of common cleaning solutions for PERR and differently etched or ashed low-k dielectric surfaces by contact angle analysis, to outline which combinations of solid and liquid will be critical regarding their wetting behavior. Besides the determination of the wetting behavior the contact angle analysis turned out to be a fast and sensible analytic tool to understand the surface modifications introduced by different plasma processes and can help to understand the mechanisms of plasma damage of low-k dielectric surfaces. The analysis showed that especially polymerizing plasma etch processes produce a low-energetic low-k dielectric surface with a negligible polar energy contributions, which inhibits their wetting by high energetic water based cleaning solutions, which actually are favored by semiconductor manufacturers. The strategy to overcome these wetting issues followed in the present work is the reduction of the surface energy of the cleaning liquids by the application of surfactants. Several types of surfactants have been applied to the cleaning liquids and the compatibility of the surfactant solutions to BEOL materials like low-k dielectrics, copper and diffusion barriers as well as their dynamic behavior has been studied. The analysis showed that choosing the appropriate rinsing solution after the cleaning process is essential to ensure its compatibility to porous low-k dielectrics. Optical, electrical and structural data indicated that DIW rinse in most of the cases was not able to remove residual surfactant species within the material, while for an IPA rinse most of the residual surfactants have been removed. Considering the data received for compatibility to low-k materials, copper and barriers, the dynamic behavior of the surfactant solutions as well as influences of increased bath temperature and long term stability a general advice about surfactant selection and processing of surfactant aided solutions within BEOL is given. / In mehrlagigen Kupfer/low-k basierten Metallisierungssystemen hochintegrierter elektronischer Bauelemente kann die Entfernung von Residuen nach der Plasmastrukturierung des Dielektrikums mittels herkömmlicher Plasmareinigungsprozesse zur Schädigung der Isolatorschicht und damit zum Ansteigen der relativen Dielektrizitätszahl sowie der Leckströme führen. Neben der Entwicklung schädigungsarmer Plasmaprozesse stellt der Ersatz dieser Prozesse durch Nassreinigungsschritte zur Ätzresiduenentfernung eine vielversprechende Alternative dar. Mit stetig abnehmenden Strukturabmaßen ist bei der Entwicklung dieser Nassreinigungsprozesse neben der Materialkompatibilität auch das Benetzungsverhalten der Reinigungsflüssigkeit von entscheidender Bedeutung, da die Oberflächenenergie der Reinigungslösung das Eindringen dieser in kleinste Strukturen verhindern und es durch hohe Kapillarkräfte zum Kollaps von Grabenstrukturen im Dielektrikum kommen kann. In der vorliegenden Arbeit wurde zunächst mittels Kontaktwinkelanalyse die Oberflächenenergie verschieden prozessierter low-k Dielektrikaschichten sowie herkömmlicher Lösungen zur Entfernung von Ätzresiduen untersucht, um hinsichtlich ihres Benetzungsverhaltens besonders kritische Materialkombinationen aufzuzeigen. Neben der Bestimmung des Benetzungsverhaltens hat sich die Kontaktwinkelanalyse zur Oberflächenenergieberechnung als schnelle und empfindliche Methode zur Analyse der Auswirkung von Plasmaprozessen auf die Oberfläche von low-k Dielektrika erwiesen. Die Untersuchungen haben gezeigt, dass besonders polymerisierende Plasmaprozesse eine niederenergetische Oberfläche erzeugen, welche von den derzeit in der Halbleiterfertigung bevorzugten hochenergetischen wasserbasierten Reinigungslösungen nur schlecht benetzt wird. Um diesem Effekt entgegenzuwirken wurde in der vorliegenden Arbeit die Senkung der Oberflächenenergie der Reinigungslösungen durch Zugabe von Tensiden untersucht. Es wurden mehrere Tenside unterschiedlichen Typs den Reinigungsflüssigkeiten zugemischt und die Kompatibilität dieser Lösungen mit low-k Dielektrika, Kupferschichten und Diffusionsbarrieren untersucht sowie ihr dynamisches Verhalten analysiert. Dabei hat sich gezeigt, dass die Auswahl der geeigneten Spüllösung nach dem eigentlichen Reinigungsprozess von entscheidender Bedeutung ist. Optische, elektrische sowie strukturelle Daten deuten darauf hin, dass bei Verwendung einer Spülung mit deionisiertem Wasser in den meisten Fällen Tensidrückstände im porösen Dielektrikum verbleiben. Eine Spülung mit Isopropanol war hingegen in der Lage, einen Großteil dieser Tensidrückstände zu entfernen. Unter Einbeziehung der Daten zur Materialkompatibilität und dem dynamischen Verhalten der Tensidlösungen bei Raumtemperatur und erhöhter Badtemperatur sowie ihrer Langzeitstabilität konnte schließlich eine Prozessempfehlung für die Verwendung der benetzungsoptimierten Reinigungslösungen in der BEOL-Prozessierung gefunden werden.