A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

Voltage source inverter (VSI) fed induction motors are increasingly used in industrial and transportation applications as variable speed drives. However, VSIs generate non-sinusoidal voltages and hence result in harmonic distortion in motor current, motor heating, torque pulsations and increased acoustic noise. Most of these undesirable effects can be reduced by increasing the switching frequency of the inverter. This is not necessarily true for acoustic noise. Acoustic noise does not decrease monotonically with increase in switching frequency since the noise emitted depends on the proximity of harmonic frequencies to the motor resonant frequencies. Also there are practical limitations on the inverter switching frequency on account of device rating and losses. The switching frequency of many inverters often falls in the range 2 kHz - 6 kHz where the human ear is highly sensitive. Hence, the acoustic noise emission from the motor drive is of utmost important. Further, the acoustic noise emitted by the motor drive is known to depend on the waveform quality of the voltage applied. Hence, the acoustic performance varies with the pulse width modulation (PWM) technique used to modulate the inverter, even at the same modulation index. Therefore a comprehensive study on the acoustic noise aspects of induction motor drive is required. The acoustic noise study of the motor drive poses multifaceted challenges. A simple motor model is sufficient for calculation of total harmonic distortion (THD). A more detailed model is required for torque pulsation studies. But the motor acoustic noise is affected by many other factors such as stator winding distribution, space harmonics, geometry of stator and rotor slots, motor irregularities, structural issues controlling the resonant frequency and environmental factors. Hence an accurate model for acoustic noise would have to be very detailed and would span different domains such as electromagnetic fields, structural engineering, vibration and acoustics. Motor designers employ such detailed models along with details of the materials used and geometry to predict the acoustic noise that would be emitted by a motor and also to design a low-noise motor. However such detailed motor model for acoustic noise purposes and the necessary material and constructional details of the motor are usually not available to the user. Also, certain factors influencing the acoustic noise change due to wear and tear during the operational life of the motor. Hence this thesis takes up an experimental approach to study the acoustic noise performance of an inverter-fed induction motor at any stage of its operating life. A 10 kVA insulated gate bipolar transistor (IGBT) based inverter is built to feed the induction motor; a 6 kW and 2.3 kW induction motors are used as experimental motors. A low-cost acoustic noise measurement system is also developed as per relevant standards for measurement and spectral analysis of the acoustic noise emitted. For each PWM scheme, the current and acoustic noise measurements are carried out extensively at different carrier frequencies over a range of fundamental frequencies. The main cause of acoustic noise of electromagnetic origin is the stator core vibration, which is caused by the interaction of air-gap fluxes produced by fundamental current and harmonic currents. In this thesis, an experimental procedure is suggested for the acoustic noise characterization of an induction motor inclusive of determination of resonant frequencies. Further, based on current and acoustic noise measurements, a vibration model is proposed for the stator structure. This model is used to predict the acoustic noise pertaining to time harmonic currents with reasonable accuracy. Literature on motor acoustic noise mainly focuses on sinusoidal PWM (SPWM), conventional space vector PWM (CSVPWM) and random PWM (RPWM). In this thesis, acoustic noise pertaining to two bus-clamping PWM (BCPWM) schemes and an advanced bus-clamping PWM (ABCPWM) scheme is investigated. BCPWM schemes are mainly used to reduce the switching loss of the inverter by clamping any of the three phases to DC rail for 120◦ duration of the fundamental cycle. Experimental results show that these BCPWM schemes reduce the amplitude of the tonal component of noise at the carrier frequency, compared to CSVPWM. Experimental results with ABCPWM show that the overall acoustic noise produced by the motor drive is reduced at low and medium speeds if the switching frequency is above 3 kHz. Certain spread in the frequency spectrum of noise is also seen with both BCPWM and ABCPWM. To spread the acoustic noise spectrum further, many variable-frequency PWM schemes have been suggested by researchers. But these schemes, by and large, increase the current total harmonic distortion (THD) compared to CSVPWM. Thus, a novel variable-frequency PWM (VFPWM) method is proposed, which offers reduced current THD in addition to uniformly spread noise spectrum. Experimental results also show spread in the acoustic noise spectrum and reduction in the dominant noise components with the proposed VFPWM. Also, the current THD is reduced at high speeds of the motor drive with the proposed method.

No description available.

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

Je jasné, že nejúspěšnější konstrukce zahrnuje postup vícefázového řízení, ve kterém každá fáze může být považována za samostatný modul. Provoz kterékoliv z jednotek musí mít minimální vliv na ostatní, a to tak, že v případě selhání jedné jednotky ostatní mohou být v provozu neovlivněny. Modulární řešení vyžaduje minimální elektrické, magnetické a tepelné ovlivnění mezi fázemi řízení (měniče). Synchronní stroje s pulzním tokem a permanentními magnety se jeví jako atraktivní typ stroje, jejíž přednostmi jsou vysoký kroutící moment, jednoduchá a robustní konstrukce rotoru a skutečnost, že permanentní magnety i cívky jsou umístěny společně na statoru. FS-PMSM jsou poměrně nové typy střídavého stroje stator-permanentní magnet, které představují významné přednosti na rozdíl od konvenčních rotorů - velký kroutící moment, vysoký točivý moment, v podstatě sinusové zpětné EMF křivky, zároveň kompaktní a robustní konstrukce díky umístění magnetů a vinutí kotvy na statoru. Srovnání výsledků mezi FS-PMSM a klasickými motory na povrchu upevněnými PM (SPM) se stejnými parametry ukazuje, že FS-PMSM vykazuje větší vzduchové mezery hustoty toku, vyšší točivý moment na ztráty v mědi, ale také vyšší pulzaci díky reluktančnímu momentu. Pro stroje buzené permanentními magnety se jedná o tradiční rozpor mezi požadavkem na vysoký kroutící moment pod základní rychlostí (oblast konstantního momentu) a provozem nad základní rychlostí (oblast konstantního výkonu), zejména pro aplikace v hybridních vozidlech. Je předložena nová topologie synchronního stroje s permanentními magnety a spínaným tokem odolného proti poruchám, která je schopná provozu během vinutí naprázdno a zkratovaného vinutí i poruchách měniče. Schéma je založeno na dvojitě vinutém motoru napájeném ze dvou oddělených vektorově řízených napěťových zdrojů. Vinutí jsou uspořádána takovým způsobem, aby tvořila dvě nezávislé a oddělené sady. Simulace a experimentální výzkum zpřesní výkon během obou scénářů jak za normálního provozu, tak za poruch včetně zkratových závad a ukáží robustnost pohonu za těchto podmínek. Tato práce byla publikována v deseti konferenčních příspěvcích, dvou časopisech a knižní kapitole, kde byly představeny jak topologie pohonu a aplikovaná řídící schémata, tak analýzy jeho schopnosti odolávat poruchám.