Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

This thesis focuses on the design and analysis of a novel variable inductor (VID) based VCO solution to the frequency tuning range (TR) limitation of the IEEE 802.11ad compliant radio systems. The IEEE 802.11ad standard has drawn strong attention from the industry as the next generation affordable multi-gigabit speed wireless communication standard. Prepared for the global market, IEEE 802.11ad compliant systems are required to cover a broad 8 GHz TR centered on 60 GHz. This wide TR at V band imposes significant challenge to the VCO design in radio transceivers, and makes the TR of the integrated VCO a major bottleneck to the successful commercialization of many IEEE 802.11ad compliant radio systems today. As an effort to solve the current TR problem for the IEEE 802.11ad compliant radio systems, 2 VCOs designs based on this novel VID-based solution and a conventional Colpitts-Clapp VCO design are presented in this thesis report. The novel VCOs integrate a VID into the differential Colpitts configuration to create a feasible solution to the aforementioned TR problem. The VID in the VCO tank eliminates the base node varactors and their fixed parasitic capacitance that degrades TR in conventional VCO designs, while the differential Colpitts configuration provides advantageous performance at mm-wave frequencies and high output power for real-world applications. Also, a fundamental 30 GHz Colpitts-Clapp VCO was developed in conjunction with the other 2 VCOs for comparison purposes. One of the 2 VID-based VCO designs is a fundamental 30 GHz VID-based Colpitts VCO that covers 17% TR for proof of concept to the novel topology. Another is an IEEE 802.11ad compliant 60 GHz VCO chain consists of the 30 GHz VID-based Colpitts VCO and a frequency doubler covering 17% TR with 3 dBm output power and -115.7 dBc/Hz phase noise at 10 MHz offset. The conventional Colpitts-Clapp VCO is used to compare with the other 2 VID-based VCOs. As the measurement results indicate, this VID-based VCO topology provides a viable solution to overcome the TR bottleneck in the current IEEE 802.11ad compliant VCO development. All 3 VCOs are fabricated using a 130 nm SiGe BiCMOS process. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2014-01-23 13:40:31.258

Der thermische Widerstand ist eine wichtige Kenngröße von Silicium-Germanium-Hetero-Bipolartransistoren (SiGe-HBTs). Bisher kam es bei der quantitativen Bestimmung der thermischen Widerstände von SiGe-HBTs zu deutlichen Abweichungen zwischen Simulation und Messung. Der Unterschied zwischen Simulation und Messung betrug bei den untersuchten HBTs mehr als 30 Prozent. Diese Arbeit widmet sich der Aufklärung und Beseitigung der möglichen Ursachen hierfür. Zu diesem Zweck werden als erstes die Messmethoden analysiert. Es zeigt sich, dass die bisher verwendete Extraktionsmethode sensitiv auf den Early-Effekt (Basisweitenmodulation) reagiert. Im Rahmen der Untersuchungen wurde ein neues Extraktionsverfahren entwickelt. Die neue Extraktions­methode ist unempfindlich gegenüber dem Early-Effekt. Mit Bauelemente­simulationen wird erstmalig die Wirkung des Seebeck-Effektes (Thermospannungen) auf die elektrisch extrahierten thermischen Widerstände demonstriert. Der Seebeck-Effekt bewirkt, dass die elektrisch extrahierten thermischen Widerstände der untersuchten HBTs nahezu 10 Prozent kleiner als die erwarteten Werte sind. Dieser Effekt wurde bisher nicht beachtet und wird hier erstmals nachgewiesen. Weiterhin wird die Abhängigkeit des thermischen Widerstandes vom Arbeitspunkt untersucht. Dabei hat sich gezeigt, dass bis zu einer Basis-Emitter-Spannung von 0,91 Volt die geometrische Form des Wärme abgebenden Gebietes unabhängig vom Arbeitspunkt ist. Anhand von Messungen wird gezeigt, dass die Dotierung die spezifische Wärmeleitfähigkeit von Silicium reduziert. Die Abnahme wird für Dotierungen größer als 1*1019 cm‑3 deutlich sichtbar. Ist die Dotierung größer als 1*1020 cm‑3, beträgt die Abnahme der spezifischen Wärmeleitfähigkeit mehr als 75 Prozent. Mithilfe einer Simulatorkalibrierung wird die spezifische Wärmeleitfähigkeit als Funktion der Dotierung bestimmt. Die erhaltene Funktion kann künftig beim thermischen Entwurf von HBTs verwendet werden. Somit können zukünftig genauere Vorhersagen zum thermischen Widerstand der HBTs gemacht werden. Dies ermöglicht zuverlässigere Aussagen darüber, wie Änderungen des Transistordesigns zur Minimierung des thermischen Widerstandes beitragen. / The thermal resistance is an important parameter of silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Until now, the quantitative determination of the thermal resistance showed significant differences between measurements and simulations. The difference between simulation and measurement of the investigated HBTs was more than 30 percent. This thesis devotes the clarification and elimination of potential sources for it. For this purpose, the measurement methods are analyzed at first. It is shown, that the currently used extraction method is sensitive to the Early effect (basewidth modulation). A now extraction method was developed, which is not sensitive to the Early effect. For the first time, the influence of the Seebeck effect (thermoelectric voltages) on the electrically extracted thermal resistance is shown by device simulations. The Seebeck effect leads to a 10 percent lower extracted thermal resistances compared to the expected values of the investigated HBTs. This effect was not taken into account up to now and is demonstrated here for the first time. Furthermore, the dependence of the thermal resistance on the operating point was investigated. The results show that the shape of the heat source is independent of the operating point if the base emitter voltage is smaller than 0.91 volt. The thermal conductivity of silicon is decreased by increasing doping concentrations. This is shown by measurements. The reduction of the thermal conductivity is well observable for doping concentrations higher than 1*1019 cm‑3. For doping concentration higher than 1*1020 cm‑3 the reduction amounts to more than 75 percent. The thermal conductivity was determined as a function of the doping concentration with the aid of a simulator calibration. This function can be used in the future thermal design of HBTs. It facilitates the optimization of the HBTs with respect to a minimal thermal resistance.

The physics and technology of the heterojunction infrared photodetectors having different material systems have been studied extensively. Devices used in this study have been characterized by using mainly optical methods, and electrical measurements have been used as an auxiliary method. The theory of internal photoemission in semiconductor heterojunctions has been investigated and the existing model has been extended by incorporating the effects of the difference in the effective masses in the active region and the substrate, nonspherical-nonparabolic bands, and the energy loss per collisions. The barrier heights (correspondingly the cut-off wavelengths) of SiGe/Si samples have been found from their internal photoemission spectrums by using the complete model which has the wavelength and doping concentration dependent free carrier absorption parameters. A qualitative model describing the mechanisms of photocurrent generation in SiGe/Si HIP devices has been presented. It has been shown that the performance of our devices depends significantly on the applied bias and the operating temperature. Properties of internal photoemission in a PtSi/Si Schottky type infrared detector have also been studied. InGaAs/InP quantum well photodetectors that covers both near and mid-infrared spectral regions by means of interband and intersubband transitions have been studied. To understand the high responsivity values observed at high biases, the gain and avalanche multiplication processes have been investigated. Finally, the results of a detailed characterization study on a systematic set of InAs/GaAs self-assembled quantum dot infrared photodetectors have been presented. A simple physical picture has also been discussed to account for the main observed features.

Millimeter-wave has been a medium for automotive, sensor, and defense applications for a long time. But, a fully integrated silicon-based transceiver at 60 GHz or higher frequencies has become the driving force for recent research activities in integrated millimeter-wave (MMW) circuit designs. However, no integrated compact high-performance millimeter-wave system can be designed without accurate estimation and optimization of layout parasitics. In this dissertation, the estimation, modeling and optimization of parasitic effects as well as the verification of extraction methodologies for RF/MMW applications are investigated. Different circuit design- and layout-examples are considered with stress on the inclusion and optimization of wire/interconnect parasitics. A novel methodology is proposed to reduce the number of design-passes and to include layout parasitics in the design optimization procedure. An automated verification procedure for existing parasitic extraction tools is developed. Neural-network-based models are used to demonstrate the effectiveness of artificial intelligence techniques for characterizing parasitic components. The parasitic sensitivities for selected millimeter-wave circuits are demonstrated, and a parasitic benchmarking procedure is developed using MMW oscillators. Measurement results of several circuits that are implemented in state-of-the-art CMOS and SiGe-BiCMOS processes are used to demonstrate the role of parasitics and the systematic design methodology including parasitics.

A caracterização do strain (deformação) em estruturas cristalinas em filmes finos semicondutores apresenta importantes aplicações tecnológicas, como por exemplo: a formação de defeitos, modificação da estrutura das bandas de condução e valência, e consequentemente modificando a mobilidade de portadores no material. Técnicas de espalhamento com íons de H e He têm sido amplamente empregadas para determinar a deformação, visto que mudanças na canalização ou nas direções de bloqueio podem ser facilmente relacionadas com as deformações no parâmetro de rede. Um novo método, chamado de cartografia-MEIS, é utilizado para determinar a intensidade da deformação estrutural em uma rede cristalográfica. A partir desta técnica, a projeção estereográfica de um único cristal pode ser medida com uma técnica MEIS padrão para um determinado elemento atômico e determinada profundidade. Aqui demonstramos que esta técnica pode ser expandida para caracterizar heteroestruturas SiGe tensas com alta precisão. Em nosso método, não só as principais direções cristalinas são analisados, mas também os índices mais elevados. O método também proporciona sensibilidade elementar com resolução de profundidade e pode ser utilizado em materiais nanoestruturados. A determinação da deformação baseia-se na posição das muitas linhas de bloqueio, ao contrário dos métodos tradicionais, onde duas direções são utilizados. Nós também fornecemos um método para determinar o melhor ajuste nos dados para a deformação na rede, verificando estes resultados a partir de simulações de Monte-Carlo. / The characterization of the strain in the crystal structures of thin semiconductor films has important technological applications such as, for example, the formation of defects, changes in the structure of the conduction and valence bands, and therefore modifying the mobility of carriers in the material. Scattering techniques with H and He ions have been widely used to determine the deformation, as changes in drains or the blocking directions can be easily related to the deformation of the lattice parameter. A new method, called cartography-MEIS, is used to determine the intensity of the structural deformation in a crystallographic structure. From this technique, the stereographic projection of a single crystal can be measured with a standard MEIS technique for a particular atomic element and given depth. Here we demonstrate that this technique can be expanded to characterize strained SiGe heterostructures with high accuracy. In our method, not only the main crystalline directions are analyzed but also the higher index ones. The method also provides elemental sensitivity with depth resolution and can be used in nano-structured materials. The determination of the strain is based on the position of the many blocking lines contrary to the traditional methods where two directions are used. We also provide a method to determine the lattice deformation fitting the data best and checked it against full Monte-Carlo simulations.

A caracterização do strain (deformação) em estruturas cristalinas em filmes finos semicondutores apresenta importantes aplicações tecnológicas, como por exemplo: a formação de defeitos, modificação da estrutura das bandas de condução e valência, e consequentemente modificando a mobilidade de portadores no material. Técnicas de espalhamento com íons de H e He têm sido amplamente empregadas para determinar a deformação, visto que mudanças na canalização ou nas direções de bloqueio podem ser facilmente relacionadas com as deformações no parâmetro de rede. Um novo método, chamado de cartografia-MEIS, é utilizado para determinar a intensidade da deformação estrutural em uma rede cristalográfica. A partir desta técnica, a projeção estereográfica de um único cristal pode ser medida com uma técnica MEIS padrão para um determinado elemento atômico e determinada profundidade. Aqui demonstramos que esta técnica pode ser expandida para caracterizar heteroestruturas SiGe tensas com alta precisão. Em nosso método, não só as principais direções cristalinas são analisados, mas também os índices mais elevados. O método também proporciona sensibilidade elementar com resolução de profundidade e pode ser utilizado em materiais nanoestruturados. A determinação da deformação baseia-se na posição das muitas linhas de bloqueio, ao contrário dos métodos tradicionais, onde duas direções são utilizados. Nós também fornecemos um método para determinar o melhor ajuste nos dados para a deformação na rede, verificando estes resultados a partir de simulações de Monte-Carlo. / The characterization of the strain in the crystal structures of thin semiconductor films has important technological applications such as, for example, the formation of defects, changes in the structure of the conduction and valence bands, and therefore modifying the mobility of carriers in the material. Scattering techniques with H and He ions have been widely used to determine the deformation, as changes in drains or the blocking directions can be easily related to the deformation of the lattice parameter. A new method, called cartography-MEIS, is used to determine the intensity of the structural deformation in a crystallographic structure. From this technique, the stereographic projection of a single crystal can be measured with a standard MEIS technique for a particular atomic element and given depth. Here we demonstrate that this technique can be expanded to characterize strained SiGe heterostructures with high accuracy. In our method, not only the main crystalline directions are analyzed but also the higher index ones. The method also provides elemental sensitivity with depth resolution and can be used in nano-structured materials. The determination of the strain is based on the position of the many blocking lines contrary to the traditional methods where two directions are used. We also provide a method to determine the lattice deformation fitting the data best and checked it against full Monte-Carlo simulations.

Na década de 90, os Sistemas ERP (Enterprise Resource Planning) alcançaram larga utilização, principalmente em empresas de grande porte, devido ao seu elevado custo. Em contrapartida, o interesse por sistemas livres data dos primeiros softwares desenvolvidos para computadores na década de 60 e 70 até os dias atuais com sistemas empresariais como os sistemas ERP. O problema desta pesquisa encontra-se em como adotar, selecionar e implementar um ERP livre. Assim, o objetivo deste trabalho é compreender e avaliar o processo de adoção, seleção e implementação de ERP livre. Para esta finalidade, o trabalho é dividido em duas partes: a parte inicial, baseada na pesquisa bibliográfica, apresenta como 3 capítulos iniciais a Introdução, Fundamentação Teórica e Metodologia. A parte final que apresenta a contribuição desta pesquisa, composta dos capítulos Modelo Inicial, Trabalho de Campo, Modelo Final e Conclusão. As contribuições do trabalho iniciam-se com a proposição pelo autor de um modelo inicial de ciclo de vida de ERP abrangendo estes processos considerando não haver distinções entre o modelo para um ERP proprietário ou livre. Refina-se este modelo inicial através da aplicação do método de pesquisa-ação em um trabalho de campo com a implantação de um ERP livre em uma organização brasileira. Como resultado deste trabalho obteve-se um modelo final de ciclo de vida de ERP independente do mesmo ser desenvolvido na forma de software livre ou proprietário. Identificaram-se também as diferenças nos processos de adoção, seleção e implementação entre ERP proprietário e livre. Encontraram-se conclusões que suportam as empresas a considerar ou não a inclusão do ERP livre nos processos de adoção, seleção e implementação. / In the 90s, the ERP systems (Enterprise Resource Planning) have achieved wide use, especially in large-sized companies because of its high cost. By contrast, interest in free systems date of the first software designed for computers in the 60s and 70s until the present day with enterprise systems such as ERP systems. The problem of this research is on how to adopt, select and implement an ERP free. The objective of this work is to understand and evaluate the process of adoption, selection and implementation of ERP free. To this, work has two parts: the initial part, based on bibliographic research has 3 chapters: initial introduction, theoretical fundaments and methodology. The final part shows the contribution of this research composed of chapters: Initial Model, Work of Field and Final Model. Finally, present the conclusion. The contributions of work begin with the proposition by the author of an original model of the life cycle of ERP covering these processes considering no distinctions between the proprietary and free ERP. Initial model was refined using the method of action research with the adoption, selection and implementation of a free ERP in a Brazilian company. As result of this study, published a final model of the life cycle of ERP independent of development form (free or proprietary). Was identified also the differences between free and proprietary ERP in adoption, selection and implementation process. We found conclusions that support companies to consider whether or not the inclusion of ERP free in cases of adoption, selection and implementation.

L’intégration monolithique d’oxydes ferroélectriques sur substrats semi-conducteurs pourrait permettre l'ajout de nouvelles fonctionnalités sur puces de la nanoélectronique. L'utilisation d'un ferroélectrique est en particulier intéressante pour la réalisation de dispositifs à basse consommation d'énergie. Toutefois, leur intégration se heurte à un certain nombre de verrous scientifiques et technologiques tels que le contrôle de l'interface oxyde/semi-conducteur, l’instabilité de la polarisation ferroélectrique en couches minces ou encore la compatibilité de l'intégration avec les procédés industriels actuels. Les principaux objectifs de ma thèse ont été : l'optimisation de la croissance MBE de BaTiO3 épitaxié sur Si et Si1-xGex en termes de structure cristalline et de propriétés ferroélectriques, l’étude des effets de taille sur la ferroélectricité et le démarrage de l’intégration de BaTiO3 dans des dispositifs à effet de champ. Différentes conditions de croissance sur substrats de silicium, en particulier la température et la pression d'oxygène P(O2), ont été étudiées. Les analyses de diffraction des rayons X (XRD) combinées à des techniques avancées de microscopie électronique en transmission (STEM-HAADF, GPA, EELS) ont permis d'établir une corrélation, à l'échelle locale, entre l'orientation de la maille tétragonale et la composition cationique des films. La ferroélectricité de films orientés axe c, d'épaisseur 16-20 nm, préparés sous des pressions partielles P(O2) de 1-5 x 10-7 Torr, à 450-525°C, et avec un recuit post-dépôt sous oxygène, a été mise en évidence par microscopie à force atomique en mode piézoélectrique (PFM). Nous avons également démontré la ferroélectricité de couches ultra-minces (1.6, 2.0, 2.8, 3.2 et 4.0 nm) par PFM et par des mesures complémentaires de microscopie à force atomique en mode Kelvin (permettant d'exclure un mécanisme d'origine purement électrochimique). Pour 4, 5, 7 et 8 monocouches, l'amplitude de la polarisation pointant vers l'interface supérieure (Pup) est supérieure à celle de la polarisation Pdown. Ceci est attribué à des régions non ferroélectriques ou à des régions polaires dont la polarisation est ancrée aux interfaces. Nous avons ensuite étudié la croissance de BaTiO3 épitaxié sur substrats Si1-xGex, ce qui constitue une approche inédite, particulièrement intéressante pour moduler les contraintes, notamment en vue des futurs transistors. Afin de comprendre l'effet de la présence de Ge, la croissance de BaTiO3 sur Si0.8Ge0.2 contraint sur Si(001) a été étudiée. Le suivi de la croissance in-situ par spectroscopie de photoélectrons X et l’analyse de la structure cristalline et de l’interface par XRD et STEM-HAADF ont révélé l'importance de la préparation du substrat. La passivation de Si0.8Ge0.2 avec des atomes de Ba permet l’épitaxie directe d’un film de BaTiO3 orienté (112), ceci par l'intermédiaire d'une couche d'interface épitaxiée, identifiée comme étant le silicate de structure orthorhombique Ba2SiO4. Ce silicate est épitaxié selon deux orientations dans le plan de Si0.8Ge0.2, ce qui conduit aux deux orientations <110> et <111> observées pour BaTiO3 dans le plan du substrat. Enfin, en collaboration avec IBM Research, une voie d’intégration basse température « gate-last » a été développée pour intégrer les couches minces de BaTiO3 dans des dispositifs à effets de champ sur Si (condensateurs et transistors). Les films de BaTiO3 ont été déposés par MBE sur des substrats pré-structurés. Un procédé approprié a été choisi pour le dépôt de l'électrode TiN et pour la lithographie/gravure. Certains empilements, composés d'une matrice amorphe et de nano-grains dans les structures capacitives, présentent un comportement ferroélectrique (Tc~105°C). Cette première démonstration d’une capacité ferroélectrique de BaTiO3 "quasi-amorphe" sur Si à permittivité relative modérée (~25) et à faible courant de fuite est particulièrement intéressante. [...] / No abstract

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