Low-frequency noise (LFN) is characterized using in-house measurement systems in a variety of SiGe HBT generations. As technology scales to improve the performance and integration level, a large low-frequency noise variation in small geometry SiGe HBTs is first observed in 90 GHz peak fT devices. The fundamental mechanism of this geometry dependent noise variation is thought to be the superposition of individual Lorentzian spectra due to the presence of G/R centers in the device. The observed noise variation is the result of a trap quantization effect, and is thus best described by number fluctuation theory rather than mobility fluctuation theory. This noise variation continues to be observed in 120 GHz and 210 GHz peak fT SiGe HBT BiCMOS technology. Interestingly, the noise variation in the 210 GHz technology generation shows anomalous scaling behavior below about 0.2-0.3um2 emitter geometry, where the noise variation rapidly decreases. Data shows that the collector current noise is no longer masked by the base current noise as it is in other technology generations, and becomes the dominant noise source in these tiny 210 GHz fT SiGe HBTs. The proton response of LFN in SiGe HBTs is also investigated in this thesis. The results show that the relative increase of LFN is minor in transistors with small emitter areas, but significant in transistors with large emitter areas after radiation. A noise degradation model is proposed to explain this observed geometry dependent LFN degradation. A 2-D LFN simulation is applied to SiGe HBTs for the first time in order to shed light on the physical mechanisms responsible for LFN. A spatial distribution of base current noise and collector current noise reveals the relevant importance of the physical locations of noise sources. The impact of LFN in SiGe HBTs on circuits is also examined. The impact of LFN variation on phase noise is demonstrated, showing VCOs with small geometry devices have relatively large phase noise variation across samples.

This work investigates the effects of post-fabrication applied mechanical tensile strain on Silicon (Si) Bipolar Junction Transistor (BJT) and Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices. Applied strain effects on MOSFET transistors are being heavily explored, both in academia and industry, as a possible alternative to dimensional scaling. This thesis focuses on how strain affects Si BJT and SiGe HBTs, where tensile strain is applied after the Integrated Circuit (IC) fabrication has been completed, using a unique mechanical method. The consequence of both biaxial and uniaxial strain application has been examined in this work. Chapter I gives a short introduction to the scope of this work, the motivation for conducting this research and the contributions of this experiment. Chapter II entails a brief discussion on Si bipolar and SiGe heterojunction bipolar device physics, which are key to the understanding of strain induced effects. Chapter III provides a thorough summary of the current state of research regarding applied strain, also known as Strain Engineering. It covers different types, orientations, and application techniques of strain. Chapter IV, highlights the details of this experiment, and also presents the measured results. It is observed that for this particular method of biaxial tensile strain application, the collector current (IC) and current gain degrades for both Si BJT and SiGe HBT. Base current (IB) decreases in Si BJT, though it increases for SiGe HBT after strain. Little or no change is noticed in the dynamic or ac small-signal characteristics like unity-gain cutoff frequency (fT) and base resistance (rBB) after strain. Uniaxially strained SiGe HBT samples showed similar results as the biaxial strain. This chapter also attempts to explain the origin of these strain induced changes. Chapter V, summarizes the finding of this experiment, and concludes the thesis with some future directions for this research.

This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range. For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.

The objective of the dissertation is to combine the recent Mixed-Mode reliability stress studies into a single text. The thesis starts with a review of silicon-germanium heterojunction bipolar transistor fundamentals, development trends, and the conventional reliability stress paths used in industry, after which the new stress path, Mixed-Mode stress, is introduced. Chapter 2 is devoted to an in-depth discussion of damage mechanisms that includes the impact ionization effct and the selfheating effect. Chapter 3 goes onto the impact ionization effect using two-dimensional calibrated MEDICI simulations. Chapter 4 assesses the reliability of SiGe HBTs in extreme temperature environments by way of comprehensive experiments and MEDICI simulations. A comparison of the device lifetimes for reverse-EB stress and mixed-mode stress indicates different damage mechanisms govern these phenomena. The thesis concludes with a summary of the project and suggestions for future research in chapter 5.

The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differential resistance (NDR) effect and a collector current kink effect in first-generation SiGe HBTs at deep cryogenic temperatures. A theory of positive feedback due to the enhanced heterojunction barrier effect at deep cryogenic temperatures is proposed to explain such effects. Intricate design of the germanium and base doping profiles can greatly suppress both carrier freezeout and the heterojunction barrier effect, leading to a significant improvement in the DC and RF performance for NASA lunar missions. Furthermore, cooling is used as a tuning knob to better understand the performance limits of SiGe HBTs. The consequences of cooling SiGe HBTs are in many ways similar to those of combined vertical and lateral device scaling. A case study of low-temperature DC and RF performance of prototype fourth-generation SiGe HBTs is presented. This study summarizes the performance of all three prototypes of these fourth-generation SiGe HBTs within the temperature range of 4.5 to 300 K. Temperature dependence of a fourth-generation SiGe CML gate delay is also examined, leading to record performance of Si-based IC. This work helps to analyze the key optimization issues associated with device scaling to terahertz speeds at room temperature. As an alternative method, an fT -doubler technique is presented as an attempt to reach half-terahertz speeds. In addition, a roadmap for terahertz device scaling is given, and the potential relevant physics associated with future device scaling are examined. Subsequently, a novel superjunction collector design is proposed for higher breakdown voltages. Hydrodynamic models are used for the TCAD studies that complete this part of the work. Finally, Monte Carlo simulations are explored in the analysis of aggressively-scaled SiGe HBTs.

This thesis explores the critical advantages of using silicon-germanium (SiGe) HBTs for RF front-end design. The first chapter looks at the SiGe BiCMOS technology platform and its important performance metrics. The second chapter discusses ultra-wide tuneability and the critical role that this functionality can have on real world applications. The third chapter presents simulated and measured results of two wideband ring oscillators (8-18 GHz) designed and fabricated in the Jazz 120 BiCMOS platform. A 7-22 GHz wideband VGA in the 8HP platform is also presented further exemplifying the wideband capabilities of SiGe HBTs.

<p>Challenges with integrating high-κ gate dielectric,retrograde Si_1-xGe_xchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si_1-xGex surface-channel and different high-κgate dielectric are examined. Si_1-xGex ρMOSFETs with an Al₂O₃/HfAlO_x/Al₂O₃nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si_1-xGe_xρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si_1-xGe_xρMOSFETs.</p><p>Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si_1-xGe_xincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si_1-xGe_x/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi₂-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi_1-xGex is found to form on selectively grown p-typeSi_1-xGe_xused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi_1-xGe_x/p-type Si_1-xGe_xcontacts is 5´10^-8Ωcm², which satisfies the requirement for the 45-nmtechnology node in 2010.</p><p>When the Si_1-xGe_xchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi_1-xGe_xretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.</p><p><b>Key Words:</b>MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.</p>

<p>A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO₂ and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-⁴ Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×10²⁰cm-³. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi₀.₈Ge_0.2/Si_0.8Ge_0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10^-8 Ωcm² and 1.4x10^-7 Ωcm², respectively.</p>

Cette thèse a pour objet l'étude et la réalisation de transistors bipolaires à hétérojonction Si/SiGeC à très hautes performances pour les applications de télécommunications et de détection radar (> 50 GHz). Le premier chapitre rappelle la théorie du fonctionnement du transistor bipolaire, aussi bien en régime statique que dynamique. Nous présentons ensuite dans un second chapitre un historique des technologies de fabrication des TBH SiGe, spécifiquement dans un cadre de compatibilité BiCMOS, en expliquant les choix pris en faveur d'un auto-alignement complet et d'une épitaxie sélective de la base. Les résultats obtenus dans cette thèse sont comparés aux performances de l'état de l'art. Nous étudions ensuite l'optimisation classique du TBH, et nous démontrons comment, par différentes optimisations du profil vertical et des dimensions latérales du composant, nous avons pu augmenter les fréquences fT et fMAX de 200 GHz au début de la thèse jusqu'à environ 300 GHz. La possibilité d'optimiser la tenue en tension collecteur est démontrée par des procédés technologiques en rupture avec l'optimisation classique du transistor, tels que l'émetteur métallique, l'insertion de Ge dans l'émetteur et la recombinaison en base neutre. Des améliorations significatives de BVCEO ont pu être démontrées grâce à ces procédés, ce qui permet d'obtenir des produits fT × BVCEO à l'état de l'art (> 400 GHz.V). La dernière partie de la thèse vise à étudier le comportement du TBH en fonction de la température : Nous décrivons tout d'abord l'auto-échauffement du transistor, et son impact sur les performances dynamiques. Des variantes technologiques permettant de réduire l'auto-échauffement sont étudiées (profondeur des DTI et fragmentation de l'émetteur), et un modèle simple de calcul de RTh est développé. Nous terminons par l'étude du TBH aux températures cryogéniques. fT et fMAX étant fortement améliorées à basse température (plus de 400 GHz), nous en tirons, grâce à l'extraction des différents temps de transit, des perspectives intéressantes pour l'amélioration ultérieure du composant, avec pour objectif d'atteindre des fréquences de transition de l'ordre du THz.

In this thesis, the circuits which comprise the front-end of a millimeter-wave transmit-receive module are investigated using a state-of-the-art 90 nm SiGe BiCMOS process for use in radar remote sensing applications. In Chapter I, the motivation for a millimeter-wave radar in the context of space-based remote sensing is discussed. In addition, an overview of Silicon-germanium technology is presented, and the chapter concludes with a discussion of design challenges at millimeter-wave frequencies. In Chapter II, a brief history of radar technology is presented - the motivations leading to the development of the transmit-receive module for active electronically scanned arrays are discussed, and the critical components which reside in nearly every high-frequency transmit-receive module are introduced. In Chapter III, the design and results of a W-band single-pole, double-throw switch using SiGe p-i-n diodes are discussed. In particular, the design topology and methods used to achieve low-loss and high power handling over a wide matching bandwidth without sacrificing isolation are described. In Chapter IV, the design and results of a W-band low-noise amplifier using SiGe HBT's are discussed. The design methodologies used to achieve high gain and exceptional noise performance over a wide matching bandwidth are described. Concluding remarks and a discussion of future work are in Chapter V.