While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

The objective of the research in this dissertation is to demonstrate the viability of using silicon-germanium (SiGe) bipolar/complementary metal-oxide semiconductor (BiCMOS) technologies in novel high-speed, high-performance wireless and wireline applications. These applications include self-healing integrated systems, W-Band phased array radar systems, and multi-gigabit wireline transceiver systems. The contributions from this research are summarized below: 1. Design of a wideband 8-18 GHz signal source with the best reported tuning range and die area combination for self-healing applications [95]. 2. Design of a robust, multi-band 8-10/ 16-20 GHz signal source with amplitude-locking for self-healing applications. A figure-of-merit (FoM) is proposed that combines tuning range and die area, and this work achieves the best FoM compared with state-of-the art [51]. 3. First ever reported on-die healing of image-rejection ratio of an 8-18 GHz mixer integrated with the multi-band test signal source [52], [96]. 4. Design of a 94 GHz differential Colpitts oscillator with 14% tuning range that spans 86-99 GHz for phased-array radar systems. 5. Identification of technology platform related bottlenecks in multi-gigabit wireline systems. A novel study of linearity of switching transistors in a current-mode logic (CML) gate. 6. A novel FoM that can be used to predict large-signal CML delay using small-signal Y-parameter techniques [97].

SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wireline transceiver in SiGe BiCMOS technology. This work also includes design and testing of a charge amplification channel front-end intended to act as the interface between a piezoelectric sensor and an ADC. An additional feature is the design and testing of a 50 Ohm output buffer utilized for testing of components in a lab setting.

The objective of this research is to explore high-speed analog-to-digital converters (ADCs) using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for wireless digital receiver applications. The stringent requirements of ADCs for the high-performance next-generation wireless digital receiver include (1) low power, (2) low cost, (3) wide input signal bandwidth, (4) high sampling rate, and (5) medium to high resolution. The proposed research achieves the objective by implementing high-performance ADC's key building blocks and integrating these building blocks into a complete sigma-delta analog-to-digital modulator that satisfies the demanding specifications of next-generation wireless digital receiver applications. The scope of this research is divided into two main parts: (1) high-performance key building blocks of the ADC, and (2) high-speed sigma-delta analog-to-digital modulator. The research on ADC's building blocks includes the design of two high-speed track-and-hold amplifiers (THA) and two wide-bandwidth comparators operating at the sampling rate > 10 GS/sec with satisfying resolution. The research on high-speed sigma-delta analog-to-digital modulator includes the design and experimental characterization of a high-speed second-order low-pass sigma-delta modulator, which can operate with a sampling rate up to 20 GS/sec and with a medium resolution. The research is envisioned to demonstrate that the SiGe HBT technology is an ideal platform for the design of high-speed ADCs.

A novel modification to the standard cascode amplifier architecture is presented in SiGe which allows for an optimal separation of gain and breakdown functions through the mixed breakdown cascade architecture, opening the door for moderate power amplifiers in SiGe. Utilizing this technique, a two-stage, high-gain amplifier operating at X-Band is fabricated and measured. The 20 dB of gain per stage represents the highest gain at X-Band at the time of publication. Additionally, a near one Watt power amplifier is designed and fabricated at X-Band, which represents the highest output power in SiGe at X-Band at time of publication. Related to the power amplifier design, thermal considerations are also investigated. The validity of utilizing lumped mutual thermal coupling in SiGe devices is presented. Using this finding, a thermal coupling model and network which are compliant for use with commonly available HBT models and circuit simulators is presented. This model and network is used to thermally optimize SiGe PA cells based upon layout spacing.

Der thermische Widerstand ist eine wichtige Kenngröße von Silicium-Germanium-Hetero-Bipolartransistoren (SiGe-HBTs). Bisher kam es bei der quantitativen Bestimmung der thermischen Widerstände von SiGe-HBTs zu deutlichen Abweichungen zwischen Simulation und Messung. Der Unterschied zwischen Simulation und Messung betrug bei den untersuchten HBTs mehr als 30 Prozent. Diese Arbeit widmet sich der Aufklärung und Beseitigung der möglichen Ursachen hierfür. Zu diesem Zweck werden als erstes die Messmethoden analysiert. Es zeigt sich, dass die bisher verwendete Extraktionsmethode sensitiv auf den Early-Effekt (Basisweitenmodulation) reagiert. Im Rahmen der Untersuchungen wurde ein neues Extraktionsverfahren entwickelt. Die neue Extraktions­methode ist unempfindlich gegenüber dem Early-Effekt. Mit Bauelemente­simulationen wird erstmalig die Wirkung des Seebeck-Effektes (Thermospannungen) auf die elektrisch extrahierten thermischen Widerstände demonstriert. Der Seebeck-Effekt bewirkt, dass die elektrisch extrahierten thermischen Widerstände der untersuchten HBTs nahezu 10 Prozent kleiner als die erwarteten Werte sind. Dieser Effekt wurde bisher nicht beachtet und wird hier erstmals nachgewiesen. Weiterhin wird die Abhängigkeit des thermischen Widerstandes vom Arbeitspunkt untersucht. Dabei hat sich gezeigt, dass bis zu einer Basis-Emitter-Spannung von 0,91 Volt die geometrische Form des Wärme abgebenden Gebietes unabhängig vom Arbeitspunkt ist. Anhand von Messungen wird gezeigt, dass die Dotierung die spezifische Wärmeleitfähigkeit von Silicium reduziert. Die Abnahme wird für Dotierungen größer als 1*1019 cm‑3 deutlich sichtbar. Ist die Dotierung größer als 1*1020 cm‑3, beträgt die Abnahme der spezifischen Wärmeleitfähigkeit mehr als 75 Prozent. Mithilfe einer Simulatorkalibrierung wird die spezifische Wärmeleitfähigkeit als Funktion der Dotierung bestimmt. Die erhaltene Funktion kann künftig beim thermischen Entwurf von HBTs verwendet werden. Somit können zukünftig genauere Vorhersagen zum thermischen Widerstand der HBTs gemacht werden. Dies ermöglicht zuverlässigere Aussagen darüber, wie Änderungen des Transistordesigns zur Minimierung des thermischen Widerstandes beitragen. / The thermal resistance is an important parameter of silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Until now, the quantitative determination of the thermal resistance showed significant differences between measurements and simulations. The difference between simulation and measurement of the investigated HBTs was more than 30 percent. This thesis devotes the clarification and elimination of potential sources for it. For this purpose, the measurement methods are analyzed at first. It is shown, that the currently used extraction method is sensitive to the Early effect (basewidth modulation). A now extraction method was developed, which is not sensitive to the Early effect. For the first time, the influence of the Seebeck effect (thermoelectric voltages) on the electrically extracted thermal resistance is shown by device simulations. The Seebeck effect leads to a 10 percent lower extracted thermal resistances compared to the expected values of the investigated HBTs. This effect was not taken into account up to now and is demonstrated here for the first time. Furthermore, the dependence of the thermal resistance on the operating point was investigated. The results show that the shape of the heat source is independent of the operating point if the base emitter voltage is smaller than 0.91 volt. The thermal conductivity of silicon is decreased by increasing doping concentrations. This is shown by measurements. The reduction of the thermal conductivity is well observable for doping concentrations higher than 1*1019 cm‑3. For doping concentration higher than 1*1020 cm‑3 the reduction amounts to more than 75 percent. The thermal conductivity was determined as a function of the doping concentration with the aid of a simulator calibration. This function can be used in the future thermal design of HBTs. It facilitates the optimization of the HBTs with respect to a minimal thermal resistance.

No description available.

The development of millimeter-wave (30-300 GHz) sensors and communications systems has a long history of interest, spanning back almost six decades. In particular, mm-wave radars have applications as automotive radars, in remote atmospheric sensing applications, as landing radars for air and spacecraft, and for high precision imaging applications. Mm-wave radar systems have high angular accuracy and range resolution, and, while susceptible to atmospheric attenuation, are less susceptible to optically opaque conditions, such as smoke or dust. This dissertation document will present the initial steps towards a new approach to the creation of a mm-wave radar system at 94 GHz. Specifically, this dissertation presents the design, fabrication and testing of various components of a highly integrated mm-wave a 94 Ghz monopulse radar transmitter/receiver. Several architectural approaches are considered, including passive and active implementations of RF monopulse comparator networks. These architectures are enabled by a high-performance three-dimensional rectangular coaxial microwave transmission line technology known as PolyStrataTM as well as silicon-based IC technologies. A number of specific components are examined in detail, including: a 2x2 PolyStrata antenna array, a passive monopulse comparator network, a 94 GHz SiGe two-port active comparator MMIC, a 24 GHz RF-CMOS 4-port active monopulse comparator IC, and a series of V- and W-band corporate combining structures for use in transmitter power combining applications. The 94 GHz cavity-backed antennas based on a rectangular coaxial feeding network have been designed, fabricated, and tested. 13 dB gain for a 2 x 2 array, as well as antenna patterns are reported. In an effort to facilitate high-accuracy measurement of the antenna array, an E-probe transition to waveguide and PolyStrata diode detectors were also designed and fabricated. AW-band rectangular coaxial passive monopulse comparator with integrated antenna array and diode detectors have also been presented. Measured monopulse nulls of 31.4 dB in the ΔAZ plane have been demonstrated. 94-GHz SiGe active monopulse comparator IC and 24 GHz RF-CMOS active monopulse comparator RFIC designs are presented, including detailed simulations of monopulse nulls and performance over frequency. Simulations of the W-band SiGe active monopulse comparator IC indicate potential for wideband operation, with 30 dB monopulse nulls from 75-105 GHz. For the 24-GHz active monopulse comparator IC, simulated monopulse nulls of 71 dB and 68 dB were reported for the azimuthal and elevational sweeps. Measurements of these ICs were unsuccessful due to layout errors and incomplete accounting for parasitics. Simulated results from a series of rectangular coaxial power corporate power combining structures have been presented, and their relative merits discussed. These designs include 2-1 and 4-1 reactive, Wilkinson, and Gysel combiners at V- and W-band. Measured back-to-back results from Gysel combiners at 60 GHz included insertion loss of 0.13 dB per division for a 2-1 combination, and an insertion loss of 0.3 dB and 0.14 dB for "planar" and "direct" 4-1 combinations, respectively. At 94 GHz, a measured insertion loss of 0.1 dB per division has been presented for a 2-1 Gysel combination, using a back-to-back structure. Preliminary designs for a solid-state power amplifier (SSPA) structure have also been presented. Finally, two conceptual monopulse transceivers will be presented, as a vehicle for integrating the various components demonstrated in this dissertation. / Ph. D.

As the demand for wireless electronics is increasing, more and more gadgets are connected wirelessly and devices are being improved constantly. The need of the new research and development for advance electronics with high performances is the priority. The data transfer rates are improved for faster communication and better efficiency is to reduce the battery consumption in handheld devices. This thesis presents three single-stage power amplifiers (PAs): class-AB, class-F and inverse class-F (class-F-1) at 28 GHz. The PAs have identical input networks: input matching, base DC feed, and base stabilizing networks. At the load side, there is a different load network for each PA. Class-AB PA load network has a single inductor with a parasitic capacitor to create a resonance at 28GHz. Class-F PA load network is composed of a parallel network (one LC tank in series with an inductor) and a series network (one 3f0-resonance LC tank in series with a capacitor) to create a multi-resonance load network. Class-F-1 load network is composed of a parallel network (two LC tank in series with an inductor) and a series network (one 2f0-resonance LC tank in series with a capacitor) to have a multi-resonance network. The main purpose of using multi-resonance load networks in class-F and class-F-1 is to shape the collector currents and voltages in order to achieve the highest efficiency possible. The chosen bias point is VCE=2.3V and ICE~12mA. As the results, class-AB PA achieves the peak PAE of 44%, 15 dBm OP-1dB, >19 dBm Psat , and 10 dB Gp. Class-F PA achieves the peak PAE of 46%, 14.5 dBm OP-1dB, ~18 dBm Psat , and 10 dB Gp. Class-F-1 PA achieves the peak PAE of 45%, 15.1 dBm OP-1dB, >18 dBm Psat , and 10 dB Gp.. In order to compare the linearity performances among three PA classes, a two-tone signal and a modulated signal with different modulation schemes (QPSK, 16QAM, 64QAM, and 256QAM) are applied to the PAs to produce IM3, ACPR, and EVM. After the analysis and comparison on efficiency and linearity, class-F PA gives the highest efficiency but has the worst linearity while class-AB has the best linearity but has the worst efficiency among three. Class-F-1 PA results lies in the middle of two other classes in term of efficiency and linearity. / Master of Science