O objetivo desse estudo foi averiguar a possibilidade de se estimar os componentes anaeróbios do déficit máximo acumulado de oxigênio (MAOD) utilizando apenas o consumo de oxigênio (VO2). Adicionalmente, foi proposto um método alternativo que não necessita utilizar a extrapolação do VO2 do exercício submáximo para estimar a demanda de O2 para o exercício supramáximo. Para tanto, dez sujeitos fisicamente ativos foram submetidos aos seguintes testes: a) teste progressivo até a exaustão para determinar a carga correspondente ao consumo de oxigênio (WVO2max); b) seis testes de cargas constantes com intensidades abaixo da WVO2max (40-90% WVO2max); c) um teste a 110% da WVO2max; d) teste anaeróbio de Wingate. A fração do metabolismo anaeróbio alático foi estimada pela fase rápida do excesso do VO2 após o exercício (EPOCRÁPIDO), ao passo que a fração do metabolismo anaeróbio lático foi determinada tanto pela diferença entre MAOD e o EPOCRÁPIDO (MAODLA-1) como pelo acúmulo de lactato no sangue (MAODLA-2). O MAODMOD foi calculado pela somatória do EPOCRÁPIDO com MAODLA-2. Os principais resultados foram: a) as estimativas das contribuições do metabolismo anaeróbio lático não eram estatisticamente diferentes (MAODLA-1 = 2,40 ± 0,66 l; MAODLA-2 = 2,20 ± 0,4 l; p > 0,05); b) similarmente, os resultados do MAOD (3,03 ± 0,62 l) MAODMOD (2,84 ± 0,41) não eram significativamente diferentes (p > 0,05); c) foram detectadas correlações positivas entre MAODMOD, EPOCRÁPIDO, MAODLA-2 e os índices do teste de Wingate; d) os valores percentuais do EPOCRÁPIDO e do MAODLA-1 eram 22 ± 9% e 78 ± 9%, respectivamente. Esses resultados sugerem que os componentes anaeróbios do MAOD podem ser estimados satisfatoriamente utilizando somente o VO2 e que o MAOD pode ser determinado mediante MAODmod / The objective of this study was ascertain the possibility of estimate the anaerobic components of the maximal accumulated oxygen deficit (MAOD) used only oxygen uptake (VO2). In addition, was proposed an alternative method (MAODMOD) to determine the MAOD without using the extrapolation from submaximal VO2 to estimate the O2 demand of supramaximal exercise. Thus, ten subjects physically active performed the following tests: a) a maximal incremental exercise test for the measurement of the power output correspondent to maximal oxygen uptake (WVO2max); b) six submaximal tests with intensities bellow of the WVO2max (40-90% WVO2max); c) a supramaximal test at 110% WVO2max; d) Wingate anaerobic test. The fraction of the anaerobic alactic metabolism was calculated based on the fast component of excess post-exercise oxygen uptake (EPOCRÁPIDO), although the fraction of the anaerobic lactic metabolism was calculated based on both difference between MAOD and EPOCRÁPIDO (MAODLA-1) and changes in net blood lactate accumulation (MAODLA-2). MAODMOD was calculated by the sum of the EPOCRÁPIDO with the MAODLA-2. The main results were: a) non significant difference was found between the anaerobic lactic estimates (MAODLA-1 = 2,40 ± 0,66 l; MAODLA-2 = 2,20 ± 0,4 l; p > 0,05); b) similarly, there was no significant difference (p > 0,05) between MAOD (3,03 ± 0,62 l) and MAODMOD (2,84 ± 0,41); c) positive and significant correlation were detected between MAODMOD, EPOCRÁPIDO, MAODLA-2 and the indices of the Wingate anaerobic test (p < 0,05); d) the mean of the percentage values of the EPOCRÁPIDO and MAODLA-1 were 22 ± 9% e 78 ± 9%, respectively. These data suggest that the anaerobic components of the MAOD can be satisfactorily estimated using only the VO2 and that the MAOD can be determined using the MAODmod

With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.

No description available.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

L'environnement radiatif spatial est composé d'une grande diversité de particules dans un spectre en énergie très large. Parmi les effets affectant les composants électroniques, on distingue les effets cumulatifs et les effets singuliers transitoires analogiques (ASET). Les effets cumulatifs correspondent à une dégradation continue des paramètres électriques du composant induits par un dépôt d'énergie à faible débit de dose tout au long de la mission spatiale. Les ASETs sont eux causés par le passage d'une particule unique traversant une zone sensible du composant et engendrant une impulsion de tension transitoire qui se propage à la sortie de l'application. Au cours des tests au sol, les deux effets sont étudiés séparément, mais ils se produisent simultanément en vol. Il se produit donc un effet de synergie, induit par la combinaison de la dose et de l'apparition soudaine d'un ASET dans le dispositif préalablement irradié.Une étude de l'effet de synergie dose-ASET est proposée. Pour accélérer les irradiations, une technique connue sous le nom de « méthode de commutation de débit de dose » (DRS) prenant en compte la sensibilité accrue au faible débit de dose (ELDRS) est utilisée. Un modèle haut niveau est développé en utilisant l'analyse circuit permettant de prédire l'effet de synergie observé sur un amplificateur opérationnel à trois étages. Pour prédire l'effet de synergie, l'effet de dose est pris en compte en faisant varier les paramètres décrivant le modèle suivant une loi de variation déduite de la dégradation du courant d'alimentation qui est couramment enregistré au cours des essais industriels. Enfin, les effets transitoires des radiations sur l'électronique (TREEs) induits par un environnement de très fort débit de dose de rayons X pulsés ainsi que l'effet de synergie dose-TREE sont étudiés à l'aide d'un générateur de Flash-X. La méthode classique d'analyse des ASETs permet alors d'expliquer la forme des impulsions transitoires observées. / The natural radiative space environment is composed by numerously particles in a very large energy spectrum. From an electronics component point of view, it is possible to distinguish cumulative effects and so-called Analog Single Event Transient effects (ASET). Cumulative effects correspond to continuous deterioration of the electrical parameters of the component, due to a low dose rate energy deposition (Total Ionizing Dose: TID) throughout the space mission. ASETs are caused by a single energetic particle crossing a sensitive area of the component inducing a transient voltage pulse that occurs at the output of the application. During ground testing, both effects are studied separately but happen simultaneously in flight. As a result a synergy effect, induced by the combination of the low dose rate energy deposition and the sudden occurrence of an ASET in the device previously irradiated, occurs. A study of dose-ASET synergistic effects is proposed using an accelerated irradiation test technique known as Dose Rate Switching method (DRS) tacking into account the concern of the Enhanced Low Dose Rate Sensitivity (ELDRS). A High Level Model is developed using circuit analysis to predict the synergy effect observed on a three stages operational amplifier. To predict synergy effect, the TID effect is taken into account by varying the model parameters following a variation law deduced from the degradation of the supply current which recorded during usual industrial TID testing. Finally, the Transient Radiation Effects on Electronics (TREE) phenomena induced by a Very High Dose Rate X-ray pulse environment and the dose-TREE synergy effect are then investigated using an X-ray flash facility. The classical ASETs methodology analysis can explain the shapes of transients observed.

Recently, a lot of research work has been dedicated toward enhancing performance, reliability and integrity of distributed energy resources that are integrated into distribution networks. The problem of islanding detection and islanding prevention (i.e. anti-islanding) has stimulated a lot of research due to its role in severely compromising the safety of working personnel and resulting in equipment damages. Various Islanding Detection Methods (IDMs) have been developed within the last ten years in anticipation of the tremendous increase in the penetration of Distributed Generation (DG) in distribution system. This work proposes new IDMs that rely on transient and distributed behaviors to improve integrity and performance of DGs while maintaining multi-DG islanding detection capability. In this thesis, the following questions have been addressed: How to utilize the transient behavior arising from an islanding condition to improve detectability and robust performance of IDMs in a distributive manner? How to reduce the negative stability impact of the well-known Sandia Frequency Shift (SFS) IDM while maintaining its islanding detection capability? How to incorporate the perturbations provided by each of DGs in such a way that the negative interference of different IDMs is minimized without the need of any type of communication among the different DGs? It is shown that the proposed techniques are local, scalable and robust against different loading conditions and topology changes. Also, the proposed techniques can successfully distinguish an islanding condition from other disturbances that may occur in power system networks. This work improves the efficiency, reliability and safety of integrated DGs, which presents a necessary advance toward making electric power grids a smart grid.

State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.