Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations. Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications. / PHD / In communication systems, filter design is a fundamental task required to recover the signal of interest in the presence of interference. As upcoming communication systems, such as 5th generation (5G) mobile communications and future IEEE 802.11 standards (Wi-Fi), require higher speed and flexibility in signal processing due to the rapidly increasing number of users and data rates, it becomes more challenging to design such filters. In general, analog filters are useful for high-speed, digital filters features flexibility. To take advantage of both aspects, discrete-time (DT) domain filters have become a promising alternative, which can be used to implement digital signal processing functions in the analog domain. This dissertation presents the development of DT analog finite-impulse-response (AFIR) filter design for mixed-signal processing applications. The core idea in this work is to adopt the capacitive DAC (CDAC) as a coefficient multiplier, which enables digital code coefficient multiplication as well as high-speed and high-linearity performance while consuming low power. A prototype 4th order DT FIR filter implemented in 32nm SOI CMOS process is demonstrated with measurements. Based on the developed AFIR filters, proof-of-concept FIR-based beamforming is investigated as well. For this purpose, AFIR filter modules are built on printed-circuit-boards (PCBs) and coefficients are calculated by a simplified method. In addition, this dissertation also includes analysis and optimization of multi-section CDAC (MS-CDAC) structures. Traditional CDAC approaches have a fundamental trade-off between noise and linearity versus size, switching energy and speed. This work explores the characteristics of CDACs depending on the section segmentations and the optimal structure is selected based on the trade-off. Through comprehensive simulations and calculations, the selected structure for 10-bit MS-CDAC achieved 97% and 98% reduced total capacitance and switching energy, respectively.

A relação entre transferência de lipídeos, idade e aterogênese são complexas e ainda não estão claras. É possível que a troca de lipídeos esteja alterada com a avançar da idade e relacionada com a Doença Arterial Coronariana (DAC). O objetivo deste trabalho foi verificar a hipótese se em indivíduos mais jovens a habilidade da HDL de receber lipídeos é diferente de indivíduos mais velhos com e sem a evidência clínica da DAC. Dentro desses aspectos, foram determinados o diâmetro da partícula desta lipoproteína, a atividade da Paraoxonase (PON1) e sua capacidade de receber lipídeos. Para tanto, foram estudados 86 indivíduos divididos em quatro grupos: adulto jovem (25±4), meia-idade (42±8), idosos sem evidência clínica de DAC (75±6) e idosos com DAC (74±5). Uma nanoemulsão artificial rica em colesterol (LDE) marcada com 3H-TG e 14C-CL ou 3H-CE e 14C-FL foi incubada com plasma. Após a precipitação de outras lipoproteínas, o sobrenadante contendo HDL foi separado e em seguida, medida a radioatividade. O diâmetro da HDL foi medido por laser scattering (nm). Foram constatadas diferenças significativas entre as taxas de transferência de 3H-éster de colesterol (CE) entre os grupos: adulto jovem (3.7±1.0%); meia idade (4.1 ±0.7%) e idosos (5.3±1.8%);p= 0.024. Também ocorreu diferença entre as taxas de transferência do 14C-fosfolipídeo (FL): adulto jovem (18.7±4.6%), meia idade (18.3 ±4.0%) e idosos (20.6±5.3); p=0.0368. Com relação ao tamanho das partículas de HDL, foi encontrada diferença entre os grupos: os grupos adulto jovem (8.9± 0.3nm) e meia idade (8.9± 0.3nm) apresentaram menores diâmetros de HDL quando comparados ao do grupo de idosos sem evidência clínica da DAC (9.7± 1.6);p= 0,0444. As transferências de lipídeos foram expressas em % de radioatividade. A idade correlacionou-se positivamente com a taxa de transferência do 3H- éster de colesterol (r=0.3365; p=0.0036), com a concentração de colesterol total (r=0.4965; p=0.0001) e com a concentração de HDL colesterol (r=0.3559; p=0.0023). Também houve correlação positiva com o tamanho de HDL (r=0.3695; p=0.0013). Em princípio, os indivíduos idosos sem evidência clínica da DAC, aparentemente têm alguma proteção contra a mesma. Desse modo, com o intuito de saber se os resultados encontrados no presente trabalho sustentam a afirmação acima, foi realizada a comparação desse grupo com um grupo de idosos que apresentavam a DAC. O grupo com DAC apresentou menor tamanho de partícula de HDL (8,7±0,7). As taxas de transferência de 3H-CE e de 14C-FL também foram menores neste grupo (3H-CE=3,1 ±2,3 e 3H-TG= 5,1 ±1 ,6). Devido ao importante papel antiaterogênico da HDL, esses resultados podem ser relevantes para estabelecer novos mecanismos existentes entre os aspectos qualitativos dessa lipoproteína, o avanço da idade e a presença da DAC. / The relationship between transfer of lipids, age and atherogenesis are complex and yet unclear and is possible that the shift of lipids to HDL may be altered by the aging process and related with coronary artery disease (CAD). We tested the hypothesis whether in younger patients the ability of HDL to receive lipids is different from that of elderly patients with or without CAD. Inside of these aspects, the HDL size, the activity of Paraoxonase (PON1) and its capacity to receive lipids was determined. It was studied, 25 younger, 25 middle age, 36 elderly patients with a coronariography and/or a perfusion scintilography on the last 6 months (11 with CAD, 74±5 yo; and 25 patients without proved CAD, 75±6 yo). An artificial cholesterol-rich nanoemulsion labeled with 3H-TG and 14C-FC or H-CE and 14C-PL was incubated, per 1 hour, with plasma. After chemical precipitation of apoB-containing lipoproteins and the nanoemulsion, the supernatant containing HDL was counted for radioactivity. The HDL diameter was measured by laser-light-scattering. Transfer of CE and PL to HDL was smaller in young patients than in the elderly patients without CAD, but the transfer of the other lipids are equal (CE: young= 3.7±1.0%; middle age= 4.1 ±0.7%; elderly without CAD= 5.3±1.8%; p= 0.024 and PL: young= 18.7±4.6%; middle age= 18.3 ±4.0%; elderly without CAD= 20.6±5.3; p=0.0368). The HDL size was greater in elderly group without CAD (9.7± 1.6nm) than in younger (8.9± 0.3nm) and middle age patients (8.9± 0.3nm); p=0,0444. Transfer of lipids to HDL was expressed as % of total incubated radioactivity. The age positively correlated with the transfer of CE (r=0.3365; p=0.0036), with the total cholesterol concentration (r=0.4965; p=0.0001) and with the HDL concentration cholesterol (r=0.3559; p=0.0023). Also had positive correlation with the size of HDL (; p=0.0013). In principle, the aged patients without CAD, have some protection against the same one. In this aspect, with intention to know if the results found in the present work support the affirmation above, was compared this group with a group of aged that presented the CAD. Comparing elderly patients without CAD with elderly patients with CAD, the transfer of CE and FL as well as HDL size was smaller in the CAD group (CE=3.1±2.3 and TG= 5.1±1.6; 8.7±0.7nm). Due to HDL important antiatherogenic roles, this result can be relevant to establish new mechanisms and risk factors in aging and in CAD.

Made available in DSpace on 2016-04-04T18:27:48Z (GMT). No. of bitstreams: 1 Fabricia Medeiros Sanches.pdf: 436028 bytes, checksum: 8c7d688676aa4a702ade87e22bd12392 (MD5) Previous issue date: 2009-02-27 / The Central Relationship Questionnaire-CRQ is a self-report instrument designed to evaluate the central relationship patterns, specially related to the lovers relationship. As the Core Conflictual Relationship Them- CCRT the CRQ is divided in three subscales: Wishes (W); Responses from Other (RO), and Responses of Self (RS). The aim of this study was to investigate the internal consistency and the convergent and discriminant validities of the Brazilian version of the CRQc6.0 in coronary patients. Method: The Sample included 40 coronary patients (1G) and 30 people of the community (2G). When compared to the 2G participants of 1G were older (average age 58 vs. 37 years old), predominantly composed by men (65% vs. 43,3%), with lower scholarship level (65% - less of 5 years vs. 47% - complete high school). Instruments: The CRQ 6.0 and the Escala de Sintomas Psicopatol?gicos- EAS-40, a measure of psychopathological symptoms according to the following dimensions: psychoticism (F1), obsessivity-compulsivity(F2), somatization (F3) and anxiety (F4).Results: Results suggested: good internal consistency of CRQ 6.0 (?>0,80) in both groups excepting to RO (?=0,58) in 1G; no significant association between the CRQ 6.0 dimensions and the EAS-40 dimensions in 1G p>0,05); significant association between RO and psychoticism, and between RE and psychoticism, RE and obsessivity-compulsivity; RE and somatization and RE and EAS-total (p<0,01). The discriminant validity analyses between the 1G and 2G pointed to significant differences to the W (p=0,018) and RE (p=0,026) dimensions. Future researches should involve more representative and paired samples. It is still suggested that measures of levels of alexithymia and depression are evaluated. / O Question?rio de Relacionamento Central (CRQ) ? um instrumento de autorelato para avaliar o padr?o central de relacionamentos, mais precisamente os relacionamentos amorosos. Originado do m?todo do Tema Central de Relacionamento Conflituoso-CCRT, ? dividido em tr?s subescalas: Desejos (D), Respostas do Outro (RO) e Respostas do Eu (RE). O objetivo foi o de investigar a consist?ncia interna, validade convergente e discriminante da vers?o brasileira do CRQ em pacientes coronarianos. A amostra incluiu 40 pacientes com Doen?a Arterial Coronariana, constituintes do Grupo Um (G1) e 30 acompanhantes do Grupo Dois (G2). Comparado os dois grupos, GC tinha idade m?dia mais elevada (idade m?dia 58 vs.37anos), predomin?ncia do sexo masculino (65% vs. 43,3%) e n?vel mais baixo de escolaridade (62% menor que cinco anos vs. 47% segundo grau completo). Instrumentos: CRQ 6.0 e Escala de Sintomas Psicopatol?gicos-EAS-40 que avalia sintomas psicopatol?gicos segundo as dimens?es: psicoticismo (F1), obsessividade-compulsividade (F2), somatiza??o (F3) e ansiedade (F4). Resultados: Todas as dimens?es do CRQ apresentaram boa consist?ncia interna (?>0,80) em ambos os grupos, com exce??o de RO (?=0,58) no G1. N?o foram encontradas associa??es significantes entre as dimens?es do CRQ 6.0 e as da EAS-40 no G1. No G2 as associa??es foram significantes entre RO e psicoticismo e entre RE e psicoticismo, obsessividade compulsividade e somatiza??o e EAS-40 total (p<0,01). A an?lise de validade discriminante entre G1 e G2 resultou em diferen?as significantes nas dimens?es D (p=0,018) e RE (p=0,026). Pesquisas futuras com o CRQ 6.0 e pacientes com DAC, devem contar com amostras maiores e pareadas. Sugerem-se, ainda, avalia??es dos n?veis de alexitimia e depress?o.

Les convertisseurs analogiques-numériques fondés sur le principe de la modulation §¢ sont capables de fonctionner à des résolutions très élevés. L'utilisation en interne d'un CAN et d'un CNA multibit permet de réduire le taux de suréchantillonnage, les contraintes imposées par les circuits actifs, amé- liore la stabilité de la boucle du modulateur, mais rend celui-ci très sensible aux imperfections des composants du convertisseur numérique analogique (CNA) interne situé dans le chemin de retour. Les erreurs statiques dues aux non idéalités des circuits constitutifs de ce CNA peuvent être corrigées au moyen de techniques d'appariement dynamique des composants (DEM). Ce travail de thèse est consacré entre autre à l'étude théorique de ces techniques de correction des défauts des cellules des CNA multibits. Après avoir rappelé le principe de la conversion §¢ d'une part, et les différentes sources d'erreurs dominantes dans le cas multibit d'autre part, les techniques d'appariement existantes sont analysées et comparées. Nous soulignons les avantages, les inconvénients, et les domaines d'applications préférentiels de chacune. Le coeur du travail consiste en la proposition de quatre nouvelles techniques d'appariement dynamique. Les deux premières dérivent de la méthode de la moyenne des données (DWA), l'une pour le cas passe-bas du premier ordre, l'autre dans le cas passe-bande du second ordre. Les deux dernières propositions (appelées MDEM et STDEM) dérivent des deux algorithmes de tri (SDEM) et d'arborescence (TDEM) : elles conviennent à une mise en forme des erreurs d'ordre élevé et sont destinées aux applications passe-bas et passe-bande de haute performance. Ces quatre méthodes proposées ont été mises en équation et leurs performances confirmées par diverses simulations. Une implantation des algorithmes MDEM et STDEM a été faite au niveau cellule standard jusqu'à l'étape finale de routage en technologie CMOS 0.35 ¹m. L'ensemble des résultats des simulations au niveau système et au niveau transistor conforme l'avantage des techniques développées dans ce travail en termes de surface occupée et aussi de fréquence maximale d'application, si on les compare avec les algorithmes conventionnels de SDEM. Dans une dernière partie, les erreurs dynamiques du CNA, en particulier l'effet de la gigue d'horloge, le glitch, la dissymétrie des temps de transition, l'injection de charge (CFT) et la métastabilité du quantificateur sont également analysés. A l'issue de ces réflexions, une nouvelle cellule de CNA incluant un bloc limitant la plage dynamique de la commande d'entrée (SRD) est proposée. Elle possède une structure de remise à zéro partielle (semi-RZ) qui permet de bénéficier à la fois de l'avantage de la cellule RZ et non RZ. De plus, l'effet du retard du bloc de DEM est compensé par une modification dans l'architecture convenant aux applications passe-bande haute fréquence.

In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been proven to provide low power and high speed operation. Typically, capacitor matching is the best among all integrated circuit components but the mismatch among nominally equal value capacitors will introduce nonlinear distortion. By using dynamic element matching (DEM) technique in the MSB DAC, the nonlinearity caused by capacitor mismatch is greatly reduced. The output buffer employed direct charge transfer (DCT) technique that can minimize kT/C noise without increasing the power dissipation. This segmented DAC is designed and simulated in 0.18 μm CMOS technology, and the simulated core DAC block only consumes 403 μW. / Graduation date: 2012

Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clockless transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

More than a decade since the democratic transition in 1994, South Africa still grapples with incredibly high levels of unemployment. An underperforming manufacturing sector has hampered economic growth and job creation in a country with a large pool of low and semi-skilled labour. In response to these challenges the South African government has initiated a guiding framework (NIPF) and action plan (IPAP) spearheaded by a sectoral and geographic focus to place the country on a more labour-intensive industrial growth path. Given this context, it is instructive to note that industrial clustering has been identified as critical to the sustainable development of industry in both developed and developing economies. Whilst the role of industrial clustering in assisting industrial development is well documented, this paper aims to further interrogate the impact of industrial clustering on another critical developmental issue, employment. Using the Durban Automotive Cluster (DAC) as a case study, the primary objective of this research is to interrogate the impact of industrial clustering on firm-level employment. A mixed-method methodology is utilised in the study, collecting both primary and secondary data from face-to-face interviews conducted with nineteen firm-level representatives and two DAC representatives. The research findings and analysis conclude that on average, the impact of the DAC on firm-level employment is positive, although largely indirect. In particular, small or firms with low degrees of production-related technological intensity on their production perceive the impact of the DAC on their firm-level employment most positively. The majority of member firms believe the DAC has either helped sustain or in some cases grow their firms’ employment levels. The only variable that has had a more positive impact on firm-level employment is the MIDP, with labour market policies perceived to have had the most negative impact on employment. The study suggests that greater communication between the DAC and local and national governments to ensure each stakeholder’s objectives are better aligned to ensure growth of the industry (to stimulate job creation). This process will not be simple and will depend heavily on the country’s ability to address critical macro-constraints that the study has shown to hinder employment growth amongst the DAC firms. Whilst the findings relate specifically to the automotive industry in KwaZulu-Natal, the relevance of the findings extends well beyond the automotive sector. The study provides key lessons for South Africa’s sectoral and geographically focused industrial policy focus that aims to achieve industrial development and employment growth in South Africa. / Thesis (M.Dev.Studies)-University of KwaZulu-Natal, Durban, 2012.

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC. Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση της θεωρίας των πιθανοτήτων τα χαρακτηριστικά του απλού Ladder και χρησιμοποιήθηκαν για την εξαγωγή συμπερασμάτων που αφορούν στη γραμμικότητα της νέας δομής Ladder. Τα θεωρητικά αποτελέσματα επιβεβαιώθηκαν με εξομοιώσεις. Τέλος, μία σχεδίαση σε φυσικό επίπεδο με την χρήση μόνο MOSFETS και CMOS τεχνολογίας (χωρίς την χρήση αντιστάσεων) σχεδιάσθηκε και εξομοιώθηκε στο Cadence ένας Ladder της νέας δομής. / This Diploma Thesis studies on a new Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the University of Patras. The new DAC structure is based on the simple R2R ladder combining several of them in a 2-dimentional grid. As result a high linearity DAC is derived after a simple calibration procedure. The Diploma Thesis presents results on probability of the simple R2R Ladder, employs these results so as to forecast the linearity of the 2-dimentional Ladder, whereas confirms theoretical results with simulations. Finally, a DAC based on the 2-dimentional topology has been designed and simulated using Cadence, in the framework of this Diploma Thesis.

abstract: A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA / Dissertation/Thesis / Ph.D. Electrical Engineering 2011