Este trabalho apresenta uma arquitetura para simulação de circuitos de lógica com binacional de topologia arbitrária, visando interfaceamento com algoritmos evolutivos para fins de geração de hardware. A implementação é em FPGA utilizando a técnica VRC. O simulador permite circuitos compostos por LUTs de número de entradas parametrizável. A livre interconectividade entre as LUTs permite a construção de circuitos cíclicos. A arquitetura é modular e de interfaceamento simples. Alta performance é obtida através do uso de múltiplos módulos de simulação em paralelo, trazendo resultados que ultrapassam os obtidos em outros trabalhos utilizando DPR. / This work presents an architecture for simulation of combinational logic circuits of arbitrary topology, meant to be interfaced with evolutionary algorithms for hardware generation. It was implemented in FPGA using the VRC technique. The simulator allows for circuits composed of LUTs of parametrizable number of imputs. The free interconectivity between LUTs allows the construction of cyclic circuits. The architecture is modular and of simple interfacing. High performance is obtained by the use of multiple simulation modules in parallel, bringing results that surpass the ones obtained from other works based on DPR.

UTFPR; CNPq; CAPES; Fundação Araucária; Ministério da Saúde / Os sistemas de diagnóstico por imagem de ultrassom (US) figuram entre os mais sofisticados equipamentos de processamento de sinais na atualidade. Apesar da alta tecnologia envolvida, a maioria dos sistemas comerciais de imagem possui arquitetura típica “fechada”, não atendendo às exigências de flexibilidade e acesso aos dados de radiofrequência (RF) para desenvolvimento e teste de novas modalidades e técnicas do US. Este trabalho apresenta uma nova arquitetura modular de hardware (front-end), baseada em dispositivos FPGA (Field Programmable Gated Array), e software (back-end), baseada em PC ou DSP, totalmente programável, aberta e flexível, para pesquisa e investigação de técnicas inovadoras para geração de imagens médicas por US. A plataforma desenvolvida ULTRA-ORS (do inglês Ultrasound Open Research System) permite conexão com transdutores multielementos dos tipos lineares, convexos e phased array com frequência central entre 500 kHz e 20 MHz, e capacidade de expansão para operação com transdutores de até 1024 elementos multiplexados. O módulo eletrônico lógico para formação do feixe (beamformer transmitter) possibilita excitação simultaneamente, através de sinais PWM, de 128 canais com formas de ondas arbitrárias, abertura programável, e tensão de excitação de até 200 Vpp, permitindo controle individual de habilitação, amplitude de apodização com até 256 níveis, ângulo de fase e atraso temporal de disparo adequado para focalização na transmissão. O módulo de recepção (beamformer receiver) realiza a aquisição simultânea de 128 canais com taxa de amostragem programável até 50 MHz e resolução de 12 bits. Como item imprescindível deste trabalho, a plataforma proposta possibilita acesso e transferência dos dados de RF digitalizados para um computador através de interfaces seriais ou para kits de DSP para processamento das imagens. Como resultado do projeto de pesquisa, é apresentado um novo sistema digital de US que pode ser utilizado para avaliações das imagens geradas pela técnica beamforming, utilizando como referência a ferramenta de simulação Field II e comparações com as imagens geradas por equipamentos comerciais em phantom mimetizador de tecidos biológicos de US. / Medical ultrasound (US) scanners are amongst the most sophisticated signal processing machines in use today. Even with the recent advances in electronic technology, their typical architecture is often “closed” and does not fit the requirements of flexibility and RF data access to the development and test of new modalities and US techniques. This work presents the development of a novel modular hardware architecture (front-end), FPGA-based (Field Programmable Gated Array) and software (back-end), PC-based or DSP-based, fully programmable, open and flexible, for research and investigation of new techniques for medical US imaging. The proposed platform, ULTRA-ORS (Ultrasound Open Research System), allows connection to linear, convex and phased array transducers with center frequency between 500 kHz and 20 MHz, and expansion capability for operation with transducers up to 1024 multiplexed elements. The transmitter beamformer can excite simultaneously, using PWM signals, 128-channel with arbitrary waveform, programmable aperture, and 200 Vpp excitation voltage, allowing individual enable control, amplitude apodization up to 256 levels, phase angle and proper time delay for focusing on transmission. The receiver beamformer can handle simultaneous 128-channels acquisition with programmable sampling rate up to 50 MHz and 12-bit resolution. As essential item of this work, the platform enables access to the raw RF signals to be transferred to a computer through serial ports or DSP kits for imaging processing. As a result of the research project, we present a new digital US system that can be used for evaluation of images generated by the beamforming technique, using as reference the Field II simulation tool and comparisons with commercial equipment using US tissue-mimicking phantom. / 5000

A presença de cargas não-lineares em um ponto do sistema de distribuição pode deformar a forma de onda de tensão devido ao consumo de correntes não senoidais. O uso de filtros ativos de potência permite uma redução significativa do conteúdo harmônico da corrente de alimentação. Entretanto, as estruturas digitais de controle para estes filtros, particularmente o cálculo das correntes de referência, pode necessitar de processamento de alto desempenho. Neste trabalho se propõe o desenvolvimento de estruturas de controle com alto desempenho de processamento, para aplicação em filtros ativos de potência. Neste sentido, é considerada uma arquitetura que permite processamento paralelo utilizando dispositivos lógicos programáveis. A estrutura desenvolvida utiliza um modelo híbrido com um DSP e uma FPGA. O DSP é utilizado para aquisição de sinais de tensão e corrente, controladores adicionais relacionados a fundamental e acionamento PWM. A FPGA é utilizada para o processamento intensivo do sinal de compensação de harmônicas. Desta forma, através da análise experimental são obtidas reduções significativas nos tempos de processamento comparadas as abordagens tradicionais utilizando somente DSP. Os resultados experimentais validam a estrutura projetada e são comparados com outras arquiteturas relatadas na literatura. / The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Este trabalho apresenta a modelagem e implementação em FPGA de sistemas digitais de compensação de desvios para TIADC. O desenvolvimento de todo este trabalho seguiu uma metodologia top-down. Seguindo esta metodologia foi elaborada a modelagem comportamental de um TIADC de dois canais e seus respectivos desvios de offset, ganho e clock skew em Simulink. Além da modelagem comportamental de sistemas digitais para a compensação destes desvios. Para o desvio de clock skew foi utilizada a compensação através de filtros de delay fracionário, mais especificamente, a eficiente estrutura de Farrow. A definição de qual método seria utilizado para o projeto do filtro, e da estrutura de Farrow, exigiu um estudo de diversos métodos de projeto apresentados na literatura. Os sistemas digitais de compensação modelados foram convertidos em código VHDL, para implementação e validação em FPGA. A validação destes sistemas foi realizada utilizando a metodologia de teste FPGA In Loop. Os resultados obtidos com os compensadores de desvio do TIADC demonstram o elevado ganho de desempenho fornecido por estas estruturas. Além deste resultado, este trabalho ilustra o potencial das metodologias de desenvolvimento, implementação e teste em FPGA utilizadas para a obtenção destes compensadores. / This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs. / This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.

Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs. / This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.

FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts.

<p>To facilitate indoor air quality (IAQ) monitoring, the research described herein develops and implements methods for the electronic integration of two types of gas sensor, each functionalized with a polymer blend tailored for CO₂ detection. A highly sensitive and tunable electronic chemiresistive sensor interface was developed and experimentally validated. This device achieved analog-to-digital conversion (ADC) through a pulse width modulated (PWM) signal, temporary data storage with an efficient data buffering system, and noise reduction and signal amplification utilizing an instrumentation amplifier integrator circuit. These techniques can used beyond CO₂-specific applications to compensate for certain undesirable chemiresistive sensor characteristics, such as low response magnitude and signal noise. Additionally, resonant mass sensing circuitry was combined with an on-chip field programmable gate array (FPGA) implemented frequency counter. Hz-level resolution was achieved with an Alorium Snō FPGA board and a Verilog data acquisition and communication program. This device can monitor up to 16 sensor channels simultaneously and has a straightforward interface with a controllable output. Furthermore, the functionality of each integrated sensor was experimentally validated. With additional work, these integrated designs have the potential to be inexpensive, low-power, highly sensitive devices that are suitable for practical use in IAQ monitoring applications.</p>

Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents the development, experimentation and validation of a reliable and robust system to monitor the injector pulse generated by an Engine Control Module (ECM) and send the corresponding fueling quantity to the real-time computer in a closed loop Hardware In the Loop (HIL) bench. The system can be easily calibrated for different engine platforms as well. The fueling quantity that is being injected by the injectors is a crucial variable to run closed loop HIL simulation to carry out the performance testing of engine, aftertreatment and other components of the vehicle. This research utilized Field Programmable Gate Arrays (FPGA) and Direct Memory Access (DMA) transfer capability offered by National Instruments (NI) Compact Reconfigurable Input-Output (cRIO) to achieve high speed data acquisition and delivery. The research was conducted in three stages. The first stage was to develop the HIL bench for the research. The second stage was to determine the performance of the system with different threshold methods and different sampling speeds necessary to satisfy the required accuracy of the fueling quantity being monitored. The third stage was to study the error and its variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and cheaper inductor load cells emulating the injectors, over different operating conditions with full factorial design of experimentation and mixed model Analysis Of Variance (ANOVA). Different thresholds were experimented to find out the best thresholds, the Start of Injection (SOI) threshold and the End of Injection (EOI) threshold that captured the injector “ontime” with best reliability and accuracy. Experimentation has been carried out at various data acquisition rates to find out the optimum speed of data sampling rate, trading off the accuracy of fueling quantity. The experimentation found out the expected error with a system with cheaper solution as well, so that, if a test application is not sensitive to error in fueling quantity, a cheaper solution with lower sampling rate and inductors as load cells can be used. The statistical analysis was carried out at highest available sampling rate on both injectors and inductors with the best threshold method found in previous studies. The result clearly shows the factors that affect the error and the variability in the standard deviations in error; it also shows the relation with the fixed and random factors. The real-time application developed for the HIL bench is capable of monitoring the injector waveform, using any fueling ontime table corresponding to the platform being tested, and delivering the fueling quantity in real-time. The test bench made for this research is also capable of studying injectors of different types with the automated test sequence, without occupying the resource of fully capable closed loop test benches for testing the ECM unctionality.

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.