This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA). Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random local variations are growing rapidly in each technology generation. However, there is requirement of quantification of variation in silicon. We propose an all-digital circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form based on a reconfigurable ring oscillator structure. A test chip is fabricated in 65nm technology node to show the feasibility of the technique. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. The huge random delay variation in silicon motivates the inclusion of random local process parameters in delay model. In today’s low power design with multiple supply domain leads to non-uniform supply profile. The switching activity across the chip is not uniform which leads to variation of temperature. Accurate timing prediction motivates the necessity of Process, Voltage and Temperature (PVT) aware delay model. We use neural networks, which are well known for their ability to approximate any arbitrary continuous function. We show how the model can be used to derive sensitivities required for voltage and temperature scalable linear SSTA for an arbitrary voltage and temperature point. Using the voltage and temperature scalable linear SSTA on ISCAS 85 benchmark shows promising results with average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.65% and errors in predicting the 99% and 1% probability point are 1.31% and 1% respectively with respect to SPICE.

This dissertation studies a local manifestation of ecclesiastical reform in the medieval county of Savoy: the twelfth-century transformation of secular canons into Augustinian regular canons at the church of Sts. Peter and Ursus in the alpine town of Aosta (now Italy). I argue that textual sources, material culture, and the practice of place together express how the newly reformed canons established their identity, shaped their material environment, and managed their relationship with the unreformed secular canons at the cathedral. The pattern of regularization in Aosta—instigated by a new bishop influenced by ideas of canonical reform—is only one among several models for implementing reform in medieval Savoy. This study asserts the importance of this medieval county as a center for reforming efforts among a regional network of churchmen, laymen, and noblemen, including the count of Savoy, Amadeus III (d. 1148). After a prologue and introduction, chapter 1 draws on traditional textual evidence to recount the history of reform in medieval Savoy. Chapters 2 through 4 focus on the twelfth-century sculpted capitals in the cloister built to accommodate the common life of the new regular canons. Several of the historiated capitals portray the biblical siblings, Martha and Mary, and Leah and Rachel, as material metaphors that reflect and reinforce the active and contemplative lives of the Augustinian canons. Other capitals represent the regular canons’ assertion of their precedence over the cathedral canons and suggest tensions between the two communities. The final chapter examines thirteenth-century conflicts over bell-ringing and ecclesiastical processions in the urban topography of Aosta to illustrate how the regular and secular canons continued to negotiate their relationship. Appendices include an English translation of a vita of St. Ursus (BHL 8453). The dissertation as a whole reconstructs the places and material culture of medieval Aosta to convey the complexities of religious and institutional life during a time of reform and beyond. / text

「比爾與梅琳達•蓋茲基金會」（Bill & Melinda Gates Foundation）從成立至今，捐出超過300億美元的鉅款，資助了近8000項慈善公益專案，其範圍橫跨了全世界極貧地區，挽救無數寶貴生命，堪稱全球影響力最大的公益基金會。 從資訊軟體專業起家的Bill Gates對慈善領域並不熟悉，但卻能在短時間內利用觸媒特性，快速建立合作夥伴系統、吸納捐款與資源，充份發揮平台的正向網絡效應及鎖定效應，迅速壯大基金會規模，並高度有效率運用資源，讓每一分錢的價值發揮到最大，足以作為學習借鏡。 本研究目的在找出「比爾與梅琳達•蓋茲基金會」的經營模式與機制設計，並依此探討其對全人類社會關鍵議題的影響與貢獻；及其關鍵性成功因素，同時探究其對慈善事業及其他公益組織有何影響。希望藉此提供台灣其他非營利組織一些建議，讓它們能從蓋茲基金會的成功經驗中學習，或是在此基礎上創新。 本研究發現，蓋茲基金會創新的觸媒平台經營模式與獨特的機制設計 -「對其目標市場及客戶客觀精確且完整深入的研究分析」、「創意的捐贈機制協助其建立強大的夥伴生態系統進而發揮平台強大的網絡效應」、「高度目標導向的專案執行並重視績效與考核」、「資源高度有效率運用且以量化為溝通的準則」、「有系統地將內隱經驗轉化為外顯知識」，以及「將企業營運經營管理與公司治理理念導入非營利組織」為其關鍵成功因素。 / Bill & Melinda Gates Foundation has so far donated more than 30 billion US. dollars to fund about 8,000 charitable projects, which benefit those extremely poor areas in the world and save countless lives. It may be deemed as the world's most influential philanthropic organization. However, it is well-known that Bill Gates is not familiar with philanthropy work, but somehow he has leveraged characteristic catalyst to build the partner ecosystem efficiently to attract donations and resources; moreover, he helps the organization to fully utilize the platform’s positive network and lock-in effects to help expanding the scale of the Foundation rapidly. It is known that Gates Foundation with Gate’s leadership is good at maximizing resources’ value. Thus this study aims to identify the business model and the mechanism design of Gates Foundation. It deeply investigates each activity from the platform’s value propositions to find out its key success factors. Meanwhile, it explores this model and how it causes impact on philanthropic industry. This study hopes to provide advice for non-profit organizations so that they could learn from the Bill & Melinda Gates Foundation’s experiences or even mirror some of the original strategic thoughts of its mechanism designs once they decide to develop more aggressively on the philanthropy. The study found the key success factors of Gates Foundation as bellow: •Deep insight and complete analysis on its target markets and customers. •Creative donation mechanisms that helps to form a strong partner ecosystem, and bring positive network effect to the platform. •Goal-oriented project that is highly executed and emphasized on the performance evaluation. •High efficiency on the use of resources and how its value is maximized. •Transfer implicit experience into explicit knowledge & know-how. •Utilize management knowledge & methodology of global enterprise and practice it in philanthropic organization.

O presente trabalho apresenta o conceito de portal urbano rodoviário como a porta de entrada de uma cidade. Analisa portais de seis cidades: Londrina (PR), Jaú (SP), Vitória (ES), Brasília (DF), Cuiabá (MT), e Goiânia (GO), projetados por arquitetos de renome, como Vilanova Artigas, Carlos Maximiliano Fayet, Lucio Costa e Paulo Mendes da Rocha, sua importância para o desenvolvimento da cidade em que se encontra e sua possível descaracterização, pois estudos a respeito dessa apropriação espacial nas edificações públicas projetadas com o cuidado de fornecer ambientes agradáveis ao usuário, merecem destaque entre as publicações da área de arquiteturae urbanismo. Essas análises têm início à luz de um contexto histórico sociocultural em que se ergueram tais portais, no glamour do modernismo e influências das escolas paulista e carioca, envolvendo questões de tipologia entre outras, evoluindo para a realidade atual, na qual algumas edificações se encontram em funcionamento, de acordo com a atividade proposta ainda em projeto, sem deixar de levar em consideração a recente possibilidade de transformação do espaço oferecido por esses edifícios, em razão da ocupação de um centro de lojas e lanchonetes. / The present work introduces the concept of an urban road gate as the main entrance of a city. Therefore, it analyses the gates present in six cities: Londrina(PR), Jaú (SP), Vitória (ES), Brasília (DF), Cuiabá (MT), and Goiânia (GO) which all of them have been designed by famous architects, such as: Vilanova Artigas, Carlos Maximiliano Fayet, Lucio Costa e Paulo Mendes da Rocha. The present study, analyses the importance of the gates to the development of the city in which it was built and its possible mischaracterizing, once it is important that studies are carried regarding the present usage of this typology of building, which was conceived with the purpose of providing pleasurable public spaces to the general population and due to that, these gates deserve distinction among the publications about architecture and urbanism. The studies about the gates start with the understanding of the social cultural context in which they were designed and built, the glamour of modernism and the influences of the architectural production of Rio de Janeiro (RJ) and São Paulo (SP) concerning subjects as typology and others, evolving until the actual situation, where some of the buildings still working and functioning, following the activities proposed in the original design, as well as the recent possibility of transformation of these spaces, due to the creation of a commercial center and food chains.

Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont le "gate-matrix" et le "linear-matrix". L'indépendance vis-à-vis des règles de dessin est obtenue en utilisant la technique de description symbolique (dessin sous une grille unitaire), et les dimensions des transistors sont définies par le concepteur ou par un outil de dimensionnement. Nous proposons une méthode et un prototype logiciel pour la synthèse automatique des masques, en utilisant le style "linear-matrix multi-bander". La description d'entree du générateur est un fichier format SPICE (au niveau transistor), ce qui permet d'avoir un nombre très élevé de cellules, en particulier les portes complexes (A01), et ainsi avoir une meilleure optimisation lors de la phase d'assignation technologique. Les macro-cellules générées doivent être assemblées afin de réaliser un circuit complet. Deux contraintes supplémentaires sont ainsi imposées au générateur: malléabilité de la forme et position des broches d'entrées/sorties sur la périphérie de la macro-cellule. Les macro-cellules sont assemblées en utilisant un environnement de conception industriel. Les contributions de ce mémoire de doctorat sont d'une part le développement d'un générateur de macro-cellules flexible ayant les caracteristiques d'indépendance aux règles de dessin et d'intégration dans un environnement de macro-cellules, et d'autre part l'étude detailée des paramètres qui déterminent la surface occupée, les performances électriques et la puissance dissipée des macro-cellules générées automatiquement. / The main problems of the automatic layout synthesis are the design rules dependence and the transistor sizing. The traditional layout synthesis methods, like standard-cells, are not flexible, since the cells in the libraries are designed and sized for a specific technology. In this way, the designer must change his library at each technology improvement. The automatic layout synthesis methods overcomes these problems (design rules dependence and transistor sizing). Examples of layout styles are gate-matrix and linear-matrix. The technology independence is achieved by symbolic description (layout under an unitary grid), and the transistor sizes are defined by the designer or by a sizing tool. From these two constraints, we develop an automatic layout synthesis tool, using a linear-matrix multi-row layout style. The input description for our tool is a Spice file. This descriptions allows to define a greater number of cells (mainly AOIs gates), resulting a technology mapping with less constraints. The generated macro-cells must be assembled in order to construct a complete circuit. Two additional constraints are then imposed to the generator : variable aspect ratio and placement of the inputs/outputs pins in the macro-cell border. The macro-cells are assembled by an industrial CAD environment. The main contributions of this thesis are the development of a macro-cell generator (with the characteristics of technology independence and easy integration in a macro-cell environment) and the analysis of the parameters playing a role in the area, delay and power consumption.

The historicity of the United Monarchy has recently come under attack. The biblical 'minimalists' say that a reconstruction of ancient Israel is impossible with the sources that we have access to, and the glory and wealth of Solomon's empire is mere fiction. They disregard the Bible as a reliable source, and archaeology because it is mute and open to interpretation. Some scholars have suggested lowering the traditional dates on certain archaeological strata, resulting in an entirely different picture of the tenth century BCE. Other scholars say that the United Monarchy definitely did exist and consider the Bible a valuable historical source. The evidence for the tenth century and the United Monarchy as shown by the Hebrew Bible and archaeology is investigated as well as various key sites in Israel. The conclusion is that the traditional chronology and viewpoint of the United Monarchy still needs to be respected. / Biblical and Ancient Studies / M.A. (Biblical Studies)

O presente trabalho apresenta o conceito de portal urbano rodoviário como a porta de entrada de uma cidade. Analisa portais de seis cidades: Londrina (PR), Jaú (SP), Vitória (ES), Brasília (DF), Cuiabá (MT), e Goiânia (GO), projetados por arquitetos de renome, como Vilanova Artigas, Carlos Maximiliano Fayet, Lucio Costa e Paulo Mendes da Rocha, sua importância para o desenvolvimento da cidade em que se encontra e sua possível descaracterização, pois estudos a respeito dessa apropriação espacial nas edificações públicas projetadas com o cuidado de fornecer ambientes agradáveis ao usuário, merecem destaque entre as publicações da área de arquiteturae urbanismo. Essas análises têm início à luz de um contexto histórico sociocultural em que se ergueram tais portais, no glamour do modernismo e influências das escolas paulista e carioca, envolvendo questões de tipologia entre outras, evoluindo para a realidade atual, na qual algumas edificações se encontram em funcionamento, de acordo com a atividade proposta ainda em projeto, sem deixar de levar em consideração a recente possibilidade de transformação do espaço oferecido por esses edifícios, em razão da ocupação de um centro de lojas e lanchonetes. / The present work introduces the concept of an urban road gate as the main entrance of a city. Therefore, it analyses the gates present in six cities: Londrina(PR), Jaú (SP), Vitória (ES), Brasília (DF), Cuiabá (MT), and Goiânia (GO) which all of them have been designed by famous architects, such as: Vilanova Artigas, Carlos Maximiliano Fayet, Lucio Costa e Paulo Mendes da Rocha. The present study, analyses the importance of the gates to the development of the city in which it was built and its possible mischaracterizing, once it is important that studies are carried regarding the present usage of this typology of building, which was conceived with the purpose of providing pleasurable public spaces to the general population and due to that, these gates deserve distinction among the publications about architecture and urbanism. The studies about the gates start with the understanding of the social cultural context in which they were designed and built, the glamour of modernism and the influences of the architectural production of Rio de Janeiro (RJ) and São Paulo (SP) concerning subjects as typology and others, evolving until the actual situation, where some of the buildings still working and functioning, following the activities proposed in the original design, as well as the recent possibility of transformation of these spaces, due to the creation of a commercial center and food chains.

Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont le "gate-matrix" et le "linear-matrix". L'indépendance vis-à-vis des règles de dessin est obtenue en utilisant la technique de description symbolique (dessin sous une grille unitaire), et les dimensions des transistors sont définies par le concepteur ou par un outil de dimensionnement. Nous proposons une méthode et un prototype logiciel pour la synthèse automatique des masques, en utilisant le style "linear-matrix multi-bander". La description d'entree du générateur est un fichier format SPICE (au niveau transistor), ce qui permet d'avoir un nombre très élevé de cellules, en particulier les portes complexes (A01), et ainsi avoir une meilleure optimisation lors de la phase d'assignation technologique. Les macro-cellules générées doivent être assemblées afin de réaliser un circuit complet. Deux contraintes supplémentaires sont ainsi imposées au générateur: malléabilité de la forme et position des broches d'entrées/sorties sur la périphérie de la macro-cellule. Les macro-cellules sont assemblées en utilisant un environnement de conception industriel. Les contributions de ce mémoire de doctorat sont d'une part le développement d'un générateur de macro-cellules flexible ayant les caracteristiques d'indépendance aux règles de dessin et d'intégration dans un environnement de macro-cellules, et d'autre part l'étude detailée des paramètres qui déterminent la surface occupée, les performances électriques et la puissance dissipée des macro-cellules générées automatiquement. / The main problems of the automatic layout synthesis are the design rules dependence and the transistor sizing. The traditional layout synthesis methods, like standard-cells, are not flexible, since the cells in the libraries are designed and sized for a specific technology. In this way, the designer must change his library at each technology improvement. The automatic layout synthesis methods overcomes these problems (design rules dependence and transistor sizing). Examples of layout styles are gate-matrix and linear-matrix. The technology independence is achieved by symbolic description (layout under an unitary grid), and the transistor sizes are defined by the designer or by a sizing tool. From these two constraints, we develop an automatic layout synthesis tool, using a linear-matrix multi-row layout style. The input description for our tool is a Spice file. This descriptions allows to define a greater number of cells (mainly AOIs gates), resulting a technology mapping with less constraints. The generated macro-cells must be assembled in order to construct a complete circuit. Two additional constraints are then imposed to the generator : variable aspect ratio and placement of the inputs/outputs pins in the macro-cell border. The macro-cells are assembled by an industrial CAD environment. The main contributions of this thesis are the development of a macro-cell generator (with the characteristics of technology independence and easy integration in a macro-cell environment) and the analysis of the parameters playing a role in the area, delay and power consumption.

Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont le "gate-matrix" et le "linear-matrix". L'indépendance vis-à-vis des règles de dessin est obtenue en utilisant la technique de description symbolique (dessin sous une grille unitaire), et les dimensions des transistors sont définies par le concepteur ou par un outil de dimensionnement. Nous proposons une méthode et un prototype logiciel pour la synthèse automatique des masques, en utilisant le style "linear-matrix multi-bander". La description d'entree du générateur est un fichier format SPICE (au niveau transistor), ce qui permet d'avoir un nombre très élevé de cellules, en particulier les portes complexes (A01), et ainsi avoir une meilleure optimisation lors de la phase d'assignation technologique. Les macro-cellules générées doivent être assemblées afin de réaliser un circuit complet. Deux contraintes supplémentaires sont ainsi imposées au générateur: malléabilité de la forme et position des broches d'entrées/sorties sur la périphérie de la macro-cellule. Les macro-cellules sont assemblées en utilisant un environnement de conception industriel. Les contributions de ce mémoire de doctorat sont d'une part le développement d'un générateur de macro-cellules flexible ayant les caracteristiques d'indépendance aux règles de dessin et d'intégration dans un environnement de macro-cellules, et d'autre part l'étude detailée des paramètres qui déterminent la surface occupée, les performances électriques et la puissance dissipée des macro-cellules générées automatiquement. / The main problems of the automatic layout synthesis are the design rules dependence and the transistor sizing. The traditional layout synthesis methods, like standard-cells, are not flexible, since the cells in the libraries are designed and sized for a specific technology. In this way, the designer must change his library at each technology improvement. The automatic layout synthesis methods overcomes these problems (design rules dependence and transistor sizing). Examples of layout styles are gate-matrix and linear-matrix. The technology independence is achieved by symbolic description (layout under an unitary grid), and the transistor sizes are defined by the designer or by a sizing tool. From these two constraints, we develop an automatic layout synthesis tool, using a linear-matrix multi-row layout style. The input description for our tool is a Spice file. This descriptions allows to define a greater number of cells (mainly AOIs gates), resulting a technology mapping with less constraints. The generated macro-cells must be assembled in order to construct a complete circuit. Two additional constraints are then imposed to the generator : variable aspect ratio and placement of the inputs/outputs pins in the macro-cell border. The macro-cells are assembled by an industrial CAD environment. The main contributions of this thesis are the development of a macro-cell generator (with the characteristics of technology independence and easy integration in a macro-cell environment) and the analysis of the parameters playing a role in the area, delay and power consumption.

An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.