Made available in DSpace on 2014-06-12T16:01:00Z (GMT). No. of bitstreams: 2 arquivo7128_1.pdf: 2072446 bytes, checksum: b6bc5386371d917bd7613b206ac8e92f (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005 / A demanda cada vez maior por produtos eletronicos e a crescente capacidade de integração dos chips direcionaram a metodologia de projeto de sistemas embarcados para sua completa integração em um único chip ( System-on-Chip, ou SoC). Essa metodologia baseia-se cada vez mais em componentes previamente projetados e verificados (IP-core ) como uma alternativa de disponibilizar os sistemas dentro dos prazos esperados, sem perder o time-to-market do mercado consumidor de eletrônicos. Neste trabalho, é proposto um processo de desenvolvimento de IP-cores baseado em técnicas de engenharia de software chamado ipPROCESS, como um mecanismo de facilitar e promover o desenvolvimento de IP-cores de alta qualidade. Tendo o foco na criação de componentes de qualidade, o ipPROCESS foi definido com base em técnicas de verificação funcional, de modelagem visual da arquitetura, de interface de comunicação e de documentação seguindo os padrões da indústria. O processo foi descrito utilizando o meta-modelo UML denominado SPEM com o objetivo de facilitar e acelerar o seu entendimento, assim como permitir alterações futuras e facilitar o gerenciamento de projetos baseados no processo proposto

A crescente demanda por produtos eletrônicos e a capacidade cada vez maior de integração criaram sistemas extremamente complexos em chips, conhecidos como Systemon-Chip ou SoC. Seguindo em sentido oposto a esta tendência, os prazos (time-to-market) para que estes sistemas sejam construídos vem continuamente sendo reduzidos, obrigando que muito mais funcionalidades sejam implementadas em períodos cada vez menores de tempo. A necessidade de um maior controle de qualidade do produto final demanda a atividade de Verificação Funcional que consiste em utilizar um conjuntos de técnicas para estimular o sistema em busca de falhas. Esta atividade é a extremamente dispendiosa e necessária, consumindo até cerca de 80% do custo final do produto. É neste contexto que se insere este trabalho, propondo uma metodologia de Verificação Funcional chamada IVM que irá fornecer todos os subsídios para garantir a entrega de sistemas de alta qualidade, e ainda atingindo as rígidas restrições temporais impostas pelo mercado. Sendo baseado em metodologias já bastante difundidas e acreditadas, como o OVM e o VeriSC, o IVM definiu uma organização arquitetural e um fluxo de atividades que incorporou as principais características de ambas as abordagens que antes estavam disjuntas. Esta integração de técnicas e conceitos resulta em um fluxo de verificação mais eficiente, permitindo que sistemas atinjam o custo, prazo e qualidade esperados._________________________________________________________________________________________ ABSTRACT: The growing demand for electronic devices and its even higher integration capability created extremely complex systems in chips, known as System-on-Chip or SoC. In a opposite way to this tendency, the time-to-market for these systems be built have been continually reduced, forcing much more functionalities be implemented in even shorten time periods. The final product quality control is assured by the Functional Verification activity that consists in a set of techniques to stimulate a system in order to find bugs. This activity is extremely expensive and necessary, responding to around 80% of final product cost. In this context this work is inserted on, proposing a Functional Verification methodology called IVM that will provide all conditions to deliver high quality systems, while keeping the hard time restrictions imposed by the market. Based in well known and trusted methodologies, as OVM and VeriSC, the IVM defined an architectural organization and an activity flow that incorporates features of both approaches that were separated from each other. This techniques and concepts integration resulted in a more efficient verification flow, allowing systems to meet the desired budget, schedule and quality.

The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process. An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug. Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation. This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test. Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored. The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.

In this paper, a state of charge (SOC) and a state of health (SOH) estimation method for lead-acid batteries are presented. In the algorithm the measurements of battery’s terminal voltage, current and temperature are used in the process of SOC calculation. The thesis was written in cooperation with Micropower AB. The algorithm was designed to fulfill the specific requirements of the electric vehicles application: an error below 5% of SOC, computational simplicity and the possibility of being implemented in a basic programming languages. The current used method at Micropower, Coulomb counting, is compared with a method presented by Chiasson and Vairamohan 2005 based on modified Thevein circuit during charging and discharging of the battery. The Thevenin based method gave better result compared to Coulomb counting but seems not to fulfill Micropowers requirements. A correction method based on periods of no charging or discharging, possible to be used together with Coulomb counting as well as with the Thevenin method was developed. The evaluation method indicates that when using also the correction method the Micropowers requirements are fulfilled. / I detta papper, är ett laddningstillstånd (SOC) och hälsotillstånd (SOH) skattningsmetod för blybatterier presenteras. I algoritmen mätningarna av batteriets polspänning, ström och temperatur används i processen för SOC beräkning. Avhandlingen är skriven i samarbete med Micropower AB. Algoritmen har utformats för att uppfylla de särskilda kraven för elektriska fordon: ett fel under 5% av SOC, computational enkelhet och möjligheten att genomföras i ett grundläggande programmeringsspråk. Den nuvarande metoden vid Micropower, Coulomb räkning, jämförs med en metod som presenteras av Chiasson och Vairamohan 2005 baserad på modifierad Thevein kretsen under laddning och urladdning av batteriet.

L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

In an extension of Louden's work, this study investigated identity development across the lifespan by applying Erickson's and Marcia's identity constructs to two developmental models, the selective optimization and compensation model and a holistic wellness model. Data was gathered from traditionally aged college freshmen and adults older than 60 years of age. Uncommitted identity statuses and work and leisure wellness domains were endorsed across both groups, suggesting that identity for these groups is in a state of fluctuation yet entailing participation as a productive member of society. Emerging adult findings imply that identity diffused and moratorium identity styles are more similar in terms of cognitive, behavioral, and emotional functioning than past literature suggests for this age group. Findings also indicate that identity development is not a process completed by older adulthood, but is an ongoing, lifelong process perhaps driven by contextual factors such as health changes, unpredictable life events, social support group changes, and others. Coping method utilization and overall wellness varied between the two age groups. Conceptually, the SOC model can be viewed as embedded within each of the wellness domains such that selection, optimization, and compensation activities may be carried out within each of the various domains and serve to enhance existing functioning within each domain rather than simply compensating for lost functioning. Possible explanations of the results as well as implications for clinical practice, higher education, and future research are provided.

Orientadores: Eleri Cardozo, Eliane Gomes Guimarães / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T01:18:40Z (GMT). No. of bitstreams: 1 Coelho_PauloRodolfodaSilvaLeite_M.pdf: 3632525 bytes, checksum: 73b0d774d1efd6416d8fb34cc8abd4d7 (MD5) Previous issue date: 2006 / Resumo: Este trabalho apresenta uma arquitetura para a construção de laboratórios de acesso remoto (conhecidos como WebLabs). A arquitetura segue o paradigma de computação orientada a serviço (COS). Nesta abordagem cada recurso físico ou lógico do laboratório é modelado como um Serviço Web. Desta forma, os experimentos podem ser disponibilizados pela composição destes serviços. Um modelo conceitual para WebLabs, bem como a implementação deste modelo são apresentados. Experimentos em robótica móvel também foram desenvolvidos como exemplos de utilização deste laboratório / Abstract: This work presents an architeture for building remote access laboratories (also known as WebLabs). The architecture follows the service oriented computing (SOC). In this approach each logical or physical resource of the laboratory is modeled as a Web Service. In this way, the experiments are built through the composition of such services. A conceptual model of WebLabs, as well as an implementation of this model are presented. Experiments in mobile robotic were also developed for this laboratory / Mestrado / Engenharia de Computação / Mestre em Engenharia Elétrica

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This projects describes the design of communication between SHARC and ARM cores on ADSP-SC58x platform, concretely between bare-metal and Linux applications on ADSP-SC589 chips. There are outlined several available technologies for data transfer, such as MCAPI, MDMA or shared memory. There are also designed and implemented new communication principes based on current implementations of these technologies.