В данной работе представлена разработка схемы управления зеркальными антеннами 600 метрового радиотелескопа на основе цифровой обработки сигналов. Был произведен анализ диаграммы направленности радиотелескопа при цифровом методе формирования, а также оценено влияние фазовых ошибок на диаграмму направленности радиотелескопа, возникающих в процессе оцифровке аналогового сигнала на несущей частоте. Было произведено математическое моделирование и оценка влияния параметров цифровой элементной базы на характеристики диаграммы направленности радиотелескопа, предложено оборудование для построения диаграммообразующей схемы радиотелескопа. / This work contains the development of a control scheme for mirror antennas of a 600-meter radio telescope based on digital signal processing. An analysis was made of the radiation pattern of the radio telescope under the digital method of formation. The influence of phase errors on the radiation pattern of the radio telescope, which arise in the process of digitizing an analog signal at a carrier frequency, was estimated. Mathematical modeling and estimation of the effect of the parameters of the digital element base on the characteristics of the radiation pattern of the radio telescope were made, equipment for constructing a radio telescope was proposed.

Le convertisseur analogique-numérique (ADC), fait fonction d’interface entre les domaines de représentation analogique et numérique des systèmes mixtes de traitement du signal.Il est un élément central en cela que ses performances circonscrivent celles des traitements numériques qui lui succèdent et a fortiori celles de son dispositif hôte. C’est notamment le casdes récepteurs radioélectriques numériques à large bande instantanée. De fait, ces systèmes voient leurs performances de dynamiques instantanées monotonale (DTDR) et bitonale (STDR)– i.e. leur capacité à traiter simultanément des composantes de faible puissance en présence d’une ou plusieurs autres composantes de plus forte puissance – limitées par la linéarité de leur ADC.Ce dernier caractère est quantifié par les performances de dynamique sans raies parasites (SFDR)et distorsion d’intermodulation (IMD) d’un ADC.Les critères de DTDR et de STDR sont essentiels pour les récepteurs radios numériques de guerre électronique conçus pour le traitement des signaux de radiocommunications. En effet, ces dispositifs sont employés à l’établissement de la situation tactique de l’environnement électromagnétique à des fins de support de manoeuvres militaires. La fidélité de la représentation numérique du signal analogique reçu est donc critique. Ainsi, cette thèse vise à étudier la linéarisation des ADC, i.e. l’augmentation des SFDR et IMD, en vue de l’amélioration des dynamiques instantanées de ces récepteurs.Dans ce manuscrit, nous traitons cette problématique selon deux axes différents. Le premier consiste à corriger les distorsions introduites par un ADC au moyen de tables de correspondances(LUT) pré-remplies. À cette fin, nous proposons un algorithme de remplissage de LUT procédant d’une méthode de la littérature par la réduction de moitié du nombre de coefficients à déterminer pour estimer la non-linéarité intégrale (INL) d’un ADC. Sur la base de cette nouvelle méthode,nous développons une approche de correction des non-linéarités dynamiques introduites par un ADC reposant sur une paire de LUT statiques et présentons un exemple d’algorithme permettant de l’opérer. Le second axe du manuscrit repose sur la modélisation comportementale de l’ADC par les séries de Volterra à temps discrets et leurs dérivés. En premier lieu, nous considérons les trois problématiques fondamentales de cette approche de linéarisation : la modélisation ;l’identification de modèle ; et l’inversion de modèle. Puis, nous définissons trois solutions de linéarisation d’ADC aveugles. Enfin, nous analysons l’implémentation sur circuits à réseaux logiques programmables (FPGA) de l’un de ces algorithmes afin d’évaluer la pertinence d’uneopération en temps-réel des échantillons de sortie d’un ADC échantillonnant à une fréquence d’environ 400 MHz. / The analog-to-digital converter (ADC) is a central component of mixed signal systems as the interface between the analog and digital representation spaces. Its performance bounds that of the device it is integrated in. Indeed, ADC linearity is essential for maintaining in the digital space the reliability of its input signal and then that of the information it carries.Wideband digital radio receivers are particularly sensitive to ADC non-linearities. Single-tone and dual-tone dynamic range (respectively STDR and DTDR) of such systems – i.e. the abilityto process simultaneously signal components with high power ratio – are limited by the spurious free dynamic range (SFDR) and intermodulation distortion (IMD) of their internal ADC.DTDR et de STDR are key metrics for electronic warfare wideband digital radio receivers developed for radiocommunication signal processing. As a matter of fact, these equipments are employed for analyzing the tactical situation of the radiofrequency spectrum in order to support military maneuvers. Hence, signal integrity is critical. This thesis deals with the ADC linearization issue in this context. Thus, it aims to study techniques for increasing ADC SFDRand IMD for the purpose of improving dynamic ranges of electronic warfare wideband digitalr eceivers.In this dissertation, the problematic of ADC linearization is approached in two different ways.On the one hand, we consider distortion compensation using pre-filled look-up tables (LUT). Wepropose an algorithm for filling LUTs that stems from an existing method by halving the numberof coefficients required for the integral non-linearity (INL) estimation. Then, based on this new method, we develop an approach for correcting ADC dynamic non-linearities using a couple ofstatic LUTs and we present an example of algorithm for operating this method. On the other hand,we study linearization solutions that rely on behavioural modelling of ADCs using discrete-time Volterra series and its derivatives. First, we address the three fundamental issues of this approach:modelling ; model identification ; and model inversion. Then, we propose three blind linearization algorithms. Finally, we consider the implementation on field programmable gate array (FPGA) of one of them for the purpose of evaluating the relevance of real-time linearization of an ADC sampling at about 400 MHz.

L’ évolution des systèmes radar et de guerre électronique tend à concevoir desrécepteurs numériques possédant des bandes instantanées de plus en plus larges. Cette contraintese reporte sur les Convertisseurs Analogique-Numérique (CAN) qui doivent fournir une fréquenced’échantillonnage de plus en plus élevée tout en conservant une puissance dissipée réduite. Unesolution pour répondre à cette demande est le CAN à Temps Entrelacés (ET-CAN) qui paralléliseM CANs pour augmenter la fréquence d’échantillonnage d’un facteur M tout en restant dansun rapport proportionné avec la puissance dissipée. Cependant, les performances dynamiquesdes ET-CANs sont réduites par des défauts d’entrelacements liés à des différences de processusde fabrication, de leur tension d’alimentation et des variations de température. Ces défautspeuvent être modélisés comme issus des disparités d’offsets, de gains ou décalages temporels etglobalement comme issus des disparités de réponses fréquentielles. Ce sont sur ces dernièresdisparités, moins traitées dans la littérature, que portent nos travaux. L’objectif est d’étudierces disparités pour en déduire un modèle et une méthode d’estimation puis, de proposer desméthodes de compensation numérique qui peuvent être implémentées sur une cible FPGA.Pour cela, nous proposons un modèle général des disparités de réponses fréquentielles desET-CANs pour un nombre de voies M quelconques. Celui-ci mélange une description continuedes disparités et une description discrète de l’entrelacement, résultant sur une expression desdéfauts des ET-CANs comme un filtrage à temps variant périodique (LPTV) du signal analogiqueéchantillonné uniformément. Puis, nous proposons une méthode d’estimation des disparitésdes ET-CANs basée sur les propriétés de corrélation du signal en sortie du modèle, pour Mvoies quelconques. Ensuite, nous définissions une architecture de compensation des disparitésde réponses fréquentielles des ET-CANs et nous étudions ses performances en fonction de sesconfigurations et du signal en entrée. Nous décrivons une implémentation de cette architecturepour M=4 voies entrelacées sur cible FPGA et nous étudions les ressources consommées afin deproposer des pistes d’optimisation. Enfin, nous proposons une seconde méthode de compensationspécifique au cas M=2 voies entrelacées, dérivée de la première mais travaillant sur le signalanalytique en sortie d’un ET-CAN et nous la comparons à une méthode similaire de l’état del’art. / The evolution of radar and electronic warfare systems tends to develop digitalreceivers with wider bandwidths. This constraint reaches the Analog to Digital Converters(ADC) which must provide a sample rate higher and higher while maintaining a reducedpower dissipation. A solution to meet this demand is the Time-Interleaved ADC (TIADC)which parallelizes M ADCs, increasing the sampling frequency of an M factor while still ina proportionate relation to the power loss. However, the dynamic performance of TIADCsare reduced by errors related to the mismatches between the sampling channels, due to themanufacturing processes, the supply voltage and the temperature variations. These errors canbe modeled as the result of offset, gain and clock-skew mismatches and globally as from thefrequency response mismatches. It is these last mismatches, unless addressed in the literaturethat carry our work. The objective is to study these errors to derive a model and an estimationmethod then, to propose digital compensation methods that can be implemented on a FPGAtarget.First, we propose a general TIADC model using frequency response mismatches for any Mchannel number. Our model merge a continuous-time description of mismatches and a discretetimeone of the interleaving process, resulting in an expression of the TIADC errors as a linearperiodic time-varying (LPTV) system applied to the uniformly sampled analog signal. Then,we propose a method to estimate TIADC errors based on the correlation properties of theoutput signal for any M channel. Next, we define a frequency response mismatch compensationarchitecture for TIADC errors and we study its performance related to its configuration and theinput signal. We describe an FPGA implementation of this architecture for M=4 interleavedchannels and we study the resources consumption to propose optimisations. Finally, we proposea second compensation method, specific to M=2 interleaved channels and derived from the firstone, but working on the analytical signal from the TIADC output and we compare it to a similarstate-of-the-art method.

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification. / Graduation date: 2012 / Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range. / <p>QC 20170905</p>

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.

The aim of the thesis is the design and realization of the oscilloscope module with wireless data transfer. One part of the thesis is a short overview of the different types of AD converters. The main part is focused on the hardware configuration that allows modification of the wireless module of the oscilloscope, and the possibility of using in the industrial zone. The design takes into account reducing of consumption and EMC compatibility.

With the rapid development of mobile communication, sensors, and biomedical in recent years, the demand for accurate data information, highquality audio and image has become much more significant, which requires a high-precision Analog to Digital Converter (ADC) to process weak analog signals. As one of the core modules of ADC, the comparator’s precision, speed, stability, and noise play a key role in the performance of the whole circuit. Over the years, those performance has been improved a lot by both designing new architectures and using advanced fabrication technology. However, the conventional comparators occupy 50%-60% of the total energy consumption of EPC, even with advanced technology and lower supply voltage. In this thesis, a new type of energy-efficient comparator, called Edge-Pursuit Comparator (EPC), is proposed, which satisfies the need for low comparison energy. The design of EPC is based on a ring oscillator, when the EPC enters the evaluation mode, two signal edges with different propagation delays will chase in it until one overlaps the other, and finally generate a stable voltage level in each output node. The circuit is built and simulated in Cadence Virtuoso using cmos22fdsoi technology. The simulation results reveal that the energy consumed per comparison is dependent on the input differential voltage, and it can be as low as 7 fJ when vin = 50 mV, which is around ten times smaller compared with conventional comparators. In addition, as the power consumption is considerable when the two input voltages are very close, a promising improvement is applied to EPC, namely connecting every node with a variable capacitor, which is called Edge-Pursuit Comparator enhanced with Capacitor (EPCC). Cadence simulation results prove that EPCC can largely lower the energy consumption under a small vin while keeping input-referred noise the same. Therefore, a combination of EPC and EPCC is expected to have prospective applications in the energy-efficient area. / Med den snabba utvecklingen av mobil kommunikation, sensorer och biomedicin under de senaste åren har efterfrågan på korrekt datainformation, högkvalitativt ljud och bild blivit mycket mer betydande, vilket kräver en högprecision Analog till Digital Converter (ADC) för att bearbeta svaga analoga signaler. Som en av ADC:s kärnmoduler spelar komparatorns precision, hastighet, stabilitet och brus en nyckelroll i prestanda för hela kretsen. Under årens lopp har dessa prestanda förbättrats mycket genom att både designa nya arkitekturer och använda avancerad tillverkningsteknik. De konventionella komparatorerna upptar dock 50%-60% av den totala energiförbrukningen för EPC, även med avancerad teknik och lägre matningsspänning. I detta examensarbete föreslås en ny typ av energieffektiv komparator, kallad Edge-Pursuit Comparator (EPC), som tillgodoser behovet av låg jämförelseenergi. Designen av EPC är baserad på en ringoscillator, när EPC:n går in i utvärderingsläget kommer två signalkanter med olika utbredningsfördröjningar att jaga i den tills den ena överlappar den andra, och slutligen generera en stabil spänningsnivå i varje utgångsnod. Kretsen är byggd och simulerad i Cadence Virtuoso med hjälp av cmos22fdsoiteknik. Simuleringsresultaten visar att energiförbrukningen per jämförelse är beroende av ingångsdifferensspänningen och den kan vara så låg som 7 fJ när vin = 50 mV, vilket är cirka tio gånger mindre jämfört med konventionella komparatorer. Dessutom, eftersom strömförbrukningen är avsevärd när de två inspänningarna är mycket nära, tillämpas en lovande förbättring på EPC, nämligen att ansluta varje nod med en variabel kondensator, som kallas Edge-Pursuit Comparator förbättrad med kondensator (EPCC). Kadenssimuleringsresultat bevisar att EPCC till stor del kan sänka energiförbrukningen under en liten vin samtidigt som ingångsreferat buller hålls detsamma. Därför förväntas en kombination av EPC och EPCC ha potentiella tillämpningar inom det energieffektiva området.