The popularity of the internal combustion engine (ICE) vehicles has contributed to global warming problem and degradation of air quality around the world. Furthermore, the vehicles??? massive demand on gas has played a role in the depletion of fossil fuel reserves and the considerable rise in the gas price over the past twenty years. Those existing challenges force the auto-industry to move towards the technology development of vehicle electrification. An electrified vehicle is driven by one or more electric motors. And the electricity comes from the onboard energy storage system (ESS). Currently, no single type of green energy source could meet all the requirements to drive a vehicle. A hybrid energy storage system (HESS), as a combination of battery and ultra-capacitor units, is expected to improve the overall performance of vehicles??? ESS. This thesis focuses on the design of HESS and the development of a HESS prototype for electric vehicles (EVs) and hybrid electric vehicles (HEVs). Battery unit (BU), ultra-capacitor unit (UC) and a DC/DC converter interfacing BU and UC are the three main components of HESS. The research work first reviews literatures regarding characteristics of BU, UC and power electronic converters. HESS design is then conducted based on the considerations of power capability, energy efficiency, size and cost optimization. Besides theoretical analysis, a HESS prototype is developed to prove the principles of operation as well. The results from experiment are compared with those from simulation.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Protection systems used in distribution networks of electricity are not able to detect short circuits with high contact resistance due to the low currents generated, endangering the population and degrading the quality of the energy supplied. In this sense, this paper presents a new methodology for detecting high-impedance faults (HIF) in distribution networks. The developed algorithm has the main advantage the fact also detect and classify other types of transient as, for example, switching capacitor banks, transformers and loads. This characteristic decreases the improper operation caused by transient switching. Another feature of the developed method is no need to install additional equipment on the network which greatly reduces the cost of implementation. Additionally, the paper also discusses the causes, consequences and characteristics of HIF in order to evidence the difficulties related to their detection. A brief review of the models proposed in the literature for computational simulation of HIF is also discussed, and the model used in this work is described in detail. To evaluate the performance of the algorithm developed a series of tests with different fault scenarios high impedance were made. Furthermore, other various types of transients that are normal in the feeders were tested. The good results obtained, combined the simplicity of the method and does not need to install additional equipment feeders, makes a promising technique for real applications. / Os sistemas de proteção utilizados em redes de distribuição de energia elétrica não são capazes de detectar curtos-circuitos com alta resistência de contato devido às reduzidas correntes geradas, colocando em risco a população e degradando a qualidade da energia fornecida. Neste sentido, este trabalho visa apresentar uma nova metodologia para detecção de faltas de alta impedância (FAI) em redes de distribuição de energia elétrica. O algoritmo desenvolvido possui como principal vantagem o fato de também detectar e classificar outros tipos de transitórios como, por exemplo, chaveamento de banco de capacitores, transformadores e manobras de ramais. Essa característica diminui consideravelmente as atuações indevidas causadas por transitórios oriundos de manobras. Outra característica do método desenvolvido é a não necessidade de instalação de equipamentos adicionais na rede, o que reduz consideravelmente o custo de sua implementação. Além disso, o trabalho também aborda as causas, consequências e características das FAI de forma a evidenciar as dificuldades relacionadas à sua detecção. Uma breve revisão sobre os modelos propostos na literatura para simulação computacional de FAI também é abordado, sendo que o modelo utilizado nesse trabalho é descrito em detalhes. Para avaliar o desempenho do algoritmo desenvolvido, uma série de testes com diferentes cenários de falta de alta impedância foram realizados. Além disso, outros tipos de transitórios que são normais nos alimentadores foram testados. Os bons resultados obtidos, aliado a simplicidade do método e a não necessidade de instalação de equipamentos adicionais nos alimentadores, torna a técnica promissora para aplicações reais.

This work presents a high performance digital controller of a single phase PWM sinusoidal inverter, using a 16-bits fixed point DSP. This converter is typically used in UPS (Uninterruptible Power Supplies), where a sinusoidal output voltage is desired. The digital controller has an internal filter capacitor current loop, and an external output voltage loop. Experimental results showing the performance of the system under linear and non-linear loads are presented, where a low total harmonic distortion (THD) is achieved. / Este trabalho apresenta um controlador digital de alto desempenho para um inversor PWM senoidal monofásico, usando um processador digital de sinais de 16 bits, ponto fixo. Esta topologia é tipicamente utilizada em sistemas UPS ( Uninterruptible Power Supplies ), onde uma tensão de saída senoidal é desejada. O controlador digital proposto consiste numa malha interna de realimentação da corrente do capacitor do filtro de saída, uma malha externa de realimentação da tensão de saída. Resultados experimentais mostrando o desempenho do sistema para cargas lineares e não-lineares são apresentados, onde uma baixa distorção harmônica total (THD) é observada, e é demonstrada uma elevada rigidez dinâmica da tensão de saída para transientes de carga. / Mestre em Ciências

In this thesis, controllers for power oscillation damping, transient stability improvement and power flow control by means of a Controlled Series Compensator (CSC) and and a Dynamic Power Flow Controller (DPFC) are proposed. These devices belong to the group of power system components referred to as Flexible AC Transmission System (FACTS) devices. The developed controllers use only quantities measured locally at the FACTS device as inputs, thereby avoiding the risk of interrupted communications associated with the use of remote signals for control. For power systems with one dominating, poorly damped inter-area power oscillation mode, it is shown that a simple generic system model can be used as a basis for damping- and power flow control design. The model for control of CSC includes two synchronous machine models representing the two grid areas participating in the oscillation and three reactance variables, representing the interconnecting transmission lines and the FACTS device. The model for control of DPFC is of the same type but it also includes the phase shift of the internal phase-shifting transformer of the DPFC. The key parameters of the generic grid models are adaptively set during the controller operation by estimation from the step responses in the FACTS line power to the changes in the line series reactance inserted by the FACTS device. The power oscillation damping controller is based on a time-discrete, non-linear approach which aims to damp the power oscillations and set the desired power flow on the FACTS line by means of two step changes in the line reactance separated in time by half an oscillation cycle. A verification of the proposed controllers was done by means of digital simulations using power system models of different complexities. The CSC and DPFC controllers were shown to significantly improve the small-signal- and transient stability in one four-machine system of a type commonly used to study inter-area oscillations. The CSC controller was also tested for 18 different contingencies in a 23-machine system, resulting in an improvement in both the system transient stability and the damping of the critical oscillation mode. / QC 20101112

Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / AFRIKAANSE OPSOMMING: Hierdie proefskrif handel oor die natuurlike balanserings meganismes van veelvlakkige en modulêre omsetters wat fase-skuif dragolf puls wydte modulasie gebruik. Die meganismes kan in twee hoof groepe verdeel word: ‘n swak balanserings meganisme wat afhanklik is van die oorvleuling van die skakelfunksies en ‘n sterk meganisme wat voorkom ongeag of die skakelfunksies oorvleul al dan nie. Die sterk meganisme verdeel verder in twee subgroepe, ‘n direkte oordrag van onbalans energie en ‘n meganisme wat afhang van die verliese in die stelsel. Elkeen van die meganismes word aan die hand van ‘n omsetter topologie waarin die spesifieke meganisme oorheers beskryf en ontleed. In die ondersoek word klem geplaas op die daarstelling van uitdrukkings om die tydskonstantes van herbalansering na ’n afwyking vir elk van die omsetter toplologieë te beskryf. / ENGLISH ABSTRACT: This thesis investigates the natural balancing mechanisms in multilevel and modular converters using phase shifted carrier pulse width modulation. Two groups of mechanisms are identified; a weak balancing mechanism that is only present when the switching functions are interleaved and a strong mechanism that occurs irrespective of the interleaving of the switching functions. It is further shown that the strong balancing mechanism can be divided into a balancing mechanism that depends on the direct exchange of unbalance energy and a loss based balancing mechanism. Each of the mechanisms is discussed and analysed using a converter where the specific mechanism dominates as example. Emphasis is placed on the calculation of the rebalancing time constant following a perturbation. Closed form expressions for the rebalancing time constants for each of the analysed converters are presented.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2011. / ENGLISH ABSTRACT: This thesis investigates the viability of constructing a solid-state transformer (SST) with a series-input, parallel-output connection of full-bridge, three-level ying-capacitor converters. It focusses on the active recti er front-end of the SST which is used to control the input current to be sinusoidal and in-phase with the sinusoidal input voltage. A stack of two converters are built and tested. The input current, as well as the ying capacitor voltages of the two active recti ers in the stack, are actively controlled by a nite-state model-based predictive (FS-MPC) controller. The use of multiple ying-capacitor converters poses a problem when using FS-MPC because of the large number of possible switching states to include in the prediction equations. Three FS-MPC control algorithms are proposed to attempt to overcome the problem associated with the large number of switching states. They are implemented on an FPGA digital controller. The algorithms are compared on the bases of voltage and current errors, as well as their responses to disturbances that are introduced into the system. The simulation and experimental results that are presented shows that by interleaving the control actions for the two converters, one can obtain fast and robust responses of the controlled variables. The viability of extending the interleaving control algorithm beyond two converters is also motivated. / AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlikheid van volbrug, drievlak vlieënde-kapasitoromsetters wat gebruik word om 'n serie-intree, parallel-uittree drywingselektroniese transformator (DET) te bou. Dit fokus op die aktiewe gelykrigter van die DET wat gebruik word om die intreestroom te beheer om sinusvormig en in fase met die sinusvormige intreespanning te wees. 'n Stapel van twee omsetters word gebou en getoets. Die intreestroom, sowel as die vlieënde kapasitorspannings van die twee aktiewe gelykrigters in die stapel, word aktief beheer met behulp van 'n eindige-toestand, model-gebaseerde voorspellende beheerder (ET-MVB). Die gebruik van veelvuldige vlieënde-kapasitoromsetters bemoeilik die implementering van 'n ET-MVB-beheerder as gevolg van die groot aantal skakeltoestande wat in die voorspellende vergelykings in ag geneem moet word. Drie ET-MVB-algoritmes word voorgestel om te poog om die probleme, wat met die groot aantal skakeltoestande geassosieer word, te oorkom. Die algoritmes word in 'n FPGA digitale verwerker geïmplementeer. Die algoritmes word vergelyk op grond van hul stroom- en spanningsfoute, asook hul reaksie op steurings wat op die stelsel ingevoer word. Die simulasie en praktiese resultate toon dat, deur die beheeraksies vir die twee omsetters te laat oorvleuel, die gedrag van die beheerde veranderlikes vinniger en meer robuust is. Die moontlikheid om die oorvleuelende beheeraksies uit te brei tot meer as twee omsetters word ook gemotiveer.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

This thesis investigates single pole reclosing in series capacitor compensated line. An algorithm is developed to determine the optimal dead time required for single pole reclose of circuit breakers and to reduce the randomness of reclosing time. The algorithm considers conditions of system, fault, voltage zero crossing, arc, and IEEE C37.104-2012 standard de-ionization time. This study also addresses difficulties of single pole reclose operation such as over-voltages at the line, secondary arc extinguishing time, dead time, over-voltages across the series capacitor, and negative sequence current. The system performance is evaluated using a set of metrics based on those operation difficulties. Methods used in the industry such as shunt reactor with the neutral reactor, surge arrester, and MOV are modelled and simulated to capture their effect on the operation difficulties. Comparative analysis is made to rank the effectiveness of each element against difficulties in operating single pole reclosing of circuit breakers.

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.