Os estados emaranhados da luz são de grande importância para protocolos de comunicação quântica. Uma das principais fontes que vem sendo estudada no Laboratório de Manipulação Coerente de Átomos e Luz - LMCAL é o oscilador paramétrico ótico (OPO) no qual, através de processos paramétricos não lineares de segunda e terceira ordem (x(2) e x(3)), são produzidos feixes intensos que apresentam correlações quânticas. Recentemente, o LMCAL vem explorando o processo de mistura de quatro ondas (fenômeno derivado da susceptibilidade de terceira ordem x(3)) como fonte geradora de feixes emaranhados. Inicialmente, foi realizado a partir de células de rubídio e agora, em colaboração com o grupo de pesquisa da Profa. Michal Lipson da Universidade de Columbia, em chips de nitreto de silício (Si3N4); permitindo assim possibilidades de modulação ultra-rápida, confinamento de luz em volumes muito reduzidos, além da ótica não-linear do OPO. O presente projeto visa estudar as propriedades quânticas da luz nos OPOs em chips de silício, permitindo que sistemas muito eficientes em informação clássica possam ser usados também para implementação de protocolos de informação quântica. / Entangled States of light beams are of great importance for quantum communication protocols. One of the most relevant source of such states which is being studied at the Laboratory of Coherent Manipulation of Atoms and Light - LMCAL (in portuguese) is the Optical Parametric Oscillator (OPO) which through second and third order nonlinear parametric processes (x(2) and x(3)) produces intense fields that have quantum correlations. Recently, LMCAL is exploring four-wave mixing (FWM), a third-order nonlinear parametric process, as a source of entangled beams. Initially, on rubidium cells and now, in collaboration with Prof. Michal Lipson from the Columbia University, on silicon nitride (Si3N4) chips; opening a new avenue for ultrafast modulation, light confinement in reduced light volumes, as well as the nonlinear optics of the OPO. This project is intended to study quantum properties of light of on-chip OPOs in order to achieve the integration of these highly efficient devices for implementations of quantum information protocols.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e equações que modelam um circuito são compatíveis com a forma desse problema de otimização. Os receptores para sistemas de comunicação modernos realizam o processo de downconvertion usando uma freqüência intermediária baixa ou diretamente em banda-base. As topologias de receptor Zero-IF e Low-IF são preferidas por sua alta capacidade de integração e baixo consumo de área e de potência. Os filtros analógicos são blocos de composição básicos nesses sistemas. Neste trabalho é desenvolvida uma metodologia de projeto baseada na aplicação de programação geométrica para projeto de filtros Gm-C. A metodologia de projeto foi usada para projetar filtros analógicos complexos e reais para os padrões de comunicação Bluetooth e Zigbee IEEE/802.15.4. Os resultados obtidos mostram que a metodologia de projeto proposta neste trabalho é uma solução efetiva para reduzir o tempo de projeto e otimizar o desempenho de filtros analógicos. / The tendency of the microelectronic market is to integrate in the same chip complete electronic systems, including digital, analog and RF circuits simultaneously. The analog part of those systems represents the bottleneck in the design process. The complexity of analog design makes this one an intuitive and creative process but time expensive. An alternative methodology for analog integrated circuits design is to represent the design as a mathematical optimization problem known as geometric programming. The advantages are: global optimum achieved efficiently, and the possibility of design automation. The main disadvantage, is that all the parameters or equations that characterize a circuit are not compatible with the form of this optimization problem. Modern receivers perform downconvertion of the signal using very low, or zero intermediate frequency. Zero-IF and Low-IF topologies are preferred because of their high integration capabilities, and low area and power consumption. Analog filters are basic building blocks of such systems. In this work, a design methodology based on geometric programming is developed, for automated and optimal design of Gm-C filters. The design methodology was used to design analog complex and real filters for the digital communications standards Bluetooth and Zigbee IEEE/802.15.4. The results show that the design methodology proposed in this work is an effective solution for fast, automated and optimal analog filter design

Un Convertisseur Analogique-Numérique (CAN) pour les applications spatiales en astrophysique et cosmologie a été développé au cours de cette thèse. Cette catégorie de circuits demande des bandes passantes très larges, de très hautes fréquences d'échantillonnage et une faible résolution. L’architecture flash a été retenue pour sa rapidité et sa bande passante. La fréquence d’échantillonnage est de 8GHz. La technologie utilisée est la CMOS 65 nm de chez STMicroeletronics. La conception a été faite en deux phases. Une première qui a amené à un prototype d'un échantillonneur-bloqueur et une deuxième qui a amené au CAN. Les deux prototypes ont été caractérisés et à partir de ces résultats des perspectives d'amélioration pour les nouvelles implémentations ont été retrouvées.Pour atteindre l'objectif final du CAN multi-bits (6-bit sont visés) il a été décidé de dessiner une première version du CAN avec la moitié de la résolution initialement prévue (on passe de 6-bit à 3-bit). L'objectif est de nous permettre d’analyser le comportement des blocs fonctionnels intégrés et ensuite passer à une deuxième voire troisième version pour remplir le cahier des charges initial. / An Analog-to-Digital Converter (ADC) has been developed for astrophysical and cosmological applications. This class of circuits demands, especially in the millimeter wavelength domain, ultra wide bandwidths, ultra high sampling frequencies and a low resolution. The “flash” architecture has been chosen for its speed and bandwidth. This ADC samples at 8Gsps and it has been fabricated in 65nm CMOS technology from STMicroelectornics.The design has been done in two steps. The first was the prototype of a track-and-hold circuit. The second was the ADC. Both circuits have been characterized and from these results some perspectives for further improvements have been proposed.In order to achieve the final goal of the multi-bit ADC (6-bit resolution) we have decided to design a first prototype with half the final resolution, namely a 3-bit resolution ADC. Our idea was, with this first prototype, to conduct a first analysis of the behavior of the integrated functional blocks and, consequently, find the correct improvements required for the ADC final version.

Depuis la première génération de téléphone mobile, de nombreuses fonctions et outils ont été intégrés dans nos terminaux. Il y a vingt ans, nous utilisions nos téléphone pour émettre des appels et envoyer/recevoir des messages. Aujourd’hui, l’accès à internet, la radio, l’appareil photo, des jeux et de la musique sont des fonctionnalités que l’on retrouve dans nos téléphones mobiles.Dans un contexte de téléphonie pouvant adresse plusieurs standards, l’objectif de cette thèse est de concevoir et de réaliser l’implémentation d’une architecture capable d’améliorer la linéarité de notre émetteur pour le standard 3G, utilisant des composants analogiques et numériques. Pour cela, notre étude se concentrera sur l’amélioration de la linéarité, tout en maintenant une consommation la plus faible possible mais également tout en évitant d’augmenter la taille d’une puce 3G. Nous allons démontrer qu’il est possible d’intégrer une technique de linéarisation tout en maintenant une consommation et une surface en silicium.Le premier chapitre présente différentes architectures d’émetteurs et des techniques de linéarisation avec leurs avantages et inconvénients. Il est également présenté des moyens d’évaluer l’efficacité d’un émetteur par des simulations ou des mesures. L’objectif de cette partie est de choisir une technique de linéarisation à laquelle nous associerons une architecture d’émetteur afin de répondre le plus rigoureusement à notre application et ces contraintes émanant.Le second chapitre détaille le fonctionnement du système complet, la partie numérique et la partie analogique, s’appuyant sur des études théoriques. Nous commencerons en détaillant les contraintes et les précautions qui doivent être prises en compte par le concepteur afin d’étudier l’instabilité et le bruit produit par l’émetteur. Nous décrierons alors deux algorithmes numériques permettant de réaliser la correction des signaux. Des simulations au niveau système de la boucle Cartésienne seront également présenté utilisant, dans un premier temps un amplificateur de puissance idéal, pour ensuite utilisé un amplificateur de puissance réalisé en technologie BiCMOS, et finalement un amplificateur de puissance conçu en technologie CMOS, qui est celle choisie pour notre étude.Le troisième chapitre présente la synthèse de la partie numérique en technologie CMOS des deux algorithmes précédemment cités, elle prend en compte toutes les étapes ; du code VHDL jusqu’au layout, permettant de réaliser un circuit numérique. Ensuite, il est décrit chaque composant de la boucle cartésienne, avec leurs propres simulations ou mesures. De plus, il est important de garder à l’esprit que l’objectif de cette thèse repose sur l’intégration du système complet (partie analogique et numérique) en technologie CMOS 65nm de STMicroelectronics, démontrant ainsi la faisabilité de la solution.Dans un premier temps, nous décrirons la partie numérique permettant de réaliser les étapes de correction de phase et de soustraction des signaux en technologie ASIC. L’algorithme de CORDIC a pour avantage de minimiser la consommation et l’occupation en Silicium de la partie analogique. Par la suite, l’architecture et les spécifications de chaque brique de base constituant la partie analogique seront présentées. Dans notre cas, la chaîne directe est composée de filtres, de mélangeurs, et d'un amplificateur de puissance. Notre objectif est de réaliser ces trois fonctions avec le minium de consommation et une surface du circuit la plus faible possible, ceci permettant une intégration plus aisée.Finalement, les simulations système seront présentées utilisant le logiciel de simulation ADC (Advanced Design Software) d’Agilent pour la partie analogique. Des co-simulations ont été réalisées sur le système complet, utilisant SystemVue pour la partie numérique. Les simulations réalisant ADS nous ont fourni les performances de chaque brique de base s’appuyant sur les caractéristiques des transistors. / Since the first generation of mobile phones, a lot of functions, standards and tools have been integrated on handsets. Twenty years ago, consumers could use their mobile phones only to call and to send messages. Nowadays, internet access, radio, cameras, games and music are included and available as options for every mobile phone.All of these new services make the cost of production for a cellular phone more expensive. Despite that, industry has to find a solution to maintain their products the most attractive as possible including the large range of integrated functions.In the context of interaction with other standards, the aim of this thesis is to design and implement a chipset able to improve the linearity of a transmitter for third generation mobile phones, using both digital and analog technologies. For this purpose, the study will focus on the improvement of the linearity, keeping the consumption and the die area of the circuit as small as possible. We will prove that linearization on an integrated circuit is possible with almost the same consumption and die area occupation compared to a classic transmitter.The first chapter presents the different architectures used for a transmitter and various linearization techniques with their advantages and drawbacks. Some metrics are also presented in order to evaluate these architectures. The goal of this part is to choose a linearization technique associated to a transmitter in order to fit with our application and constraints.The second chapter explains the complete system, digital and analog parts, with theoretical studies. We will start by detailing the constraints and precautions that must be taken into account by the designer to study the instability and the noise generated by the transmitter. We will describe how two algorithms make signal corrections. In the last part we will show system level simulations of the Cartesian Feedback using, first, an ideal power amplifier (PA), then, a PA in a BiCMOS technology, and finally, a PA in a CMOS technology that will be used for the final integrated circuit.The third and last chapter shows the digital synthesis in a CMOS technology of the two algorithms previously mentioned, considering all steps, from the VHDL code until the layout of the digital part. We will describe and simulate each analog building block of the Cartesian Feedback, with the measurement results for some of them. Each chapter will be working towards the goal of this study, demonstrated in this part: to make an integrated system, with its complete solution and simulations.This chapter presents the integration of the analog and digital Cartesian Feedback described previously in 65nm CMOS technology from STMicroelectronics. First, the digital part generating the phase correction and subtraction will be shown in ASIC technology, with a CORDIC algorithm to reduce its consumption and size. Secondly, the architecture and specification of building blocks will be shown. In our case, the direct path is composed of filters, RF modulator and a Power Amplifier. Our objective is to design these three functions to minimize the consumption and the silicon area of the integrated architecture. Finally, system level simulations will be presented using the ADS (Advanced Design Software) from Agilent for the analog part. Co-simulations have been done to analyze the whole system, with SystemVue for the digital part. The simulations using ADS will provide the performance of each building block on the transistors level.

Afin de répondre à la demande croissante du nombre d'objets connectés et de débits de données plus élevés, la cinquième génération de réseau mobile (5G) va être déployée.Pour répondre à ces défis, la 5G utilisera le beamforming pour améliorer la qualité de transmission et étendre la couverture du réseau. En raison du manque de spectre RF disponible en dessous de 6 GHz, l'industrie de la téléphonie mobile étudie actuellement les bandes de fréquences millimétriques en particulier autour de 28 GHz. L'utilisation de la technologie CMOS pour les applications 5G apparait prometteuse pour le marché de masse que vise la 5G, d'autant qu'aujourd'hui la miniaturisation des transistors CMOS permet un fonctionnement compétitif aux fréquences millimétriques. Pour répondre à toutes les attentes de la 5G notamment en termes de fiabilité, de nouvelles idées en rupture, avec le self-healing et le self-contained, permettent d’utiliser au maximum les avantages de la technologie CMOS tout en proposant un fonctionnement fiable pou rl’amplificateur. Dans le cadre du self-healing et du self-contained, plusieurs circuits son tintégrés sur silicium tel qu'un amplificateur intégrant un détecteur de puissance totalement non invasif pour le self-healing et un amplificateur équilibré pour le selfcontained. / In order to meet the growing demand for more connected objects and higher data rates,the fifth generation of mobile network (5G) will be deployed. To address thesechallenges, the 5G will use beamforming to improve the transmission quality and extendthe network coverage. Due to the lack of available RF spectrum below 6 GHz, the mobileindustry is studying millimeter wave frequency bands in particular around 28 GHz. Theuse of CMOS technology for 5G applications is promising for the 5G mass market,especially nowadays the miniaturization of CMOS transistors allows competitiveoperation at millimeter frequencies. To meet all the expectations of the 5G especially interms of reliability, new breakthrough ideas, with the self-healing and the selfcontained,allow to use all the benefits of CMOS technology to the maximum whileoffering reliable operation for the amplifier. Within the framework of self-healing andself-contained, several circuits are integrated on silicon such as an amplifier integratedwith a totally non-invasive power detector for self-healing and a balanced self-containedamplifier.

La hadronthérapie est une méthode de radiothérapie utilisant des ions (ici le carbone) comme faisceau plutôt que des rayons X plus conventionnels pour le traitement des cancers. Étant donné le parcours spécifique des ions dans la matière, ils permettent de traiter des tumeurs profondes dans des zones délicates telles que le cerveau par exemple. Ceci est complémentaire à tout ce qui existe depuis des dizaines d’années (intervention chirurgicale, rayons X, chimiothérapie). Deux futurs centres de traitement et de recherche (ARCHADE à Caen et ETOILE à Lyon) seront opérationnels en France à partir de 2018 en ce qui concerne ARCHADE afin de profiter des avancées récentes et de poursuivre les recherches sur cette méthode. La perte d’énergie des ions carbone dans la matière suit la loi de Bethe-Bloch, le maximum de dépôt d’énergie se situant dans une zone restreinte appelée « pic de Bragg ». En modulant la position et l’énergie du faisceau, il est possible d’irradier l’ensemble du volume de la tumeur. Cependant, les réactions nucléaires de l’ion carbone dans les tissus entrainent la production de fragments plus légers (H, He, Li etc.) qui déposent leur énergie au-delà du pic de Bragg. Les modèles implémentés dans les codes de simulation couramment utilisés en hadronthérapie (FLUKA, GEANT4 etc.) sont incapables de reproduire en même temps les distributions angulaires des fragments générés ainsi que les distributions en énergie. Le fait de ne pas reproduire fidèlement ce phénomène de fragmentation nuit à la précision des systèmes de planification de traitement utilisés cliniquement. En effet, une mauvaise estimation du processus de fragmentation entraine un biais dans le calcul de la dose déposée dans les cellules saines en arrière du pic de Bragg. Ainsi, afin de mieux contraindre les modèles, deux expériences de mesure de sections efficaces de fragmentation du carbone ont été menées. La première en mai 2011 avec un faisceau à 95MeV/n au GANIL à CAEN avec les collaborateurs du LPC Caen et la seconde en août 2011 avec un faisceau à 400 MeV/n au GSI à Darmstadt, avec la collaboration FIRST. L’expérience E600 étudie la fragmentation des ions du faisceau de carbone à 95 MeV/n dans différentes cibles minces (Au, C, , Ti etc.) correspondant aux différents constituants élémentaires du corps humain. Les différents fragments sont détectés à l’aide de cinq télescopes. Chacun d’eux est constitué de 3 étages (2 détecteurs silicium et un scintillateur CsI) afin de faire des mesures de perte d’énergie et d’énergie totale permettant une identification par la méthode du ΔE-E. Ces télescopes étaient disposés sur des raquettes pilotées à distance afin de pouvoir modifier leur position angulaire par rapport à la position de la cible. Ainsi, les taux de production des différents fragments permettent de remonter aux sections efficaces de fragmentation doublement différentielles (en énergie et en angle). [...] / The hadrontherapy is a radiotherapy method using ions (carbon ions here) instead of the more conventional X-rays for cancer treatment. Deep radioresistant tumour areas, as brain carcinoma for example, can be treated thanks to the specific dosedeposition at the end of the ion path. This is an additional method to older classic ones (surgery, X-rays, chemotherapy). Two hadrontherapy centres for treatment and research are planned in France from 2018 (ARCHADE) in order to benefit from the newest progress and to keep improving this method. Carbon ions energy loss in the matter follows the Bethe-Bloch law. The maximum of energy depth is located in a limited area called “Bragg peak”. By adjusting the beam position and energy, the whole volume of the tumor can be irradiated. Nevertheless, nuclear reactions of carbon ion in tissues generate the production of lighter fragments (H, He, Li etc.) that deposit their energy beyond the Bragg peak. Models implemented in hadrontherapy simulation codes (FLUKA, GEANT4 etc.) cannot reproduce angular distributions of the lighter fragments and energy distributions at the same time. These poor estimations affect the treatment planning systems accuracy that are clinically used.Indeed, a bad estimation of fragmentation process induces a bias in the dose calculation concerning healthy cells beyond the Bragg peak. In order to better constraint models, two experiments based on fragmentation cross-sections measurements have been performed. The first one in may 2011 with a beam at 95 MeV/u (GANIL) in collaboration with the LPC Caen and the second one in august 2011 with a beam at 400 MeV/u (GSI) with the FIRST collaboration. E600 experiment is devoted to the study of carbon ions fragmentation at 95 MeV/u in several thin targets (Au, C, , Ti etc.) corresponding to the basic building blocks of human body. Five telescopes are designed for the fragments detection. Each one is a three-stage detector (2 silicon detectors and one CsI scintillator) that allows energy loss and total energy measurements for the ΔE-E identification method.Telescopes were disposed two by two in the reaction chamber with a remote control of the angular position. From the production rate measurements, the double differential fragmentation cross-sections (energy and angle) can be computed.From the experimental data for + reaction at 95 MeV/u on a 250 μm thick carbon target, all cross-sections were deduced.FIRST experiment uses a very different set-up. It is composed of: a beam monitoring, a vertex detector (CMOS), a calorimeter(KENTROS), a magnet (ALADIN), MUSIC (3 ionization chambers and 4 proportional counters) and a TOF-wall. Generated particles trajectory is reconstructed thanks to the vertex detector + TOF-wall for all fragments emitted with an angle lower than 5° and thanks to the vertex detector + KENTROS for higher angles. In the first case, the ALADIN magnet deflects the trajectory of the particles (MUSIC detector ran out). One 8 mm thick target has been used here. Preliminary results concerning production rates of the different charges, angular distributions and reconstruction efficiencies have been obtained. Heavier fragments mass identification is quite difficult because of the non-working MUSIC detector; it degrades the fragments momentumaccuracy.[...]

La mesure de courant dans un environnement industriel est une étape indispensable pour garantir la pérennité d'un réseau de distribution électrique. En général, chaque domaine d'applications (mesure, protection, etc...) nécessitent l'utilisation d'un capteur adapté. Ces travaux de thèse proposent d'utiliser un capteur bas coût principalement dédié à la protection, le tore de Rogowski, aussi comme élément de mesure. Afin d'améliorer sa précision intrinsèque souvent insuffisante, nous avons développé une boucle de correction et une électronique de calibrage intégrée (CMOS 0,35µm) permettant d'adapter ce capteur aux standards métrologiques. Nous détaillons dans ce manuscrit les étapes de l'élaboration de cette boucle de correction ainsi que les résultats obtenus à l'aide des différents prototypes. Nous terminons par la présentation du premier démonstrateur technologique, premier pas vers un système de mesure de courant sans contact de classe 0.1, auto-calibré, autonome et bas coût. / The measurement of the current in an industrial environment is a necessary step to ensure the sustainability of an electrical distribution network. Typically, each application domain (measurement, protection, etc ...) requires the use of a suitable sensor. This thesis work proposes the use of the Rogowski coil current transducer, a low cost sensor usually used for protection, as measuring element. In order to improve its often insufficient intrinsic accuracy, we have developed a correction loop as well as an integrated electronics for calibration (CMOS 0,35μm) to adapt the sensor to metrological standards. In this manuscript, we detail the development stages of this correction loop and the results obtained with different prototypes. We conclude with the presentation of the first technology demonstrator, a very first step towards a current measurement system that would be contactless, 0.1 accuracy class, auto-calibrated, autonomous and low cost.