Academic Clustering and Placement Tools for Modern Field-Programmable Gate Array Architectures Daniele Giuseppe Paladino Masters of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2008 Abstract Academic tools have been used in many research studies to investigate Field-Programmable Gate Array (FPGA) architecture, but these tools are not sufficiently flexible to represent modern commercial devices. This thesis describes two new tools, the Dynamic Clusterer (DC) and the Dynamic Placer (DP) that perform the clustering and placement steps in the FPGA CAD flow. These tools are developed in direct extension of the popular Versatile Place and Route (VPR) academic tools. We describe the changes that are necessary to the traditional tools in order to model modern devices, and provide experimental results that show the quality of the algorithms achieved is similar to a commercial CAD tool, Quartus II. Finally, a small number of research experiments were investigated using the clustering and placement tools created to demonstrate the practical use of these tools for academic research studies of FPGA CAD tools.

The principle of universal shipborne automatic identification system (AIS) is to allow automatic exchange of shipboard information between one vessel and another. Saab TransponderTech AB has an operating AIS transponder on the market and the purpose of this report is to investigate alternative technologies that could result in a highly integrated replacement for the existing hardware. Design aspects of a system-on-chip are discussed, such as: available system-on- chip technologies, intellectual property, on-chip bus structures and development tools. This information is applied to the existing hardware and the integration possibilities of the various parts of the AIS transponder is investigated. The focus will be on two main transponder parts that are possible to replace with highly integrated circuits. The first of these parts is the so-called digital part where system-on-chip platforms for different technologies have been investigated with a special interest in a highly integrated FPGA implementation. The second part is the radio frequency receivers where alternatives to the existing superheterodyne receiver are discussed. The conclusion drawn is that there exist technologies for developing a highly integrated AIS transponder. An attractive highly integrated transponder could consist of a FPGA system-on-chip platform with subsampling digital receivers and additional components that are unsuitable for integration.

This paper describes an FPGA implementation of a solution-counting solver for the N-Queens Puzzle. The proposed algorithmic mapping utilizes the fast carrychain logic found on modern FPGA architectures in order to achieve a regular and efficient design. From an initial full chessboard mapping, several optimization strategies are explored. Also, the infrastructure is described, which we have constructed for the computation of the currently unknown solution count of the 26- Queens Puzzle. Finally, we compare the performance of our used concrete FPGA device mappings also in contrast to general-purpose CPUs.

Η παρούσα ειδική ερευνητική εργασία υλοποιήθηκε στα πλαίσια του Μεταπτυχιακού Προγράμματος “Ηλεκτρονική και Η/Υ” του τμήματος Φυσικής του Πανεπιστημίου Πατρών. Σκοπός της εργασίας αυτής είναι η ανάπτυξη ενός συστήματος βασισμένου σε τεχνολογία FPGA [1-2]. Το σύστημα αυτό έχει τη δυνατότητα να λαμβάνει εικόνες, και αφού τις επεξεργαστεί κατάλληλα, τις αποθηκεύει στη μνήμη του και στη συνέχεια τις απεικονίζει σε μία LCD οθόνη αφής [3-4,8]. Τέλος, η διαχείριση των λειτουργιών που ενσωματώνει το σύστημα γίνεται μέσω της οθόνης αυτής [5]. Στο πρώτο κεφάλαιο πραγματοποιείται σύντομη περιγραφή του συστήματος, της βασικής αναπτυξιακής πλατφόρμας, DE2 της Altera [6], καθώς και του περιβάλλοντος ανάπτυξης Quartus II [12]. Tο δεύτερο κεφάλαιο χωρίζεται σε δύο μέρη. Στο πρώτο μέρος γίνεται παρουσίαση της TRDB-D5M CMOS Camera της Altera [9], των γενικών χαρακτηριστικών της και των απαραίτητων καταχωρητών για τη σωστή ρύθμισή της. Στο δεύτερο μέρος παρουσιάζεται η οθόνη TRDB_LTM LCD Touch Panel της Altera [7], η οποία επιλέχθηκε τόσο για την απεικόνιση των εικόνων όσο και για τον έλεγχο του συστήματος μέσω αυτής. Στο τρίτο κεφάλαιο πραγματοποιείται η πλήρης περιγραφή του συστήματος, που υλοποιήθηκε μέσω της γλώσσας ανάπτυξης υλικού Verilog HDL και ενσωματώθηκε στο FPGA [10-11], με σκοπό τη διαχείριση των δεδομένων που λαμβάνονται από την Camera. Στο τέταρτο κεφάλαιο παρουσιάζονται τα αποτελέσματα της εργασίας αυτής, τα συμπεράσματα που προέκυψαν, καθώς επίσης και προτάσεις για μελλοντική ανάπτυξη του συστήματος. Τέλος, στο παράρτημα Α παρουσιάζεται ο συνολικός κώδικας που υλοποιήθηκε και ενσωματώθηκε στο FPGA. / The present inquiring master thesis was realized as part of the postgraduate program “Electronics and Computer Science” of the department of Physics of University of Patras. The aim of this master thesis is the development of an FPGA technology based system [1-2] that has the ability to receive images, save them on its memory after appropriate processing and finally project them on an LCD touch panel [3-4,8]. The management of the system operations is realized through this touch panel [5]. Within the first chapter, we briefly describe the system, the basic development board of Altera [6], used to develop it, and finally the environment Quartus II [12]. We separated the second chapter in two parts. The first part presents the TRDB-D5M CMOS Camera of Altera [9], with its basic characteristics and the necessary registers for its appropriate regulation. The second part presents the TRDB-LTM LCD touch panel of Altera [7], which was chosen to portray images and allow the system control. The third chapter describes the system itself, realized in Verilog HDL, and incorporated in the FPGA [10-11], in order to manage the data received by the camera. The fourth chapter presents the results of this master thesis along with important conclusions and suggestions to further research. Finally, in appendix A we present the total code that was realized and incorporated in the FPGA.

Made available in DSpace on 2016-12-12T20:27:37Z (GMT). No. of bitstreams: 1 Resumo - Emiliano.pdf: 94943 bytes, checksum: 29697d95e7130478be8d1ad382dffdeb (MD5) Previous issue date: 2013-08-02 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Electrical Impedance Spectroscopy (EIS), also called Bioelectrical Impedance Analysis (BIA), is a non-invasive technique used for characterizing the electrical properties of biological materials, but also used for obtaining body composition properties and for analyzing food quality. Most EIS devices contain microcontrollers, digital signal generators and data acquisition boards. Digital Signal Processors (DSP) have also been used to implement EIS systems, but they su_er for multifrequency signal generation. Furthermore, DSPs do not have enough space for data storage. On the other hand, EIS systems based on Field-Programmable Gate Array (FPGA) devices are indicated when signal generation and acquisition demand integration and a very small noise level. In addition, FPGA can be used for getting real time signal processing, as it is a hardware rather than sequential execution of instructions. The bioimpedance measurements consist of injecting a sinewave into the material under study by two electrodes and measuring the resulting voltage by other pair of electrodes, which are placed in an impedance probe. Most EIS systems measure the injecting current by a shunt resistor, and then the real and imaginary part of the impedance of the load under study are calculated for each discrete frequency of the system. In this work, an EIS system is proposed based on FPGA for generating sinusoidal signals in the frequency range 0.1 to 500 kHz. It contains two acquisition channels and an interface for measuring both the modulus and phase of the impedance. A proposed EIS system is fully described. The system performance of the FPGA and the acquisition interface were comprehensively investigated. Experiments using saline solutions were used in order to calibrate the impedance probe used in this work. Measurements in raw bovine milk were made in order to validate the proposed EIS system. The results showed an error of 2% when measuring milk samples in the conductivity range of 1.46 to 2.9 mS/cm. Further measurements were made in order to investigate the e_ects in the impedance spectra due to Somatic Cell Count (SCC) and hydrogen peroxide in the bovine milk. The results showed that the impedance phase spectra are sensitive to SCC at low frequencies. It has also been shown that the impedance phase of the milk adulterated with hydrogen peroxide is almost linear in the frequency range from 1 up to 10 kHz. It was showed that real time measurements and signal processing based on FPGA can be used for developing an EIS system. The proposed system is modular and it can be portable. This might be the case of using this system for measuring and characterizing bovine milk by hand-held or in-milkline instrumentation. / Espectroscopia de Impedância Elétrica (EIE), também conhecida como Análise por Bioimpedância Elétrica, é uma técnica não-invasiva utilizada para determinação das propriedades elétricas de materiais biológicos e também empregada para obtenção da composição corporal e estudo da qualidade de alimentos. Diversos sistemas de EIE são projetados com microcontroladores, sintetizadores de sinais digitais e placas de aquisição. Processadores Digitais de Sinais (DSP) também são utilizados para projetos de sistemas de EIE, porém, eles sofrem falta de recursos para trabalhar com geração e condicionamento de sinais multifrequenciais. Além do mais, não têm espaço de memória su_ciente para o armazenamento de dados. Por outro lado, os sistemas baseados em FPGA são indicados para aplicações que envolvem geração e aquisição de sinais multifrequenciais que exigem forte integração e redução de ruídos na eletrônica. Diferente da execução sequencial de instruções, o FPGA trabalha em tempo real, já que se trata de processamento em hardware. A medição de bioimpedância consiste em injetar uma onda senoidal no material em estudo por meio de dois eletrodos e medir a tensão resultante através de outro par de eletrodos, onde estão fixados em uma sonda de impedância. A maioria dos sistemas de EIE efetuam a medição da corrente usando uma carga de teste e em seguida executam o cálculo da parte real e imaginária da impedância para cada frequência. Neste trabalho, é proposto um sistema de EIE baseado em FPGA para gerar sinais senoidais na faixa de frequência de 0,1 a 500 kHz. É composto de dois canais de aquisição e uma interface para medição de módulo e fase da impedância. Sua arquitetura detalhada está descrita nas seções seguintes, onde o desempenho da geração e aquisição de sinais foram precisamente estudados. Experimentos com soluções salinas foram realizados para calibrar o sistema, e medições com leite bovino foram efetuadas para validação do sistema proposto. Os resultados indicam um erro de 2% na medição de amostras com condutividade entre 1,46 e 2,9 mS/cm. Outras medições foram realizadas para investigar os efeitos no espectro de impedância devido a Contagem de Células Somáticas (CCS) e peróxido de hidrogênio no leite bovino e os estudos mostraram que o espectro de fase é sensível a CCS em baixas freqüências. Também foi possível veri_car que o leite adulterado com peróxido de hidrogênio apresenta fase aproximada a linear na faixa de 1 a 10 kHz. Este trabalho mostrou que a medição em tempo real com arquitetura baseada em FPGA pode ser utilizada para projetar sistemas de EIE. O sistema proposto é modular e pode ser portável, permitindo sua utilização para medição e caracterização do leite bovino inloco manualmente ou por instrumentação usando recipiente com amostra de leite.

Les systèmes RFID sont de plus en plus utilisés dans des applications critiques fonctionnant dans des environnements perturbés (ferroviaire, aéronautique, chaînes de production ou agroalimentaire) ou dans des applications où la sécurité est essentielle (identification, lutte contre la contrefaçon). Pourtant, ces systèmes faibles coûts, initialement conçus pour des applications de masse non critiques, sont peu robustes par nature. Pour les applications critiques, les défaillances des puces RFID peuvent avoir des conséquences catastrophiques ou créer des failles de sécurité importantes. Ces défaillances peuvent avoir des origines nombreuses : par exemple, des origines matérielles dues au vieillissement naturel des circuits intégrés ou à des attaques (optiques, électromagnétiques, en tension). Il est donc d'usage dans les applications critiques d'accroître la robustesse des systèmes RFID par la mise en œuvre de redondance matérielle. Cependant cette redondance accroît le coût du déploiement des systèmes RFID ainsi que la complexité des protocoles et middleware associés. L'amélioration de la robustesse des tags permet de grandement limiter cette redondance. L'objectif de la thèse est d'accroitre la robustesse des tags UHF passifs en proposant et validant de nouvelles architectures numériques de puces RFID robustes à la fois aux défaillances et aux attaques matérielles. Les approches de durcissement des circuits intégrés étudient généralement leur robustesse par simulation et ce de manière indépendante à la validation de leur conception. La méthode la plus courante afin de valider la robustesse d'un circuit repose sur l'injection de fautes par simulation. Pour les puces RFID, ce type d'approche par simulation est problématique car les performances des puces dépendent de nombreux paramètres difficilement modélisables globalement. En effet, le fonctionnement d'un tag dépend de son environnement électromagnétique, du nombre de tags présents dans le système, des protocoles mis en œuvre. Aussi, nous avons développé une méthodologie basée sur le prototypage permettant d'éviter des simulations complexes et chronophages. La puce RFID prototype est alors implantée dans un FPGA. Ainsi, dès la phase de conception, cette puce peut être validée fonctionnellement dans un environnement réel. De plus, en utilisant différentes techniques d'instrumentation permettant l'injection de fautes dans les circuits numériques sur FPGA, il est alors possible d'analyser l'effet sur l'ensemble du système des fautes injectées dans le tag. Dans cette thèse, dans un premier temps, le prototype fonctionnel d'un tag RFID a été développé. Dans un second temps, ce prototype a été instrumenté pour pouvoir réaliser des injections de fautes en ligne ou hors ligne. Ensuite, le comportement du système RFID en présence de fautes dans ce tag RFID a été évalué. L'analyse des effets de ces fautes sur le système a permis de proposer, de mettre en œuvre et de valider de nouvelles architectures numériques de tags RFID robustes. Ce nouvel environnement de prototypage et d'injection de fautes a également permis de démontrer les effets de nouvelles attaques contre les systèmes RFID reposant sur l'insertion de tags fautifs ou malveillants dans les systèmes. Enfin, cette approche a permis d'évaluer les méthodes de détection des tags fautifs. / RFID tags are more and more used for critical applications within harsh environments (aeronautics, railways) or for secure applications such as identification, countermeasure against counterfeiting. However, such low cost systems, initially designed for non-critical applications with a high volume, are not robust by themselves. For critical applications, a malfunction of RFID chip may have serious consequences or induce a severe security breach for hackers. Dysfunctions can have many origins: for instance, hardware issues can be due to aging effects or can also be due to hackers attack such as optical or electromagnetic fault injection. It is thus a common practice for critical applications to increase the robustness of RFID system. The main purpose of this PhD Thesis is to increase UHF tags robustness by proposing new digital architectures of RFID chips which would be resilient against both hardware attacks and natural defects.Usual design techniques for robustness IC improvement consist in evaluating the design robustness by simulation and to do this independently of the design validation. The main technique for robustness evaluation is the simulation based faults injection. Within the RFID context such an approach only based on simulation has several drawbacks. In fact, simulations often are inaccurate because the system behavior relies on several parameters such as the global electromagnetic environment, the number of tags present in the reader field, the RFID protocol parameters.The purposes of this PhD are to develop a design method dedicated to RFID system based on hardware prototyping in order to avoid time consuming simulations and then to evaluate the design within a real environment.The hardware prototyping based on FPGA allows the design to be validated in a real environment. Moreover, using instrumentation techniques for fault injection within FPGA , it will be then possible to analyze the effects of faulty tags on the global system in terms of safety and security and then to propose countermeasures.In this thesis an FPGA based emulation platform called RFIM has been developed. This platform is compliant to EPC C1 Gen2 RFID standard. The RFID tag emulator has been validated functionally in a real environment. The RFIM platform uses the instrumentation technique for injecting faults in the digital tag circuit. Through fault injection campaigns RFIM platform can analyze the effect on the entire system of the faults injected into the tag, and ten validate new robust digital architectures.The RFIM platform has been used to demonstrate the effects of further attacks against RFID systems based on the insertion of faulty or malicious tag that contains a hardware Trojan. Finally, RFIM platform helps to develop countermeasures against the fault effects. These countermeasures have been implemented and tested in a real RFID environment with several tags and reader.

Simuladores quânticos têm tido um importante papel no estudo e desenvolvimento da computação quântica ao longo dos anos. A simulação de algoritmos quânticos em computadores clássicos é computacionalmente difícil, principalmente devido à natureza paralela dos sistemas quânticos. Para acelerar essas simulações, alguns trabalhos propõem usar hardware paralelo programável como FPGAs, o que diminui consideravelmente o tempo de execução. Contudo, essa abordagem tem três problemas principais: pouca escalabilidade, já que apenas transfere a complexidade do domínio do tempo para o domínio do espaço; a necessidade de re-síntese a cada mudança no algoritmo; e o esforço extra ao projetar o código RTL para simulação. Para lidar com esses problemas, uma arquitetura de um co-processador SIMD é proposta, cujas operações das portas quânticas está baseada no modelo Network of Butterflies. Com isso, eliminamos a necessidade de re-síntese com mudanças pequenas no algoritmo quântico simulado, e eliminamos a influência de um dos fatores que levam ao crescimento exponencial do uso de recursos da FPGA. Adicionamente, desenvolvemos uma ferramenta para geração automática do código RTL sintetizável do co-processador, reduzindo assim o esforço extra de projeto. / Quantum simulators have had a important role on the studying and development of quantum computing throughout the years. The simulation of quantum algorithms on classical computers is computationally hard, mainly due to the parallel nature of quantum systems. To speed up these simulations, some works have proposed to use programmable parallel hardware such as FPGAs, which considerably shorten the execution time. However this approach has three main problems: low scalability, since it only transfers the complexity from time domain to space domain; the need of re-synthesis on every change on the algorithm; and the extra effort on designing the RTL code for simulation. To handle these problems, an architecture of a SIMD co-processor is proposed, whose operations of quantum gates are based on Network of Butterflies model. Thus, we eliminate the need of re-synthesis on small changes on the simulated quantum algorithm, and we eliminated the influence of one of the factors that lead to the exponential growth on the consumption of FPGA resources. Aditionally, we developed a tool to automatically generate the synthesizable RTL code of the co-processor, thus reducing the extra design effort.

Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de vídeo, por exemplo, memórias de grande capacidade são necessárias para armazenar vários quadros de imagem enquanto que os algoritmos de compressão fazem a busca por redundâncias. No caso de sistemas implementados em tecnologia FPGA é possível utilizar os blocos de memória disponíveis internamente ao FPGA, os quais são limitados a poucos mega-bytes de dados. Para aumentar a capacidade de armazenamento de dados é necessário usar elementos de memória externa e um núcleo de propriedade intelectual (IP) de controlador de memória é necessário. Contudo, seu desenvolvimento é uma tarefa muito complexa e nem sempre é possível utilizar uma solução "sob demanda". O uso de FPGAs para prototipar sistemas permite ao desenvolvedor integrar módulos rapidamente. Nesse caso, a verificação do projeto é uma questão importante a ser considerada no desenvolvimento de um sistema complexo. Controladores de memória de alta velocidade são extremamente sensíveis aos atrasos de propagação da lógica e do roteamento. A síntese a partir de uma descrição em linguagem de hardware (HDL) necessita da verificação de sua compatibilidade com as especificações de temporização pré-determinadas. Como solução para esse problema, é apresentado nesse trabalho um IP do controlador de memória DDR SDRAM com função de BIST (Built-In Self-Test) integrada, onde o teste de memória é utilizado para verificar o funcionamento correto do controlador. / Many integrated Systems-on-Chip (SoC) devices, specially those dedicated to multimedia applications, process large amounts of data stored on memories. The performance of the memories ports directly affects the performance of the system. Optimization of the usage of data storage and reduction of cost and power consumption of the electronic systems encourage the development of efficient architectures for memory controllers. This improvement must be reached either for embedded or external memories. In systems for video processing, for example, large memory arrays are needed to store several video frames while compression algorithms search for redundancies. In the case of FPGA system implementation, it is possible to use memory blocks available inside FPGA, but for only a few megabytes of data. To increase data storage capacity it is necessary to use external memory devices and a memory controller intellectual property (IP) core is required. Nevertheless, its development is a very complex task and it is not always possible to have a custom solution. Using FPGA for system prototyping allows the developer to perform rapid integration of modules to exercise a hardware version. In this case, test is an important issue to be considered in a complex system design. High speed memory controllers are very sensitive to gate and routing delays and the synthesis from a hardware description language (HDL) needs to be verified to comply with predefined timing specifications. To overcome these problems, a DDR SDRAM controller IP was developed which integrate the BIST (Built-In Self-Test) function, where the memory test is used to check the correct functioning of the DDR controller.

La 5ème génération de réseaux mobiles (5G), actuellement en cours de standardisation, prévoit de nouveaux scénarios de communication dans l’évolution vers un monde entièrement connecté et communicant. Dans ce contexte, un nombre très important de techniques avancées sont en cours d’exploration pour répondre aux nombreux défis imposés en termes de débit, de latence, de consommation énergétique, et de capacité à faire communiquer entre eux, efficacement, des milliards d'objets très différents. Parmi les techniques les plus prometteuses de la couche physique, de nouvelles formes d'ondes multiporteuses filtrées sont proposées. Bien qu’elles offrent un meilleur confinement spectral et une meilleure localisation en temps et en fréquence par rapport à l’OFDM de la 4G, elles présentent des limitations soit en termes de complexité soit en termes de performance et d’intégration. De plus, ces formes d’ondes sont évaluées d’un point de vue théorique et les résultats ne sont pas toujours validés sur des plateformes matérielles de preuve de concept reproduisant les conditions réelles des scénarios de la 5G.Dans ce contexte, les travaux de cette thèse proposent plusieurs contributions originales aussi bien au niveau algorithmes de traitement qu’au niveau architectures matérielles. Dans le domaine algorithmique,les travaux réalisés ont mené aux contributions suivantes : (1) Un nouveau filtre prototype court est proposé pour la forme d’onde FBMC/OQAM. Des analyses analytiques, complétées par simulation,montrent que le filtre proposé permet d’améliorer la résistance aux erreurs de synchronisation temporel et de réduire la complexité du récepteur FBMC de type « frequency-spread » comparé aux autres filtres de la littérature, (2) Un nouveau type de récepteur FBMC adapté pour les filtres courts est proposé. Ce récepteur a la particularité d’améliorer sensiblement la résistance aux canaux doublement dispersifs pour des filtres courts, et de supporter les communications asynchrones, (3) Un émetteur UF-OFDM original de complexité significativement réduite par rapport à la littérature est proposé. Contrairement aux techniques existantes, l’émetteur proposé n’introduit aucune approximation dans le signal généré, et préserve ainsi le confinement spectral de la forme d’onde. Dans le domaine de la conception matérielle, les travaux réalisés durant cette thèse ont mené aux contributions suivantes : (4) Une architecture matérielle optimisée des émetteurs FBMC et UF-OFDM de complexité comparable à OFDM, (5) Une architecture matérielle optimisée de l’étage de filtrage du récepteur FBMC « frequency-spread », avec une complexité comparable à celle d’un récepteur « polyphase-network », et (6) Une des premières plateformes matérielles de preuve de concept de la 5G, pouvant évaluer les performances des formes d’ondes pour les différents services de la 5G. / The 5th generation of mobile communications is fore seen to cope with a high degree of heterogeneity in terms of services: enhanced mobile broadband, massive machine, vehicular and mission critical communications, broadcast services. Consequently, diverse and often contradicting key performance indicators need to be supported, such as high capacity/user-rates, low latency, high mobility, massive number of devices, low cost and low power consumption. 4G is not designed to efficiently meet such a high degree of heterogeneity: the OFDM waveform exhibits several limitations in terms of spectrum usage and robustness to frequency and timing synchronization errors. In order to overcome these limitations and to cope with the new 5G requirements,several research initiatives have been conducted to design new waveforms. Proposed candidates, such as FBMC/OQAM or UF-OFDM,are mainly based on multicarrier modulation with specific filtering scheme used on the top of the OFDM basis. However, most of the proposed new waveforms are often studied and analyzed at the algorithmic level considering mainly the quality of the communication link. Therefore, the investigation of low-complexity implementations and the availability of real hardware prototypes are of high interest for performance validation and proof-of-concept of the diverse proposed communication techniques. In the above context, this thesis work proposes several original contributions in the algorithm and the hardware design domains. In the algorithm domain, this work leads to the following contributions: (1) Anovel short prototype filter for FBMC allowing for near perfectreconstruction and having the same size as one OFDM symbol is proposed. Using the Frequency Spread implementation for the FBMC receiver, analytical studies and simulation results show that the proposed filter exhibits better robustness to several types of channel impairments when compared to state-of-the-art short prototype filters and OFDM modulation. (2) A novel FBMC receiver technique suitable for short filters is proposed. This receiver enables to greatly improve the robustness against double dispersive channels for short filters, and enables the support of asynchronous communications, (3) A novel low complexityUF-OFDM transmitter without any signal quality loss isproposed. For small subband sizes, the complexity becomescomparable to OFDM regardless of the number of allocated subbands.In the hardware design domain, this thesis work leads to the following contributions: (4) An efficient pipelined hardware architecture of the FBMC/OQAM transmitter capable of supporting several filter lengths and targeting low complexity is proposed and compared to typical FBMC/OQAM and OFDM implementations, (5) An optimized frequency spread based hardware architecture of the filtering stage is proposed for the designed short prototype filter, showing lower complexity than the classical Poly Phase-Network-based implementation, (6) One of the first flexible and efficient hardware platforms for 5G waveform design, allowing the support of several communication scenarios as foreseen in 5G.

Confiabilidade é um parâmetro de projeto importante para aplicações criticas tanto na Terra como também no espaço. Os FPGAs baseados em memoria SRAM são atrativos para implementar aplicações criticas devido a seu alto desempenho e flexibilidade. No entanto, estes FPGAs são susceptíveis aos efeitos da radiação tais como os erros transientes na memoria de configuração. Além disso, outros efeitos como o envelhecimento (aging) ou escalonamento da tensão de alimentação (voltage scaling) incrementam a sensibilidade à radiação dos FPGAs. Nossos resultados experimentais mostram que o envelhecimento e o escalonamento da tensão de alimentação podem aumentar ao menos duas vezes a susceptibilidade de FPGAs baseados em SRAM a erros transientes. Estes resultados são inovadores porque estes combinam três efeitos reais que acontecem em FPGAs baseados em SRAM. Os resultados podem guiar aos projetistas a prever os efeitos dos erros transientes durante o tempo de operação do dispositivo em diferentes níveis de tensão. A correção da memoria usando a técnica de scrubbing é um método efetivo para corrigir erros transientes em memorias SRAM, mas este método impõe custos adicionais em termos de área e consumo de energia. Neste trabalho, nos propomos uma nova técnica de scrubbing usando a redundância interna a nível de quadros chamada FLR- scrubbing. Esta técnica possui mínimo consumo de energia sem comprometer a capacidade de correção. Como estudo de caso, a técnica foi implementada em um FPGA de tamanho médio Xilinx Virtex-5, ocupando 8% dos recursos disponíveis e consumindo seis vezes menos energia que um circuito corretor tradicional chamado blind scrubber. Além, a técnica proposta reduz o tempo de reparação porque evita o uso de uma memoria externa como referencia. E como outra contribuição deste trabalho, nos apresentamos os detalhes de uma plataforma de injeção de falhas múltiplas que permite emular os erros transientes na memoria de configuração do FPGA usando reconfiguração parcial dinâmica. Resultados de campanhas de injeção são apresentados e comparados com experimentos de radiação acelerada. Finalmente, usando a plataforma de injeção de falhas proposta, nos conseguimos analisar a efetividade da técnica FLR-scrubbing. Nos também confirmamos estes resultados com experimentos de radiação acelerada. / Reliability is an important design constraint for critical applications at ground-level and aerospace. SRAM-based FPGAs are attractive for critical applications due to their high performance and flexibility. However, they are susceptible to radiation effects such as soft errors in the configuration memory. Furthermore, the effects of aging and voltage scaling increment the sensitivity of SRAM-based FPGAs to soft errors. Experimental results show that aging and voltage scaling can increase at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These findings are innovative because they combine three real effects that occur in SRAM-based FPGAs. Results can guide designers to predict soft error effects during the lifetime of devices operating at different power supply voltages. Memory scrubbing is an effective method to correct soft errors in SRAM memories, but it imposes an overhead in terms of silicon area and energy consumption. In this work, it is proposed a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLRscrubbing) with minimum energy consumption overhead without compromising the correction capabilities. As a case study, the FLR-scrubbing controller was implemented on a mid-size Xilinx Virtex-5 FPGA device, occupying 8% of available slices and consumes six times less energy per scrubbed frame than a classic blind scrubber. Also, the technique reduces the repair time by avoiding the use of an external golden memory for reference. As another contribution, this work presents the details of a Multiple Fault Injection Platform that emulates the configuration memory upsets of an FPGA using dynamic partial reconfiguration. Results of fault injection campaigns are presented and compared with accelerated ground-level radiation experiments. Finally, using our proposed fault injection platform it was possible to analyze the effectiveness of the FLR-scrubbing technique. Accelerated radiation tests confirmed these results.