A extrêmement hautes fréquences, les applications électroniques vont être confrontées à des challenges liés à la réduction des dimensions et la compacité des systèmes. Les limites physiques des matériaux conventionnels étant atteintes, de nouvelles alternatives sont nécessaires dans le domaine du nano-packaging. De nouveaux matériaux ont été étudiés pour remplacer les matériaux conventionnels. Parmi eux, le nanotube de carbone démontre une excellente conductivité électrique et thermique ainsi qu’une résistance physique extraordinaire. Il est donc un candidat de choix pour des applications comme les interconnexions, l’évacuation de chaleur, le blindage électromagnétique ou encore le renforcement structurel. Autant de points capitaux pour le nano-packaging moderne. Dans ce manuscrit, les nanotubes de carbone vont être étudiés en profondeur pour réaffirmer leurs propriétés électroniques et thermiques hors du commun. Nous nous concentrerons ensuite sur l’étude de deux types d’interconnexions à base de nanotubes de carbone : des interconnexions à base de plot en nanotubes de carbone utilisant la technologie Flip-Chip et des interconnexions sans-fil à base de monopole composé de nanotubes de carbone. Enfin, nous étudierons la possibilité de créer des composants passifs Radio-Fréquence à l’aide de structures en nanotubes de carbone. De nouvelles méthodes de fabrication des structures en CNT ont été utilisées au cours de ces travaux de thèse afin d’obtenir une compatibilité avec les technologies CMOS. / At extremely high frequency, electronic applications will have to challenge problems born from the size reduction and compactification of the systems. Physical limits of conventional materials will be reached and so new alternatives are necessary in the nano-packaging field. New materials have been studied to replace conventional materials. Among them, carbon nanotubes have shown extremely high electrical and thermal conductivity as well as extraordinary physical resistance. And so carbon nanotubes are a good candidate for applications such as interconnects, thermal management, electromagnetic shielding or structural reinforcement. All of those applications are capital for modern nano-packaging. In this manuscript, carbon nanotubes will be studied in depths to demonstrate again their incredible electronic and thermal properties. We will then focus on the study of two types of carbon nanotubes based interconnects: carbon nanotubes bumps based interconnects for Flip-Chip applications and wireless interconnects based on carbon nanotubes monopole antenna. Finally, we will study the possibility of creating passive RF components using carbon nanotubes structures. New ways of fabricating the carbon nanotubes structure were used in order to get a fabrication process of the prototype completely compatible with CMOS technologies.

Ces travaux de recherche se rapportent à l'étude de transistors HEMTs en Nitrure de Gallium pour l'amplification de puissance micro-onde. Une étude des caractéristique des matériaux grand gap et plus particulièrement du GaN est réaliséé afin de mettre en exergue l'adéquation de leurs propriétés pour les applications de puissance hyperfréquence telle que l'amplification large bande. Dans ce contexte, des résultats de caractérisations et modélisations électriques de composants passifs et actifs sont présentés. Les composants passifs dédiés aux conceptions de circuits MMIC sont décrits et différentes méthodes d'optimisation que ce soit au niveau électrique ou électromagnétique sont explicitées. Les modèles non linéaires de transistors impliqués dans nos conceptions sont de même détaillés. Le fruit de ces travaux concerne la conception d'amplificateurs distribués de puissance large bande à base de cellules cascode de HEMTs GaN, l'un étant reportés en flip-chip sur un substrat d'AlN, le second en technologie MMIC. La version MMIC permet d'atteindre 6.3W sur la bande 4-18GHz à 2dB de compression. Ces résultats révèlent les fortes potetialités attendues des composants HEMTs GaN.

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d'entretien de type Colpitts,la mise en forme et jusqu'à l'adaptation du signal à sa charge d'utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s'orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del'architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l'avons reportée par flip chip sur une interfacespécifique pour

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material. Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges. The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The xvi thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.

Because of the tremendous amount of media streaming, video calling and high definition TV and gaming, the biggest challenge for the wireless industry is the increasing demand of high data rates. Utilization of mm-wave frequencies is an attractive option to meet this high demand. Recent advances in low cost semiconductor technologies allow realization of low-cost on-chip RF front-ends in the high millimeter wave (mm-wave) frequencies, making it possible to realize compact systems for these application areas. Although integrated circuits (ICs) are one of the main building blocks of a mm-wave system, in order to realize a fully functional wireless system, cost-effective antenna design and packaging are two important pre-conditions. Researchers have investigated and reported low-cost electronics packaging up to 100 GHz to a great extent on ceramic substrates, but mm-wave packaging above 100 GHz is relatively less explored, particularly on organic substrates. This Ph.D. dissertation demonstrates the design and development of microwave and mm-wave on-chip and on-package antennas and organically packaged components and modules ranging from 20 GHz to 170 GHz. The focus of this research was to design and develop mm-wave components and modules on LCP, to investigate the viability of this organic substrate and development of fabrication techniques in the K- (18-26.5 GHz), V- (50 to 70 GHz), W- (75 to 110 GHz), and D- (110 to 170 GHz) bands. Additionally, a demonstration of a micro-machined on-chip antenna has also been presented. This dissertation is divided in three parts: (1) characterization of liquid crystal polymer from 110 to 170 GHz. (2) development of highly radiation efficient on-chip and AiP antennas, and (3) development of mm-wave modules with the integration of antennas.

It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 μm thick silicon tiles between two substrates spaced 195 μm apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques. / Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

The objective of the proposed research is to design, implement, and characterize low-cost, lightweight front-end components and subsystems in the microwave domain through innovative packaging architectures for remote sensing applications. Particular emphasis is placed on system-on-package (SoP) solutions implemented in organic substrates as a low-cost alternative to conventional, expensive, rigid, and fragile radio- frequency substrates. To this end, the dielectric properties of organic substrates RT/duroid 5880, 6002 and 6202 are presented from 30 GHz to 70 GHz, covering most of the Ka and V radar bands, giving also a thorough insight on the uncertainty of the microstrip ring resonator method by means of the Monte Carlo uncertainty analysis. Additionally, an ultra-thin, high-power antenna-array technology, with transmit/ receive (T/R) functionality is introduced for mobile applications in the X band. Two lightweight SoP T/R array panels are presented in this work using novel technologies such as Silicon Germanium integrated circuits and microelectromechanical system switches on a hybrid organic package of liquid crystal polymer and RT/duroid 5880LZ. A maximum power of 47 dBm is achieved in a package with a thickness of 1.8 mm without the need of bulky thermal management devices. Finally, to address the thermal limitations of thin-film substrates of interest (liquid crystal polymer, RT/duroid 6002, alumina and Aluminum Nitride), a thermal assessment of microstrip structures is presented in the X band, along with the thermal characterization of the dielectric properties of RT/duroid 6002 from 20 ºC to 200 ºC and from 30 GHz to 70 GHz. Additional high-power, X-band technologies presented in this work include: a novel and compact topology for evanescent mode filters, and low-profile Wilkinson power dividers implemented on Aluminum Nitride using Tantalum Nitride thin-film resistors.