The downscaling of transistors is assumed to come to an end within the next years, and the semiconductor nonvolatile memories are facing the same physical downscaling challenge. Therefore, it is necessary to consider new computing paradigms and new memory concepts. Resistive switching devices (also referred to as memristive switches) are two-terminal passive device, which offer a nonvolatile switching behavior by applying short bias pulses. They have been considered as one of the most promising candidates for next generation memory and nonvolatile logic applications. They provide the possibility to carry out the information processing and storage simultaneously using the same resistive switching device. This dissertation focuses on the fabrication and characterization of BiFeO3 (BFO)-based metal-insulator-metal (MIM) devices in order to exploit the potential applications in nonvolatile memory and nonvolatile reconfigurable logics. Electroforming-free bipolar resistive switching was observed in MIM structures with BFO single layer thin film. The resistive switching mechanism is understood by a model of a tunable bottom Schottky barrier. The oxygen vacancies act as the mobile donors which can be redistributed under the writing bias to change the bottom Schottky barrier height and consequently change the resistance of the MIM structures. The Ti atoms diffusing from the bottom electrode act as the fixed donors which can effectively trap and release oxygen vacancies and consequently stabilize the resistive switching characteristics. The resistive switching behavior can be engineered by Ti implantation of the bottom electrodes. MIM structures with BiFeO3/Ti:BiFeO3 (BFO/BFTO) bilayer thin films show nonvolatile resistive switching behavior in both positive and negative bias range without electroforming process. The resistance state of BFO/BFTO bilayer structures depends not only on the writing bias, but also on the polarity of reading bias. For reconfigurable logic applications, the polarity of the reading bias can be used as an additional logic variable, which makes it feasible to program and store all 16 Boolean logic functions simultaneously into the same single cell of BFO/BFTO bilayer MIM structure in three logic cycles. / Die Herunterskalierung von Transistoren für die Informationsverarbeitung in der Halbleiterindustrie wird in den nächsten Jahren zu einem Ende kommen. Auch die Herunterskalierung von nichtflüchtigen Speichern für die Informationsspeicherung sieht ähnlichen Herausforderungen entgegen. Es ist daher notwendig, neue IT-Paradigmen und neue Speicherkonzepte zu entwickeln. Das Widerstandsschaltbauelement ist ein elektrisches passives Bauelement, in dem ein der Widerstand mittels elektrischer Spannungspulse geändert wird. Solche Widerstandsschaltbauelemente zählen zu den aussichtsreichsten Kandidaten für die nächste Generation von nichtflüchtigen Speichern sowie für eine rekonfigurierbare Logik. Sie bieten die Möglichkeit zur gleichzeitigen Informationsverarbeitung und -speicherung. Der Fokus der vorliegenden Arbeit liegt bei der Herstellung und der Charakterisierung von BiFeO 3 (BFO)-basierenden Metal-insulator-Metall (MIM) Strukturen, um zukünftig deren Anwendung in nichtflüchtigen Speichern und in rekonfigurierbaren Logikschaltungen zu ermöglichen. Das Widerstandsschalten wurde in MIM-Strukturen mit einer BFO-Einzelschicht untersucht. Ein besonderes Merkmal von BFO-basierten MIM-Strukturen ist es, dass keine elektrische Formierung notwendig ist. Der Widerstandsschaltmechnismus wird durch das Modell einer variierten Schottky-Barriere erklärt. Dabei dienen Sauerstoff-Vakanzen im BFO als beweglichen Donatoren, die unter der Wirkung eines elektrischen Schreibspannungspulses nichtflüchtig umverteilt werden und die Schottky-Barriere des Bottom-Metallkontaktes ändern. Dabei spielen die während der Herstellung von BFO substitutionell eingebaute Ti-Donatoren in der Nähe des Bottom-Metallkontaktes eine wesentliche Rolle. Die Ti-Donatoren fangen Sauerstoff-Vakanzen beim Anlegen eines positiven elektrischen Schreibspannungspulses ein oder lassen diese beim Anlegen eines negativen elektrischen Schreibspannungspules wieder frei. Es wurde gezeigt, dass die Ti-Donatoren auch durch Ti-Implantation der Bottom-Elektrode in das System eingebracht werden können. MIM-Strukturen mit BiFeO 3 /Ti:BiFeO 3 (BFO/BFTO) Zweischichten weisen substitutionell eingebaute Ti-Donatoren sowohl nahe der Bottom-Elektrode als auch nahe der Top-Elektrode auf. Sie zeigen nichtflüchtiges, komplementäres Widerstandsschalten mit einer komplementär variierbaren Schottky-Barriere an der Bottom-Elektrode und an der Top-Elektrode ohne elektrische Formierung. Der Widerstand der BFO/BFTO-MIM-Strukturen hängt nicht nur von der Schreibspannung, sondern auch von der Polarität der Lesespannung ab. Für die rekonfigurierbaren logischen Anwendungen kann die Polarität der Lesespannung als zusätzliche Logikvariable verwendet werden. Damit gelingt die Programmierung und Speicherung aller 16 Booleschen Logik-Funktionen mit drei logischen Zyklen in dieselbe BFTO/BFO MIM-Struktur.

The downscaling of transistors is assumed to come to an end within the next years, and the semiconductor nonvolatile memories are facing the same physical downscaling challenge. Therefore, it is necessary to consider new computing paradigms and new memory concepts. Resistive switching devices (also referred to as memristive switches) are two-terminal passive device, which offer a nonvolatile switching behavior by applying short bias pulses. They have been considered as one of the most promising candidates for next generation memory and nonvolatile logic applications. They provide the possibility to carry out the information processing and storage simultaneously using the same resistive switching device. This dissertation focuses on the fabrication and characterization of BiFeO3 (BFO)-based metal-insulator-metal (MIM) devices in order to exploit the potential applications in nonvolatile memory and nonvolatile reconfigurable logics. Electroforming-free bipolar resistive switching was observed in MIM structures with BFO single layer thin film. The resistive switching mechanism is understood by a model of a tunable bottom Schottky barrier. The oxygen vacancies act as the mobile donors which can be redistributed under the writing bias to change the bottom Schottky barrier height and consequently change the resistance of the MIM structures. The Ti atoms diffusing from the bottom electrode act as the fixed donors which can effectively trap and release oxygen vacancies and consequently stabilize the resistive switching characteristics. The resistive switching behavior can be engineered by Ti implantation of the bottom electrodes. MIM structures with BiFeO3/Ti:BiFeO3 (BFO/BFTO) bilayer thin films show nonvolatile resistive switching behavior in both positive and negative bias range without electroforming process. The resistance state of BFO/BFTO bilayer structures depends not only on the writing bias, but also on the polarity of reading bias. For reconfigurable logic applications, the polarity of the reading bias can be used as an additional logic variable, which makes it feasible to program and store all 16 Boolean logic functions simultaneously into the same single cell of BFO/BFTO bilayer MIM structure in three logic cycles. / Die Herunterskalierung von Transistoren für die Informationsverarbeitung in der Halbleiterindustrie wird in den nächsten Jahren zu einem Ende kommen. Auch die Herunterskalierung von nichtflüchtigen Speichern für die Informationsspeicherung sieht ähnlichen Herausforderungen entgegen. Es ist daher notwendig, neue IT-Paradigmen und neue Speicherkonzepte zu entwickeln. Das Widerstandsschaltbauelement ist ein elektrisches passives Bauelement, in dem ein der Widerstand mittels elektrischer Spannungspulse geändert wird. Solche Widerstandsschaltbauelemente zählen zu den aussichtsreichsten Kandidaten für die nächste Generation von nichtflüchtigen Speichern sowie für eine rekonfigurierbare Logik. Sie bieten die Möglichkeit zur gleichzeitigen Informationsverarbeitung und -speicherung. Der Fokus der vorliegenden Arbeit liegt bei der Herstellung und der Charakterisierung von BiFeO 3 (BFO)-basierenden Metal-insulator-Metall (MIM) Strukturen, um zukünftig deren Anwendung in nichtflüchtigen Speichern und in rekonfigurierbaren Logikschaltungen zu ermöglichen. Das Widerstandsschalten wurde in MIM-Strukturen mit einer BFO-Einzelschicht untersucht. Ein besonderes Merkmal von BFO-basierten MIM-Strukturen ist es, dass keine elektrische Formierung notwendig ist. Der Widerstandsschaltmechnismus wird durch das Modell einer variierten Schottky-Barriere erklärt. Dabei dienen Sauerstoff-Vakanzen im BFO als beweglichen Donatoren, die unter der Wirkung eines elektrischen Schreibspannungspulses nichtflüchtig umverteilt werden und die Schottky-Barriere des Bottom-Metallkontaktes ändern. Dabei spielen die während der Herstellung von BFO substitutionell eingebaute Ti-Donatoren in der Nähe des Bottom-Metallkontaktes eine wesentliche Rolle. Die Ti-Donatoren fangen Sauerstoff-Vakanzen beim Anlegen eines positiven elektrischen Schreibspannungspulses ein oder lassen diese beim Anlegen eines negativen elektrischen Schreibspannungspules wieder frei. Es wurde gezeigt, dass die Ti-Donatoren auch durch Ti-Implantation der Bottom-Elektrode in das System eingebracht werden können. MIM-Strukturen mit BiFeO 3 /Ti:BiFeO 3 (BFO/BFTO) Zweischichten weisen substitutionell eingebaute Ti-Donatoren sowohl nahe der Bottom-Elektrode als auch nahe der Top-Elektrode auf. Sie zeigen nichtflüchtiges, komplementäres Widerstandsschalten mit einer komplementär variierbaren Schottky-Barriere an der Bottom-Elektrode und an der Top-Elektrode ohne elektrische Formierung. Der Widerstand der BFO/BFTO-MIM-Strukturen hängt nicht nur von der Schreibspannung, sondern auch von der Polarität der Lesespannung ab. Für die rekonfigurierbaren logischen Anwendungen kann die Polarität der Lesespannung als zusätzliche Logikvariable verwendet werden. Damit gelingt die Programmierung und Speicherung aller 16 Booleschen Logik-Funktionen mit drei logischen Zyklen in dieselbe BFTO/BFO MIM-Struktur.

In order to meet the requests of the application as pixel switch and current driver in next generation active-matrix liquid crystal displays (AMLCD) and active-matrix organic light-emitting diodes (AMOLED). The materials of low temperature poly-silicon (LTPS) and metal-oxide are supposed to be the most potential material for active layer of thin-film transistors (TFTs) due to their high mobility compared to the traditional amorphous silicon TFTs. Therefore, in order to make the LTPS TFTs and metal-oxide TFTs affordable for the practical applications, the understanding of instability and reliability is critically important. In the first part, we studied the nonvolatile memory characteristics of polycrystalline-silicon thin-film-transistors (poly-Si TFTs) with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant gate induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection method to counteract programmed electrons and this method can exhibit good sustainability because the injected hot holes can remain in the nitride layer after repeated operations. On the other hand, we also investigated the degradation behavior of SONOS-TFT under off-state stress. After the electrical stress, the significant on-state degradation indicates that the interface states accompanied with hot-hole injection. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Furthermore, we also performed the identical off-state stress for the device with different memory states. The different degradation behavior under different memory states is attributed to the different overlap region of injected holes and trap states. In the second part, the degradation mechanism of indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs) caused by gate-bias stress performed in the dark and light illumination was investigated. The parallel threshold voltage indicates that charge trapping model dominates the degradation behavior under positive gate-bias stress. However, the degradation of negative gate bias stress is much slighter than the positive gate bias stress since the IGZO material is hard to induced hole inversion layer. In addition, the hole mobility is much lower than electron resulting in ignorable hole trapping effect. On the other hand, the identical positive and negative gate bias stress performed under light illumination exhibit opposite degradation behavior compared with dark stress. This degradation variation under dark and light illumination can be attributed to the effectively energy barrier variation of electron and hole trapping. Furthermore, to further investigate the light induced instability for IGZO TFTs, the device with and without a SiOx passivation were investigated under light illumination. The experiment results indicate that oxygen adsorption and desorption dominate the light induced instability for unpassivated device and the trap states caused during the passivation layer deposition process will induce apparent subthreshold photo-leakage current under light illumination. In the third part, we investigated the degradation mechanism of IGZO TFTs under hot-carrier and self-heating stress. Under hot-carrier stress, except the electron trapping induced positive Vt shift, an apparent on-current degradation behavior indicates that trap states creation. On the other hand, the identical hot-carrier stress performed in the asymmetric source/drain structure exhibits different degradation behavior compared with symmetric source/drain structure. For asymmetric structure, the strong electrical field in the I-shaped drain electrode will induce channel hot electron injection near the drain side and cause asymmetric threshold voltage degradation. In this part we also investigated the degradation behavior under self-heating stress. The apparent positive threshold voltage (Vt) shift and on-current degradation indicate that the combination of trap states generation and electron trapping effect occur during stress. The trap states generation is caused by the combination of Joule heating and the large vertical field. Moreover, the Joule heating generated by self-heating operation can enhance electron trapping effect and cause larger Vt shift in comparison with the gate-bias stress. Finally, the electrical properties and photo sensitivity of dual gate IGZO TFTs were investigated. The asymmetric electrical properties and photo sensitivity under top gate and bottom gate operation is attributed to the variation of gate control region. Furthermore, the obvious asymmetric photo sensitivity can be utilized to the In-cell touch panel technology and lower the process cost compared with the traditional a-Si TFTs due to the elimination of black matrix.

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations.

Charged domain walls (CDWs) in proper ferroelectrics are a novel route towards the creation of advancing functional electronics. At CDWs the spontaneous polarization obeying the ferroelectric order alters abruptly within inter-atomic distances. Upon screening, the resulting charge accumulation may result in the manifestation of novel fascinating electrical properties. Here, we will focus on electrical conduction. A major advantage of these ferroelectric DWs is the ability to control its motion upon electrical fields. Hence, electrical conduction can be manipulated, which can enrich the possibilities of current electronic devices e.g. in the field of reconfigurability, fast random access memories or any kind of adaptive electronic circuitry. In this dissertation thesis, I want to shed more light onto this new type of interfacial electronic conduction on inclined DWs mainly in lithium niobate/LiNbO3 (LNO). The expectation was: the stronger the DW inclination towards the polar axis of the ferroelectric order and, hence, the larger the bound polarization charge, the larger the conductivity to be displayed. The DW conductance and the correlation with polarization charge was investigated with a multitude of experimental methods as scanning probe microscopy, linear and nonlinear optical microscopy as well as electron microscopy. We were able to observe a clear correlation of the local DW inclination angle with the DW conductivity by comparing the three-dimensional DW data and the local DW conductance. We investigated the conduction mechanisms on CDWs by temperature-dependent two-terminal current-voltage sweeps and were able to deduce the transport to be given by small electron polaron hopping, which are formed after injection into the CDWs. The thermal activated transport is in very good agreement with time-resolved polaron luminescence spectroscopy. The applicability of this effect for non-volatile memories was investigated in metal-ferroelectric-metal stacks with CMOS compatible single-crystalline films. These films showed unprecedented endurance, retention, precise set voltage, and small leakage currents as expected for single crystalline material. The conductance was tuned and switched according to DW switching time and voltage. The formation of CDWs has proven to be extremely stable over at least two months. The conductivity was further investigated via microwave impedance microscopy, which revealed a DW conductivity of about 100 to 1000 S/m at microwave frequencies of about 1 GHz. / Geladene Domänenwände (DW) in reinen Ferroelektrika stellen eine neue Möglichkeit zur Erzeugung zukünftiger, funktionalisierter Elektroniken dar. An geladenen DW ändert sich die Polarisation sehr abrupt - innerhalb nur weniger Atomabstände. Sofern die dadurch hervorgerufene Ladungsträgeranreicherung elektrisch abgeschirmt werden kann, könnte dies zu faszinierenden elektrischen Eigenschaften führen. Wir möchten uns hierbei jedoch auf die elektrische Leitfähigkeit beschränken. Ein großer Vorteil für die Anwendung leitfähiger DW ist deren kontrollierte Bewegung unter Einwirkung elektrischer Felder. Dies ermöglicht die Manipulation das Ladungstransports, welches zum Beispiel im Bereich der Rekonfigurierbarkeit, schneller Speicherbauelemente und jeder Art von adaptiven elektronischen Schaltungen Anwendung finden kann. In dieser Dissertationsschrift möchte ich diesen neuen Typus grenzflächiger elektronischen Ladungstransports an geladenen DW hauptsächlich am Beispiel von Lithiumniobat/-LiNbO3 (LNO) untersuchen. Die Annahme lautete hierbei: umso stärker die DW zur ferroelektrischen Achse geneigt ist, also desto stärker die gebundene Polarisationsladung und folglich die elektrische DW-Leitfähigkeit. Die elektrische DW-Leitfähigkeit und die Korrelation mit der Polarisationsladung wurde mit verschiedenen experimentellen Methoden wie Rasterkraftmikroskopie, linearer und nichtlinearer optischer Mikroskopie als auch Elektronenmikroskopie untersucht. Es konnte eine klare Korrelation durch Vergleich der dreidimensionalen DW-Aufzeichnungsdaten mit der lokalen Leitfähigkeit gezeigt werden. Wir haben weiterhin den Leitfähigkeitsmechanismus an geladenen DW mittels temperaturabhängiger Strom-Spannungskennlinien untersucht und konnten hierbei einen Hopping-Transport kleiner Elektronenpolaronen nachweisen, welche nach Elektroneninjektion in die geladene DW generiert werden. Der thermisch aktivierte Ladungsträgertransport ist in guter Übereinstimmung mit zeitaufgelöster Polaron-Lumineszenzspektroskopie. Die Anwendbarkeit dieses Effektes für nicht-volatile Speicherbauelemente wurde an Metall-Ferroelektrika-Metall Schichtstrukturen mit CMOS-kompatiblen einkristalliner Filmen untersucht. Die Filme zeigen bisher nichtgesehene Durchhalte- und Speichervermögen, genau definierte Schaltspannung sowie sehr geringe Leckageströme wie dies für einkristalline Materialsysteme erwartet wird. Die Leitfähigkeit konnte mittels entsprechender Wahl der elektrischen Schaltzeiten und -spannungen zielgerichtet manipuliert und geschalten werden. Es konnte darüber hinaus gezeigt werden, dass die hergestellten geladenen DW über eine Zeitspanne von mindestens zwei Monaten stabil sind und hierbei leitfähig bleiben. Die Leitfähigkeit der DW wurde weiterhin mittels Mikrowellenimpedanzmikroskopie untersucht. Dabei konnten DW-Leitfähigkeiten von 100 bis 1000 S/m für Mikrowellenfrequenzen von etwa 1GHz ermittelt werden.

Ferroelectricity is a material property were a remanent polarization exists under zero electrical field that can be reversed by applying an electrical field [1]. As consequence, two nonvolatile states exist that can be switched by an electrical field. This feature makes ferroelectrics ideally suited for nonvolatile memories with low write energy. Therefore, already in the 1950s first attempts have been made to realize ferroelectric nonvolatile memories based on ferroelectric barium titanate (BTO) crystals having evaporated electrodes on both sides [2]. The success of this approach was hindered by disturb issues that could be solved in the early 1990s by adding a transistor device as a selector [3]. Such a memory is referred to as a ferroelectric random access memory (FeRAM). Since reading of the ferroelectric polarization from a capacitor requires switching of the ferroelectric [1], the information will be destroyed and a write back is necessary. This can be avoided if the ferroelectric is placed inside of the gate stack of a MOS transistor resulting in a ferroelectric field effect transistor (FeFET) [1]. Conventional ferroelectric materials like BTO or lead- zirconium titanate (PZT) cannot be placed directly on silicon since unwanted interface reactions will occur. The necessary interface layer together with the space charge region of the transistor device leads to a rather low capacitance in series with the ferroelectric dielectric and consequently results in a strong depolarization field that has destroyed the nonvolatility of the FeFET device for many years and hinters scaling as well [4]. Today FeRAM devices are established on the market [3,5], but are limited to niche application since scaling is hindered by many integration problems associated to materials like PZT.

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations.

Reconfigurable transistors merge unipolar p- and n-type characteristics of field-effect transistors into a single programmable device. Combinational circuits have shown benefits in area and power consumption by fine-grain reconfiguration of complete logic blocks at runtime. To complement this volatile programming technology, a proof of concept for individually addressable reconfigurable nonvolatile transistors is presented. A charge-trapping stack is incorporated, and four distinct and stable states in a single device are demonstrated.

The new class of fully silicon-compatible hafnia-based ferroelectrics with high switchable polarization and good endurance and thickness scalability shows a strong promise for new generations of logic and memory devices. Among other factors, their competitiveness depends on the power efficiency that requires reliable low-voltage operation. Here, we show genuine ferroelectric switching in HfₓZr₍₁₋ₓ₎ O₂ (HZO) layers in the application-relevant capacitor geometry, for driving signals as low as 800 mV and coercive voltage below 500 mV. Enhanced piezoresponse force microscopy with sub-picometer sensitivity allowed for probing individual polarization domains under the top electrode and performing a detailed analysis of hysteretic switching. The authentic local piezoelectric loops and domain wall movement under bias attest to the true ferroelectric nature of the detected nanodomains. The systematic analysis of local piezoresponse loop arrays reveals a totally unexpected thickness dependence of the coercive fields in HZO capacitors. The thickness decrease from 10 to 7 nm is associated with a remarkably strong decrease of the coercive field, with about 50% of the capacitor area switched at coercive voltages ≤0.5 V. Our explanation consistent with the experimental data involves a change of mechanism of nuclei-assisted switching when the thickness decreases below 10 nm. The practical implication of this effect is a robust ferroelectric switching under the millivolt-range driving signal, which is not expected for the standard coercive voltage scaling law. These results demonstrate a strong potential for further aggressive thickness reduction of HZO layers for low-power electronics.

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.