Made available in DSpace on 2016-06-02T20:29:25Z (GMT). No. of bitstreams: 1 5524.pdf: 3450663 bytes, checksum: 5c20224069dc077254a4ac63720751eb (MD5) Previous issue date: 2013-08-23 / The main objective of this work is to report a didactic experience with activities different of the commonly used in school activities. Stands out the importance of linking the mathematical content with the daily affairs of the students. By observing the students' disinterest in learning math, the many questions about where they could use the knowledge learned in school in their everyday life, and by observing the difficulty that students often have in understanding the formation of a numbering system, we designed a work exploring the binary numbering system. As it is very present in the technologies, which we no longer can avoid, and for being a structured system like all others, differing only by the base used, he became the focus of the study. The binary numbering system was introduced to the students through practical activities that aroused the curiosity of them about the possibility of writing numbers and letters using only the digits 0 and 1. / O objetivo central desse trabalho é relatar uma experiência didática com atividades diferentes das comumente utilizadas nas atividades escolares. Destaca-se a importância de relacionar os conteúdos matemáticos escolares com assuntos do cotidiano dos estudantes. Devido a observação do desinteresse dos alunos em aprender matemática, dos muitos questionamentos sobre onde poderiam usar o conhecimento aprendido na escola em seu cotidiano, além da observação da dificuldade que os alunos costumam apresentar no entendimento da formação de um sistema de numeração, foi elaborado um trabalho explorando o sistema de numeração binário. Como ele está muito presente nas tecnologias, das quais não temos mais como nos desvincular, e por ser um sistema estruturado como todos os outros, apenas diferenciando-se pela base utilizada, ele se tornou o foco do estudo. O sistema de numeração binário foi apresentado aos alunos por meio de atividades práticas que despertaram a curiosidade dos mesmos sobre a possibilidade de escrever números e letras usando apenas os algarismos 0 e 1.

De nos jours, la compression de l'image médicale est un processus essentiel dans les systèmes de cybersanté. Compresser des images médicales de haute qualité est une exigence vitale pour éviter de mal diagnostiquer les examens médicaux par les radiologues. WAAVES est un algorithme de compression d'images médicales prometteur basé sur la transformée en ondelettes discrètes (DWT) qui permet d'obtenir une performance de compression élevée par rapport à l'état de la technique. Les principaux objectifs de ce travail sont d'améliorer la qualité d'image lors de la compression à l'aide de WAAVES et de fournir une architecture DWT haute vitesse pour la compression d'image sur des systèmes embarqués. En ce qui concerne l'amélioration de la qualité, les systèmes de nombres logarithmiques (LNS) ont été explorés pour être utilisés comme une alternative à l'arithmétique linéaire dans les calculs de DWT. Une nouvelle bibliothèque LNS a été développée et validée pour réaliser le DWT logarithmique. En outre, une nouvelle méthode de quantification appelée (LNS-Q) basée sur l'arithmétique logarithmique a été proposée. Un nouveau schéma de compression (LNS-WAAVES) basé sur l'intégration de la méthode Hybrid-DWT et de la méthode LNS-Q avec WAAVES a été développé. Hybrid-DWT combine les avantages des domaines logarithmique et linéaire conduisant à l'amélioration de la qualité d'image et du taux de compression. Les résultats montrent que LNS-WAAVES est capable d'obtenir une amélioration de la qualité d'un pourcentage de 8% et de 34% par rapport aux WAAVES en fonction des paramètres de configuration de compression et des modalités d'image. Pour la compression sur les systèmes embarqués, le défi majeur consistait à concevoir une architecture 2D DWT qui permet d'obtenir un débit de 100 trames full HD. Une nouvelle architecture unifiée de calcul 2D DWT a été proposée. Cette nouvelle architecture effectue à la fois des transformations horizontale et verticale simultanément et élimine le problème des accès de pixel d'image en colonne à partir de la RAM DDR hors-puce. Tous ces facteurs ont conduit à une réduction de la largeur de bande DDR RAM requise de plus de 2X. Le concept proposé utilise des tampons de ligne à 4 ports conduisant à quatre opérations en parallèle pipeline: la DWT verticale, la transformée DWT horizontale et les opérations de lecture / écriture vers la mémoire externe. L'architecture proposée a seulement 1/8 de cycles par pixel (CPP) lui permettant de traiter plus de 100fps Full HD et est considérée comme une solution prometteuse pour le futur traitement vidéo 4K et 8K. Enfin, l'architecture développée est hautement évolutive, surperforme l'état de l'art des travaux connexes existants, et est actuellement déployé dans un prototype médical EEG vidéo. / Nowadays, medical image compression is an essential process in eHealth systems. Compressing medical images in high quality is a vital demand to avoid misdiagnosing medical exams by radiologists. WAAVES is a promising medical images compression algorithm based on the discrete wavelet transform (DWT) that achieves a high compression performance compared to the state of the art. The main aims of this work are to enhance image quality when compressing using WAAVES and to provide a high-speed DWT architecture for image compression on embedded systems. Regarding the quality improvement, the logarithmic number systems (LNS) was explored to be used as an alternative to the linear arithmetic in DWT computations. A new LNS library was developed and validated to realize the logarithmic DWT. In addition, a new quantization method called (LNS-Q) based on logarithmic arithmetic was proposed. A novel compression scheme (LNS-WAAVES) based on integrating the Hybrid-DWT and the LNS-Q method with WAAVES was developed. Hybrid-DWT combines the advantages of both the logarithmic and the linear domains leading to enhancement of the image quality and the compression ratio. The results showed that LNS-WAAVES is able to achieve an improvement in the quality by a percentage of 8% and up to 34% compared to WAAVES depending on the compression configuration parameters and the image modalities. For compression on embedded systems, the major challenge was to design a 2D DWT architecture that achieves a throughput of 100 full HD frame/s. A novel unified 2D DWT computation architecture was proposed. This new architecture performs both horizontal and vertical transform simultaneously and eliminates the problem of column-wise image pixel accesses to/from the off-chip DDR RAM. All of these factors have led to a reduction of the required off-chip DDR RAM bandwidth by more than 2X. The proposed concept uses 4-port line buffers leading to pipelined parallel four operations: the vertical DWT, the horizontal DWT transform, and the read/write operations to the external memory. The proposed architecture has only 1/8 cycles per pixel (CPP) enabling it to process more than 100fps Full HD and it is considered a promising solution for future 4K and 8K video processing. Finally, the developed architecture is highly scalable, outperforms the state of the art existing related work, and currently is deployed in a video EEG medical prototype.

De nombreuses études ont montré qu'il existe deux systèmes indépendants permettant une représentation de la numérosité sans l'utilisation des noms des nombres. Ces deux systèmes ont été mis en évidence chez l'adulte, l'animal, ainsi que chez le nourrisson. Le premier système permet une représentation approximative de la numérosité: la capacité à discriminer entre deux numérosités dépend alors de leur ratio. Le second système a pour rôle initial le suivi spatio-temporel d'objets. L'individuation, en parallèle, de différents objets permet ainsi au système d'abstraire de façon indirecte la numérosité d'un ensemble. Contrairement au premier système, le second permet d'encoder de manière exacte la numérosité mais présente toutefois une limite quant au nombre d'items pouvant être suivis (4 pour l'adulte, 3 pour le nourrisson à partir de 5 mois). Si ces deux systèmes ont été mis en évidence chez le nourrisson avant l'acquisition des mots des nombres, la question de leur apparition et de leurs liens persiste toujours. Alors que le système approximatif a été mis en évidence dès la naissance, nous n'avons pas de preuves empiriques de l'existence du second système au même âge. C'est pourquoi, à travers deux groupes d'études, nous cherché à mettre en évidence l'existence d'un système spécifique des petits ensembles chez le nouveau-né, en utilisant des situations bimodales audio-visuelles. Le premier ensemble d'expériences a montré l'existence d'une dissociation entre les petites et les grandes numérosités. Les expériences suivantes ont permis de mettre en évidence l'existence du système pour les petits ensembles dès la naissance, mais qui présente toutefois une limite de suivi à deux items et non trois comme pour les nourrissons plus âgés. Afin d'étudier l'articulation entre les deux systèmes, une expérience, décrite dans un chapitre supplémentaire, a été réalisée chez le nourrisson de 5 mois testant la discrimination continue de la numérosité, à l'aide d'un paradigme de transfert intermodal entre le toucher et la vision. / Many studies showed that two systems are available to encode numerosities without the use of number words. These two systems have been shown to exist in adults, animals, and also in infants. The first system can represent approximate numerosities: the capacity to discriminate between two numerosities depends on their ratio difference. The second system has for primary role the spatiotemporal tracking of objects. The parallel individuation of several objects enables the system to encode implicitly the numerosity of a set. Contrary to the first system, the second can encode exact numerosities, however this system is limited by the number of objects that can be tracked (4 in adults, 3 in infants from 5 months of age). These two systems have been shown to exist in infants before the acquisition of number words, however, the question of their emergence and of their links remains. While a study showed that the approximate system exists from birth on, we do not know if the second system exists at the same age. In two series of studies, using audiovisual bimodal situations, we tested the existence of a system specific for small sets in newborn infants. The first set of experiments showed a dissociation between small and large numerosities. The next experiments revealed the existence of the system for small sets from birth on, however this system appears to be limited to 2 objects, while it has a limit of 3 in older infants. In order to study the link between the two systems for encoding numerosity, a third group of experiments was conducted with 5-month-old infants. These experiments, described in a supplementary chapter, tested the continuity between small and large numerosities using a crossmodal transfer paradigm between tactile and visual modalities.

The thesis deals with speedup and accuracy of numerical computation, especially when differential equations are solved. Algorithms, which are fulling these conditions are named semi-analytical. One posibility how to accelerate computation of differential equation is paralelization. Presented paralelization is based on transformation numerical solution into residue number system, which is extended to floating point computation. A new algorithm for modulo multiplication is also proposed. As application applications in solution of differential calculus are the main goal it is discussed numeric integration with modified Euler, Runge - Kutta and Taylor series method in residue number system. Next possibilities and extension for implemented residue number system are mentioned at the end.

Η υλοποίηση αποδοτικών αριθμητικών κυκλωμάτων αποτελεί ένα ανοικτό πεδίο έρευνας καθώς η συνεχής εξέλιξη της τεχνολογίας απαιτεί την επανεκτίμηση των μεθόδων σχεδίασής τους, ενώ παράλληλα δημιουργεί νέους τομείς εφαρμογής τους. Ο τεράστιος όγκος πληροφορίας και η ανάγκη γρήγορης επεξεργασίας της έχει οδηγήσει στην ανάγκη αύξησης της συχνότητας λειτουργίας των αντίστοιχων κυκλωμάτων. Μεγάλης σημασίας παραμένει επίσης η ανάγκη για τη μείωση της κατανάλωσης ισχύος των συστημάτων αυτών, αλλά και του κόστους τους, που συνδέονται άμεσα με την επιφάνεια ολοκλήρωσής τους. Η ικανοποίηση των παραμέτρων αυτών επιτάσσει σε διάφορες περιπτώσεις την υιοθέτηση αριθμητικών συστημάτων, πέραν του συμβατικού δυαδικού συστήματος. Χαρακτηριστικά παραδείγματα αποτελούν το Αριθμητικό Σύστημα Υπολοίπων (Residue Number System – RNS) όπως επίσης και τα αριθμητικά συστήματα πλεοναζουσών αναπαραστάσεων (redundant number systems). Η διδακτορική αυτή διατριβή ασχολείται με την υλοποίηση αποδοτικών κυκλωμάτων για το Αριθμητικό Σύστημα Υπολοίπων, με την έρευνα να επικεντρώνεται στην υιοθέτηση τόσο πλεοναζουσών όσο και μη-πλεοναζουσών αναπαραστάσεων στα διάφορα κανάλια επεξεργασίας του. Το πρώτο μέρος της διατριβής έχει ως στόχο τη σχεδίαση αποδοτικών κυκλωμάτων υπολοίπων με χρήση μη-πλεοναζουσών αναπαραστάσεων τόσο για τις κύριες-βασικές αριθμητικές πράξεις (πρόσθεση, πολλαπλασιασμός) όσο και για τις δευτερεύουσες-βοηθητικές (αφαίρεση, ύψωση σε δύναμη) πράξεις. Συγκεκριμένα, παρουσιάζονται κυκλώματα αφαίρεσης και πρόσθεσης/αφαίρεσης για κανάλια υπολοίπου της μορφής 2^n+-1, κυκλώματα πολλαπλασιασμού με σταθερά για το σύνολο διαιρετών {2^n-1, 2^n, 2^n+1} καθώς και κυκλώματα Booth πολλαπλασιασμού προγραμματιζόμενης λογικής για τα κανάλια υπολοίπου 2^n+-1. Επιπλέον, παρουσιάζονται κυκλώματα ύψωσης στον κύβο για το κανάλι υπολοίπου 2^n-1. Προτείνεται επίσης μια οικογένεια αριθμητικών κυκλωμάτων (αθροιστές, αφαιρέτες, πολλαπλασιαστές, κυκλώματα ύψωσης στο τετράγωνο) υπολοίπου 2^n+1 για την αναπαράσταση ελάττωσης κατά 1, που ενσωματώνουν τη μετατροπή του αποτελέσματος στην κανονική αναπαράσταση μέσα στην αρχιτεκτονική τους, ενώ παρουσιάζεται και μία ενιαία μεθοδολογία σχεδίασης κυκλωμάτων ανάστροφης μετατροπής για σύνολα διαιρετών με κανάλια της μορφής 2^n+1 που υιοθετούν την αναπαράσταση ελάττωσης κατά 1. Τέλος, διερευνούνται και οι διαιρέτες της μορφής 2^n-2 και προτείνονται για αυτούς αποδοτικές αρχιτεκτονικές κυκλωμάτων πρόσθεσης, πολλαπλασιασμού, ύψωσης στο τετράγωνο και ευθείας μετατροπής. Στο δεύτερο μέρος της διατριβής το ενδιαφέρον εστιάζεται σε μία διαφορετική κατηγορία αναπαραστάσεων, οι οποίες παρέχουν περισσότερους από ένα δυνατούς τρόπους κωδικοποίησης των εντέλων τους. Οι πλεονάζουσες αυτές αναπαραστάσεις παρουσιάζουν συγκεκριμένα χαρακτηριστικά, όπως η δυνατότητα εξισορρόπησης ταχύτητας και επιφάνειας υλοποίησης. Στη διατριβή εξετάζονται τρεις πλεονάζουσες αναπαραστάσεις για το Αριθμητικό Σύστημα Υπολοίπων με κανάλια διαιρετών της μορφής 2^n+-1 και παρουσιάζεται μία γενικευμένη μεθοδολογία διαχείρισης των ψηφίων τους, η οποία εφαρμόζεται στη σχεδίαση κυκλωμάτων μετατροπής. Στο τελευταίο μέρος περιγράφονται δύο εφαρμογές συστημάτων που βασίζονται στο Αριθμητικό Σύστημα Υπολοίπων. Αναλυτικότερα, σχεδιάζεται και υλοποιείται ένα σύστημα ανίχνευσης ακμών σε εικόνα με ένα στάδιο προ-επεξεργασίας για μείωση του θορύβου καθώς και τρία φίλτρα πεπερασμένης κρουστικής απόκρισης. / The implementation of efficient arithmetic circuits has always been an open field for research, since the technology evolves rapidly, demanding the reevaluation of their design methods. At the same time this continuous evolution opens new research areas for these circuits. The need for fast processing of a vast amount of information demands an increase of the operational frequency of the corresponding circuits, while at the same time low power consumption, low cost and therefore low area remain of crucial importance. Meeting these needs in arithmetic circuits usually implies the employment of alternative, non-binary number systems. Such examples are the Residue Number System (RNS) and number systems with redundant representations. The subject of this PhD dissertation is the implementation of efficient arithmetic circuits for the RNS emphasizing both in redundant and not redundant representations. The first part of the dissertation deals with the design of efficient non-redundant arithmetic circuits for main arithmetic operations such as addition and multiplication that are met in every processing system, as well as for auxiliary operations like subtraction, squaring and cubing. Specifically, the circuits presented include subtractors and adders/subtractors for the moduli channels of the 2^n+-1 form, single-constant multipliers for the {2^n-1, 2^n, 2^n+1} moduli set, configurable modulo 2^n +-1 Booth-encoded multipliers as well as modulo 2^n-1 cubing units. Furthermore, a family of diminished-1 modulo 2^n+1 arithmetic circuits (adders, subtractors, multipliers and squarers) is also presented, that produces the respective result directly to weighted (normal) representation, embedding that way the conversion process between these two representations. The design of efficient Residue-to-Binary converters is also considered and a novel generic methodology is proposed for the systematic design of those circuits. The modulo 2^n-2 channel is also investigated and an arithmetic processing framework is proposed including adders, multipliers, squarers and Binary-to-Residue converters. In the second part, we focus on a different category of representations, where operands can be encoded in more than one ways. Such representations offer certain characteristics such as a tradeoff between area and speed. In particular, we consider three redundant representations for the RNS processing channels of the 2^n+-1 form, which are the most common choice. A generic methodology is presented for treating their digits in order to design efficient converters for them. The last part of the dissertation presents two applications that are implemented entirely in the RNS domain. Their architectures rely on the proposed arithmetic circuits. The first application is an image edge detector with a pre-processing noise filtering stage. The second application involves the design of three Finite Impulse Response (FIR) filters.

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).

Το αριθμητικό σύστημα υπολοίπων (RNS) έχει προταθεί ως ένας τρόπος για επιτάχυνση των αριθμητικών πράξεων του πολλαπλασιασμού και της πρόσθεσης. Ένα από τα σημαντικά πλεονεκτήματα της χρήσης του RNS είναι ότι οδηγεί σε κυκλώματα που έχουν το χαρακτηριστικό της χαμηλής κατανάλωσης. Πιο συγκεκριμένα στην παρούσα διατριβή γίνεται μια αναλυτική μελέτη πάνω στην ταχύτητα διεξαγωγής της πράξης του πολλαπλασιασμού και της άθροισης. Ο λόγος που γίνεται αυτό είναι διότι οι εφαρμογές επεξεργασίας σήματος χρησιμοποιούν ιδιαιτέρως τις προαναφερθείσες πράξεις. Επίσης γίνεται μελέτη της ισχύος που καταναλώνεται κατά την επεξεργασία ενός σήματος με τη χρήση των προτεινόμενων αριθμητικών κυκλωμάτων. Ιδιαίτερη έμφαση δίνεται στη χρήση απλών αρχιτεκτονικών τις οποίες μπορούν τα εργαλεία σύνθεσης να διαχειριστούν καλύτερα παράγοντας βέλτιστα κυκλώματα. Τέλος η διατριβή μελετά τα προβλήματα διακύμανσης των παραμέτρων του υλικού που αντιμετωπίζει η σύγχρονη τεχνολογία κατασκευής ολοκληρωμένων κυκλωμάτων. Συγκεκριμένα σε τεχνολογία μικρότερη των 90nm παρατηρείται το φαινόμενο ίδια στοιχεία κυκλώματος να συμπεριφέρονται με διαφορετικό τρόπο. Το φαινόμενο αυτό γίνεται σημαντικά πιο έντονο σε τεχνολογίες κάτω των 45nm. Η παρούσα διατριβή προτείνει λύσεις βασισμένες στην παραλληλία και την ανεξαρτησία των επεξεργαστικών πυρήνων που παρέχει το RNS, για να αντιμετωπίσει το συγκεκριμένο φαινόμενο. / The Residue Number System (RNS) has been proposed as a means to speed up the implementation of multiplication-addition intensive applications, commonly found in DSP. The main benefit of RNS is the inherent parallelism, which has been exploited to build efficient multiply-add structures, and more recently, to design low-power systems. In particular, this dissertation deals with the delay complexity of the multiply-add operation (MAC). The reason for this is that DSP applications are MAC intensive and hence this dissertation proposes solutions to increase the speed of processing. Furthermore, the study of the multiply-add operations is extended to power consumption matters. The dissertation focus on simple architectures such that EDA tools produce efficient in both power and delay, synthesized circuits. Finally the dissertation deals with variability matters that came up as the vlsi technology shrinks below 90nm. Variability becomes unaffordable especially for the 45nm technology node. This dissertation proposes solutions based on parallelism and the independence of the RNS cores to derive variation-tolerant architectures.

V systému s kódy zbytkových tříd je základem skupina navzájem nezávislých bází. Číslo ve formátu integer je reprezentováno kratšími čísly integer, které získáme jako zbytky všech bází, a aritmetické operace probíhají samostatně na každé bázi. Při aritmetických operacích nedochází k přenosu do vyšších řádů při sčítání, odečítání a násobení, které obvykle potřebují více strojového času. Srovnávání, dělení a operace se zlomky jsou komplikované a chybí efektivní algoritmy. Kódy zbytkových tříd se proto nepoužívají k numerickým výpočtům, ale jsou velmi užitečné pro digitální zpracování signálu. Disertační práce se týká návrhu, simulace a mikropočítačové implementace funkčních bloků pro digitální zpracování signálu. Funkční bloky, které byly studovány jsou nově navržené konvertory z binarní do reziduální reprezentace a naopak, reziduální sčítačka a násobička. Nově byly také navržené obslužné algoritmy.

Visual Type Instrument - VTI, is a tool containing a typeface and a set of geometric calculations that generates numerical data in spreadsheets. The data is determined from the typefaces visual dimensions and is used to calculate leading, type size, margins and format. The aim is to offer, for all of those working with typography and design, a practical way to manage text, image and format in relationship to visual size. Instead of using point measurements, VTI uses a new device called Edo. An Edo is the same as one twelfth of a millimetre. This makes VTI compatible with the metric system and helps us to set text in relation to our own formats which applies namely in millimetres.    VTI uses logical arithmetic and geometry that is set in an automated process, and many choices that normally postpone the working process can be excluded. Simultaneously VTI is meant to discreetly make the user aware that more settings can be activated in line with the users own development, which makes the creative flow unaffected.    Using a metrics based on simple fractions, a mnemonic awareness is developed with the user and an understanding of how every detail fits together becomes more obvious. The typography becomes the key to any design choices that follows. The user becomes aware of the visual size, and in a cognitive way stimulated to recreate a font size regardless of the fonts limitations.