The purpose of this master thesis was to investigate how effiecient the extractionof radiofrequency quality metrics from digital video broadcast (DVB) streamscan become using software defined radio. Software defined radio (SDR) is a fairlynew technology that offers you the possibility of very flexible receivers and transmitters where it is possible to upgrade the modulation and demodulation overtime. Agama is interested in SDR for use in the Agama Analyzer, a widely deployedmonitoring probe running on top of standard services. Using SDR, Agama coulduse that in all deployments, such as DVB by cable/terrestrial/satellite (DVBC/T/S), which would simplify logistics. This thesis is an implementation of a SDR to be able to receive DVB-C. TheSDR must perform a number of adaptive algorithms in order to prevent the received symbols from being significantly different from the transmitted ones. Themain parts of the SDR include timing recovery, carrier recovery and equalization.Timing recovery performs synchronization between the transmitted and receivedsymbols and the carrier recovery performs synchronization between the carrierwave of the transmitter and the local oscillator in the receiver. The thesis discusses various methods to perform the different types of synchronizations andequalizations in order to find the most suitable methods.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

La tesi estudia el problema de la síntesi de freqüències en les bandes de freqüències de microones i ones mil·limètriques, i la seva aplicació al disseny dels oscil·ladors locals d'un receptor coherent per a la recepció de les *radiobalises que a 12, 20 i 30 GHz emetia el satèl·lit Olympus de l'Agència Espacial Europea (ESA), amb la finalitat de caracteritzar el comportament radioelèctric de l'atmosfera a aquestes freqüències, a partir de mesures d'atenuació i transpolarització sobre aquests senyals de test, tot això dintre del marc d'un experiment de propagació (OPEX) propiciat per l'agència.La tesi s'ha centrat en l'estudi dels sistemes de síntesis de freqüències utilitzats habitualment, i especialment en els de síntesi indirecta de freqüència basats en sistemes Phase Locked Loop (PLL) a freqüències de microones ja que són la base sobre la qual s'han dissenyat i construït els prototips de multiplicadors de freqüència que s'han desenvolupat, capaços de sintetitzar senyals en bandes de mil·limètriques, que en el nostre cas s'han restringit al marge de 1 a 29 GHz.Alguns dels multiplicadors fan ús de la detecció de fase harmònica, sistema que permet realitzar multiplicacions de freqüència d'índex imparell, evitant la utilització de divisors de freqüència en el llaç de realimentació del PLL.La tesi s'estructura en quatre parts diferenciades. La primera, amb un caire eminentment teòric, s'ofereix a manera de revisió dels aspectes del soroll de fase i dels sistemes de síntesis de freqüències existents. La segona part aborda les qüestions derivades de la síntesi de freqüències en microones mitjançant PLL's, amb descripció dels components utilitzats, per a passar a tractar dels aspectes de disseny d'un receptor coherent, els seus requisits i aplicacions. En la tercera part es presenten els multiplicadors de freqüència realitzats, la seva descripció, esquema de blocs i resultats experimentals obtinguts. I finalment, en la quarta part s'inclouen una sèrie de realitzacions derivades de la utilització de sistemes PLL a freqüències de microones, amb sincronització per injecció del VCO al senyal de referència, en aplicacions de combinació de potència i de control electrònic de fase en sistemes phased-arrays amb elements actius. / La tesis estudia el problema de la síntesis de frecuencias en las bandas de frecuencias de microondas y ondas milimétricas, y su aplicación al diseño de los osciladores locales de un receptor coherente para la recepción de las radiobalizas que a 12, 20 y 30 GHz emitía el satélite Olympus de la Agencia Espacial Europea (ESA), con la finalidad de caracterizar el comportamiento radioeléctrico de la atmósfera a estas frecuencias, a partir de medidas de atenuación y transpolarización sobre esas señales de test, todo ello dentro del marco de un experimento de propagación (OPEX) propiciado por la agencia.La tesis se ha centrado en el estudio de los sistemas de síntesis de frecuencias utilizados habitualmente, y en especial en los de síntesis indirecta de frecuencia basados en sistemas Phase Locked Loop (PLL) a frecuencias de microondas puesto que son la base sobre la que se sustentan los prototipos de multiplicadores de frecuencia que se han desarrollado, capaces de sintetizar señales en bandas milimétricas, que en nuestro caso se han restringido al margen de 1 a 29 GHz.Algunos de los multiplicadores hacen uso de la detección de fase armónica, sistema que permite realizar multiplicaciones de frecuencia de índice impar, evitando el empleo de divisores de frecuencia en el lazo de realimentación del PLL.La tesis se estructura en cuatro partes diferenciadas. La primera, con un cariz eminentemente teórico, se ofrece a modo de revisión del tema del ruido de fase y de los sistemas de síntesis de frecuencias existentes. La segunda parte aborda las cuestiones derivadas de la síntesis de frecuencias en microondas mediante PLL's, con descripción de los componentes utilizados, para pasar a tratar de los aspectos de diseño de un receptor coherente, sus requisitos y aplicaciones. En la tercera parte se presentan los multiplicadores de frecuencia realizados, su descripción, esquema de bloques y resultados experimentales obtenidos. Y por último, en la cuarta parte se incluyen una serie de realizaciones derivadas de la utilización de sistemas PLL a frecuencias de microondas, con sincronización por inyección del VCO a la señal de referencia, en aplicaciones de combinación de potencia y de control electrónico de fase en sistemas phased-arrays con elementos activos. / The thesis studies the problem of the synthesis of frequencies in the microwave and millimeter waves frequency bands, and its application to the design of the local oscillators of a coherent receiver for the reception of the radio beacons that to 12, 20 and 30 GHz emitted the satellite Olympus from the European Space Agency (ESA), with the aim of characterizing the radio behavior of the atmosphere at these frequencies, from measurements of attenuation and transpolarisation on those signals of test, all that in the framework of a propagation experiment (OPEX) favored by the agency.The thesis has been focused on the study of the frequency synthesis systems, and especially on the indirect frequency synthesis systems based on Phase Locked Loops (PLL) at microwave frequencies, since they are the base on which the prototypes of frequency multipliers that they have been developed, capable of synthesizing signals in millimeter bands, are held that in our case they have restricted regardless of 1 to 29 GHz.Some of the multipliers make use of the harmonic phase detection system that allows carrying out frequency multiplications of odd index, preventing the use of frequency dividers in the feedback loop of the PLL.The thesis is structured in four differentiated parts. The first, with an eminently theoretical look, offers like revision of the subject of the phase noise and the methods of frequency synthesis. The second part tackles the questions derived from the synthesis of frequencies in microwaves through PLL's, with description of the used components, to pass to deal of the aspects of design of a coherent receiver, its requirements and applications. In the third part the frequency multipliers carried out, its description, schema of blocks and obtained experimental results are presented. And finally, in the fourth part a series of accomplishments are included phased-arrays derived of the use of systems PLL at frequencies of microwaves, with synchronization by injection of the VCO to the reference signal, in applications of power combination and of electronic phase control in systems with active elements.

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

No description available.

This doctoral thesis deals with design aspects of a reconfigurable frequency synthesizer for flexible radio transceivers in future cognitive multi-radios. The frequency bandwidth to be covered by this multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards in the frequency band 800 MHz to 6 GHz. Since multi-standard operation is required, the synthesizer must fulfil the most stringent and sometimes conflicting requirements. Given these requirements, a novel approach for multi-mode frequency synthesis has been conceived. A hybrid phase locked loop based frequency synthesizer has been proposed and a novel switching protocol has been presented and validated on an experimental evaluation board. This approach combines fractional-N and integer-N modes of operation with switched loop filter topology. Compared to standard PLL techniques, the hybrid configuration provides a great flexibility in terms of reconfiguration and moreover, it offers relatively low circuit complexity and low power consumption. This architecture provides reconfiguration of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards. Corresponding analyses, simulations and measurements have been carried out in order to verify the performance and functionality of the proposed solution. A part from the design of the multiband frequency synthesizer, a set of regional measurements of the radio spectrum utilization has been carried out in the framework of this dissertation research. These measurements are based on the energy detection principle and provide a close look at the degree of radio spectrum utilization in different regions, namely in the city of Brno in the Czech Republic and in the city of Paris and one of its suburbs in France. The goal of the experimental measurement campaign has been to estimate the degree of radio spectrum usage in a particular environment and to point out the fact that a new approach for radio spectrum management is inevitable

As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers’ relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-10-17T17:02:25Z No. of bitstreams: 1 janisonrodriguesdecarvalho.pdf: 972575 bytes, checksum: 5fe994a5a38fc60a5d01453d58003d1c (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2016-10-25T12:02:47Z (GMT) No. of bitstreams: 1 janisonrodriguesdecarvalho.pdf: 972575 bytes, checksum: 5fe994a5a38fc60a5d01453d58003d1c (MD5) / Made available in DSpace on 2016-10-25T12:02:47Z (GMT). No. of bitstreams: 1 janisonrodriguesdecarvalho.pdf: 972575 bytes, checksum: 5fe994a5a38fc60a5d01453d58003d1c (MD5) Previous issue date: 2008-02-15 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação apresenta uma abordagem sobre a estimação de parâmetros de harmônicos/inter-harmônicos de sinais elétricos no cenário de freqüência variante. Como resultados, são obtidas duas novas metodologias, adequadas para o processamento de tais sinais. A primeira estrutura é baseada no erro de fase da Transformada Discreta de Fourier (DFT – Discrete Fourier Transform) para sinais com desvio de freqüência. Ela faz uso de filtros digitais para eliminação das oscilações dos resultados da DFT e estimação do desvio da freqüência do sinal. Com as equações de resposta em freqüência do filtro DFT são então realizadas as correções de amplitude e fase. A segunda estrutura, principal foco desta dissertação, é obtida com a associação de bancos de filtros e processamento multitaxa com ferramentas de estimação de parâmetros, neste caso os Phase-Locked Loop (PLL). Nesta estrutura, o banco de filtros é responsável pela decomposição do sinal analisado separando as componentes harmônicas. A utilização de dispositivos de diminuição de taxa, os downsamplers, possibilita que os PLLs possam realizar as estimações trabalhando com freqüência inferior à freqüência do estágio de filtragem. Para os harmônicos de alta ordem os parâmetros reais são obtidos, inclusive, a partir de sinais sub-amostrados, resultantes do processo de redução de taxa. A análise dos resultados obtidos com estas estruturas é realizada, sendo realizadas comparações com o desempenho do algoritmo tradicional STFT (Short-Time Fourier Transform), da DFT recursiva e de uma estrutura baseada em PLL encontrada na literatura. Com o intuito de implementação em tempo real em plataformas DSP (Digital Signal Processors) é realizado também o levantamento do esforço computacional aproximado, com comparações com os métodos já citados. / This dissertation discusses parameter estimation of harmonics/inter-harmonics of electrical signals under time-varying conditions. Two new suitable approaches for processing this kind of signals are proposed. The first one is based on phase error of DFT (Discrete Fourier Transform) result, occurring due to the frequency deviation of input signal. This method makes use of digital filters to prevent oscillations of DFT results, estimating the frequency with a simple linear equation. Magnitude and phase response of DFT filter are then used to provide correct estimations of amplitude and phase. The second one, the central focus of this work, is obtained from the association of a digital analysis filter bank and multirate processing with an estimation tool: the Phase-Locked Loop (PLL). The filter bank is responsible for decomposition of the analyzed signal, separating it in its harmonic components. Down-sampler devices follow the filter stage, resulting in an estimation stage working with reduced sampling rate. For high-order harmonics, parameters are estimated from signals obtained by undersampling operation. Simulations results are presented, comparing performance of proposed methods with performances of traditional STFT (ShortTime Fourier Transform) algorithm, DFT Recursive algorithm and PLL-based single rate structure found in literature. With the aim in a DSP-based platform implementation, approximated counts show the number of arithmetic operations of each method, pointing out the methods more suitable for this purpose.

[pt] Trata-se de um sistema capaz de sintetizar sinais musicais através da geração e do processamento de espectros de freqüência que podem ocupar qualquer região da faixa de audição humana. Para obtenção de componentes espectrais passíveis de controle em amplitude e em fase, descreve-se um gerador de série de Fourier concebido a partir de multiplicadores de freqüência que utilizam redes de fase presa. Com este gerador é possível ainda a produção de espectros cujas componentes não se relacionam harmonicamente. O processamento espectral consta da imposição de um caráter dinâmico às componentes: cada harmônico do gerador de série de Fourier é modulado em amplitude por curvas que podem assumir uma multiplicidade de forma, de modo a se estabelecerem possibilidades de elaboração musical. Além disso, dispõe-se de um sistema gerador de tempos para comando dos instantes de atuação das curvas de amplitude. Finalmente, discute-se a maneira de deslocamento do espectro dentro da faixa audível. / [en] It is presented a system capable of synthesize musical signals by generating and processing frequency spectra which can be placed anywhere in the áudio frequency range. For obtaining spectral components which are amplitude and phase controlable, a Fourier series generator was conveived through frequency multipliers which use phase- locked loop techniques. With this generator, there exists too the possibility of generate spectra whose upper partials are not harmonically related. The spectral processing is carried out by imposing a dynamic character to the partials: each of them is amplitude modulated by curves capable of assuming a plurality of forms, such that possibilities of musical work can be stablished. Further, a time generator system for control of the spectrum is described. Finallly , the means for shifting the spectrum within the audio frequency range is discussed.

Traditional implementations of optical receivers are designed to operate with external photodetectors or require integration in a hybrid technology. By integrating a CMOS photodetector monolithically with an optical receiver, it can lead to the advantage of speed performance and cost. This dissertation describes the implementation of a photodetector in CMOS technology and the design of an optical receiver front-end and a clock and data recovery system. The CMOS detector converts the light input into an electrical signal, which is then amplified by the receiver front-end. The recovery system subsequently processes the amplified signal to extract the clock signal and retime the data. An inductive peaking methodology has been used extensively in the front-end. It allows the accomplishment of a necessary gain to compensate for an underperformed responsivity from the photodetector. The recovery circuits based on a nonlinear circuit technique were designed to detect the timing information contained in the data input. The clock and data recovery system consists of two units viz. a frequency-locked loop and a phase-locked loop. The frequency-locked loop adjusts the oscillator’s frequency to the vicinity of data rate before phase locking takes place. The phase-locked loop detects the relative locations between the data transition and the clock edge. It then synchronises the input data to the clock signal generated by the oscillator. A system level simulation was performed and it was found to function correctly and to comply with the gigabit fibre channel specification. / Dissertation (MEng (Micro-Electronics))--University of Pretoria, 2007. / Electrical, Electronic and Computer Engineering / unrestricted