The goal of software-defined radio (SDR) is to move the processing of radio signals from the analog domain to the digital domain — to use digital microchips instead of analog circuit components. Until faster, higher-precision analog-to-digital (ADCs) and digital-to-analog converters (DACs) become affordable, however, some analog signal processing will be necessary. We still need to convert high-radio frequency (RF) signals that we receive to low intermediate-frequency (IF) or baseband (centered on zero Hz) signals in order for ADCs to sample them and feed them into microchips for processing. The reverse is true when we transmit. Amplification is also needed on the receive side to fully utilize the dynamic range of the ADC and power amplification is needed on the transmit side to increase the power output from the DAC for transmission. Analog filtering is also needed to avoid saturating the ADC or to filter out interference when receiving and to avoid transmitting spurs. The analog frequency conversion, amplification and filtering section of a radio is called the RF front end. This thesis describes work on a new RF front end daughterboard for the Universal Software Radio Peripheral, or USRP. The USRP is a software-radio hardware platform designed to be used with the GNU Radio software radio software package. Using the Motorola RFIC4 chip, the new daughterboard receives RF signals, converts them to baseband and does analog filtering and amplification before feeding the signal into the USRP for processing. The chip also takes transmit signals from the USRP, converts them from baseband to RF and amplifies and filters them. The board was designed and laid out by Randall Nealy. I wrote the software driver for GNU Radio. The driver defines the interface between the USRP and the RFIC chip, controls the physical settings, and calculates and sets the hundreds of variables necessary to operate this extremely complex chip correctly. It allows plug-and-play compatibility with the current USRP daughterboards and supplies additional functions not available in any other daughterboard. / Master of Science

Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance. / Doctor of Philosophy / To keep up with the ever-growing demand for exchanging information through a radio frequency (RF) wireless network, the specification of the communication hardware (i.e. transmitter and receiver) must be improved as the bottleneck of the system. This has been motivating engineers to introduce new and efficient approaches toward this goal. In this dissertation however, we study three aspects of the circuit design. First, variation in the ambient temperature can significantly degrade the performance of the communication system. Therefore, we study these variations on the performance of the transmitter at high temperature (i.e. above 200 C). Then, the temperature compensation approaches are introduced to minimize the impact of the temperature changes. The effectiveness of the introduced techniques are validated through measurements of the prototyped transmitter. Second, signal generators (i.e. oscillators) are the inseparable blocks of the transmitters. Phase noise is one of the most important specifications of the oscillators that can directly be translated to the quality and data rate of the communication. A new oscillator structure targeting ultra-low phase noise is introduced in the second part of this dissertation. The designed oscillator is fabricated and measured to evaluate its performance. Finally, a new polar transmitter architecture for low power applications is introduced. The transmitter offers design simplicity and compact size compared to other polar transmitter architectures while high performance.

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit. / Master of Science

This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed. In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs. We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.

In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.

Modern wireless communication techniques employed in the Wi-Fi® protocol, such as orthogonal frequency-division multiplexing exhibit analogue signals with high peak-to-average power ratio. Therefore, power amplifiers for Wi-Fi suffer from low efficiency when operating in back-off mode, away from their maximum efficiency at peak power. In recent years, digital power amplifiers have been developed to replace their analogue equivalent, taking advantage of easier scaling and circumventing transition frequency issues. Since the digital power amplifier technology for Wi-Fi application is recent, it has not yet replaced robust analogue amplifiers in industrial context. This work proposes to investigate the feasibility and complexity to replace an analogue amplifier with its digital counterpart, with at least the same specification. Among several possible architectures, the reverse class D is chosen for its apparent simplicity. It achieves low power loss into transistors parasitics by operating in square-current mode instead of voltage mode, hence displaying a current-based RF-DAC behaviour. After elaborating the core design with simple efficiency enhancement techniques specific to reverse class D, the layout of the circuitry has been designed. Post-layout simulations have shown the reverse class D digital amplifier designed in CMOS 22nm achieves the required specification of 18dBm average output power with -28dB error vector magnitude in the 2.4GHz range. This basic architecture achieves 19% average drain efficiency, a small improvement over its analogue equivalent currently in use. / Moderna trådlösa kommunikationstekniker som används i Wi-Fi®-protokollet, till exempel ortogonal frekvensdelningsmultiplexering, uppvisar analoga signaler med hög variation i amplitud. Därför har effektförstärkare för Wi-Fi låg verkningsgrad eftersom de arbetar i back-off-läge, långt ifrån sin maximala verkningsgrad vid hög uteffekt. Under de senaste åren har digitala effektförstärkare utvecklats för att byta ut deras analoga motsvarigheter. Eftersom digitala effektförstärkare för Wi-Fi är nya, har de ännu inte ersatt robusta analoga förstärkare i industriella sammanhang. I detta arbete föreslås en undersökning av genomförbarheten och komplexiteten i att ersätta en analog förstärkare med dess digitala motsvarighet, med åtminstone samma specifikation. Bland flera möjliga arkitekturer har den strömbaserade klass D valts på grund av sin enkelhet. Den uppnår låg effektförlust i transistorparasiter genom att arbeta i strömsläge istället för i spänningsläge, och fungerar som en strömbaserade RF-DAC. Efter att ha utarbetat kärnkonstruktionen med enkla tekniker för effektivitetsförbättring som är specifika för strömbaserade klass D har kretsens layout utformats. Simuleringar efter layouten har visat att den digitala förstärkaren i strömbaserade klass D som konstruerats i CMOS 22nm uppnår den nödvändiga specifikationen på 18 dBm genomsnittlig uteffekt med -28 dB felvektorstorlek vid 2,4 GHz. Denna arkitektur uppnår en genomsnittlig verkningsgrad på 19%, vilket är en liten förbättring jämfört med den analoga motsvarighet som för nuvarande används.

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered. / Master of Science

The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions. The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90<degree> balance was achieved, over a specific range of LO power levels, with a square wave noise signal injected onto the mixer DC supply rails. The susceptibility of receiver I/Q balance to mixed-signal effects in a SoC environment motivates the second part of this dissertation --- the design of a phase and amplitude tunable, quadrature voltage-controlled oscillator (QVCO) for the on-chip synthesis of quadrature signals. The QVCO design, implemented in the Freescale (formerly Motorola) 0.18um SiGe:C RFBiCMOS process, uses two identical, differential LC-tank VCOs connected such that the two oscillator outputs lock in quadrature to the same frequency. The QVCO designs proposed in this work provide the additional feature of phase-tunability, i.e. the relative phase balance between the quadrature outputs can be adjusted dynamically, offering a simulated tuning range of ~90<degree>+/-10â ¹degree> in addition, a variable-gain buffer/amplifier circuit that provides amplitude tunability is introduced. One potential application of the QVCO is in a self-correcting RF receiver architecture, which, using the phase and amplitude tunability of the QVCO, could dynamically adjust the IF output quadrature phase and amplitude balance, in near real-time, in the analog-domain. The need for high-quality inductors in both the DCR and QVCO designs motivates the third aspect of this dissertation --- the characterization and modeling of on-chip spiral inductors with patterned ground shields, which are placed between the inductor coil and the underlying substrate in order to improve the inductor quality factor (Q). The shield prevents the coupling of energy away from the inductor spiral to the typically lossy Si substrate, while the patterning disrupts the flow of induced image currents within the shield. The experimental effort includes the fabrication and testing of a range of inductors with different values, and different types of patterned ground shields in different materials. Two-port measurements show a ~50% improvement in peak-Q and a ~20% degradation in self-resonant frequency for inductors with shields. From the measured results, a scalable lumped element model is developed for the rapid simulation of spiral inductors with and without patterned ground shields. The knowledge gained from this work can be combined and applied to a range of future RF/wireless SoC applications. The designs developed in this dissertation can be ported to other technologies (e.g. RF CMOS) and scaled to other frequency ranges (e.g. 24GHz ISM band) to provide solutions for emerging applications that require low-cost, low-power RF/microwave circuit implementations. / Ph. D.

Ce travail de thèse s’inscrit dans le cadre d’un projet Français « VéLo » qui est une collaboration entre l’industriel STMicroelectronics et plusieurs laboratoires dont les laboratoires IMS-bordeaux et LAAS. Le but du projet est de concevoir un prototype de radar anticollision millimétrique. Dans ce travail un synthétiseur de fréquence est implémenté. Ce dernier sera intégré dans la chaine de réception du démonstrateur. Une étude bibliographique des architectures classiques de système de radiocommunication a été réalisée. Des exemples d’architectures rencontrées dans le domaine millimétrique ont été étudiés.L’objet principal de cette thèse est l’étude des oscillateurs synchronisés par injection ILO. L’objectif est de réaliser un oscillateur verrouillé par injection qui sera piloté par un oscillateur de fréquence plus basse possédant des caractéristiques de stabilité et de bruit meilleures.Dans ce travail de thèse, le mécanisme de verrouillage des oscillateurs par injection a été décrit. Un modèle de synchronisation par injection série, basé sur la théorie de Huntoon Weiss et inspiré du travail de Badets réalisé sur les oscillateurs synchrones verrouillés par injection parallèle, est proposé. La théorie établie a permis d’exprimer la plage de synchronisation en fonction de la topologie utilisée et des composants de la structure. La validité de la théorie a été évaluée par la simulation de la structure. Les résultats présentés montrent une bonne concordance entre la simulation et la théorie et permettent de valider le principe de synchronisation par injection. La faisabilité de l’intégration d’un ILO millimétrique synchronisé par l’harmonique d’un signal de référence de fréquence plus basse a été démontrée expérimentalement. Le synthétiseur de fréquence est réalisé en technologie BiCMOS 130nm pour des applications millimétriques de STMicroelectronics. Ce dernier opère dans une plage de 2GHz autour de la fréquence 82,5GHz. Les performances en bruit du synthétiseur sont satisfaisantes. Le bruit de phase de l’ILO recopie celui du signal injecté. Les équipements de mesures utilisés, le bruit de phase de l’oscillateur atteint des valeurs inférieures à -110dBc/Hz à 1MHz de la porteuse. / This thesis is a part of a French project "VELO". The project is collaboration between STMicroelectronics and several laboratories including IMS-Bordeaux and LAAS laboratories. The aim of this project is to achieve a prototype of millimeter anti-collision radar. In this work a frequency synthesizer is implemented. This circuit will be incorporated in the reception chain of the demonstrator. A bibliographical study of classical architecture was completed. Examples of architectures encountered in the millimeter frequency range have been studied. The purpose of this thesis is to study the phenomena of synchronization in oscillators. The objective is to design an injection locked oscillator ILO driven by another oscillator, the second oscillator operates at lower frequency and offers better stability and noise characteristics.In this thesis, the injection locking mechanism of the oscillators has been described. A model of synchronization by series injection is proposed. The model is based on the theory of Huntoon and Weiss and inspired by Badets’ work performed on parallel injection. The theory expresses the synchronized frequency range depending on the used topology and the values of the components. The validity of the theory was evaluated by simulation. The results show good agreement between simulation and theory and validate the principle of synchronization by injection.The feasibility of a millimeter ILO synchronized by the harmonic of a reference signal operating at lower frequency has been demonstrated experimentally. The synthesizer was implemented in BiCMOS technology for 130nm applications millimeter of STMicroelectronics. The oscillator operates at 82.5 GHz and performs a frequency range of 2GHz. The noise performance of the synthesizer is satisfactory. The phase noise of the ILO depends on the reference phase noise, and reaches values of -110dBc/Hz at 1MHz from the carrier frequency.

Cette thèse est une étude sur la caractérisation, la modélisation et l’optimisation des effets substrat dans les circuits intégrés, dédies à des applications WLAN.L’objectif de ces travaux de recherche est de développer une nouvelle méthodologie d’extraction qui prenne en compte tous les parasites ; à savoir les modèles RLCK distribués, les effets électromagnétiques, ainsi que le couplage substrat.Les effets substrat ont été optimisés grâce au développement de nouvelles structures d’isolation utilisant des tranches profondes d’isolation (DTI).La prédictibilité des simulations circuits a été améliorée grace à l’introduction d’une nouvelle méthodologie d’extraction, basée sur une approche quasi-statique prenant en compte avec précision la description exacte et complète du procédé BiCMOS ainsi que les pertes dans le substrat, aussi bien diélectriques que résistives.La validité de cette méthodologie a été évaluée en comparant les résultats de simulation avec les mesures sur silicium. La bonne corrélation des résultats démontre la pertinence de cette nouvelle méthodologie. Cette méthode permet de plus, de réduire le « time to maket » grâce à l’optimisation des temps de simulations. / This thesis is about characterization, modelling and optimization of substrate effects in integrated circuits, dedicated to WLAN applications.The objective of this thesis is to develop a new extraction methodology that takes into account all parasites; distributed RLCK models, electromagnetic effects, as well as substrate coupling.Substrate effects have been optimized through the development of a new insulation strategies using deep isolation isolation (DTIs).The circuit predictability has been improved thanks to the development of a new extraction methodology, based on a quasi-static approach taking into account the complete description of the BiCMOS process as well as the substrate loss, both capacitive and resistive effects.The validation of this methodology was evaluated by comparing simulation results with silicon measurements. The good correlation of the obtained results demonstrates the accuracy of this new methodology. This method also makes it possible to reduce the time to market thanks to the optimization of the simulation times.