Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.

The thesis focuses on designing and characterizing SiC 3.3 kV Diffused Metal-Oxide Semiconductor Field-Effect Transistor (DMOSFET)s with a Ron that is significantly lower than that of current commercial devices. The On-state resistance and breakdown voltage are then adjusted by adding a Super-Junction structure. Because of the pillar structure below the p-base area, the depletion will occur both vertically and horizontally and keeps the electric field distribution throughout the drift layer constant. The Super Junction Metal-Oxide Semiconductor Field-Effect Transistor (SJ MOSFET) has a good advantage compared to DMOSFETs. Due to its capacity to tolerate higher breakdown voltages and the fact that it does not require an increase in cell pitch to reach higher voltages, the Super-Junction approach is now the subject of effective research as compared to IGBTs and DMOSFETs. Silicon Carbide , a material with a wide bandgap that facilitates high temperature operation, high blocking voltage, high current flow and high switching frequency, is used to construct the device. In order to maintain a consistent electric field throughout the device, the concentration of the n and p pillars was chosen with a good charge balance between them. The outcomes of designing and simulating a DMOSFET, a Semi-SJ MOSFET, and a Full SJ MOSFET are compared in this research. The semi SJ device resulted in a Ron of 18.4 mΩcm2 and a Vb of 4.1 kV. The full SJ device reached a Ron of 12.4 mΩcm2 and a breakdown voltage of 4.2 kV. One optimized device was chosen from the semi SJ devices and used in several TCAD simulations, and the outcomes were evaluated based on the JFET width, pillar thickness, and charge imbalance between the p and n pillars. In this study, the device was also modelled for 6.5 kV and 10 kV SiC blocking voltage capabilities; the findings are also discussed. / Denna uppsats fokuserar på att utveckla och karakterisera 3.3 kV kiselkarbidbaserade DMOSFET-transistorer med betydligt lägre framspänningsfall jämfört med kommersiella halvledarkomponenter. Framspänningsfallet och spärrspänningen modifieras genom att använda en pelarliknande halvledarstruktur i drift regionen, dvs. en super-junction [SJ] struktur. På grund av pelarstrukturen under p-bas området, uppträder utarmningsområdet av laddningsbärare både vertikalt och horisontellt och ger ett konstant elektriskt fält genom drift-regionen. Super-junction transistorer har flera fördelar jämfört med komponenter i DMOSFET struktur. På grund av sin kapacitet att motstå högre spärrspänningar och genom att strukturen inte behöver en större enhetscellbredd för att nå högre spärrspänning, så är just nu super-junction strukturer i stort forskningsfokus jämfört med IGBT och DMOSFET komponenter. Kiselkarbid, ett material med ett brett bandgap, möjliggör komponenter för höga temperaturer, höga spärrspänningar, höga elektriska strömmar, samt höga växlingsfrekvenser, har använts för att bygga de undersökta komponenterna. För att generera ett konstant elektriskt fält över drift-regionen, så har dopningsnivåerna för n- och p- pelarna valts för att hålla en bra laddningsbalans mellan dem. Simuleringsresultaten av dessa komponentstrukturer, DMOSFET, halv-SJ MOSFET, och hel-SJ MOSFET är jämförda i detta projekt. Halv-SJ MOSFET transistorn resulterade i ett framspänningsfall på 18.4 mΩcm2 och når en spärrspänning av 4.1 kV. Hel-SJ MOSFET strukturen uppnår ett framspänningsfall på 12.4 mΩcm2 och med spärrspänning av 4.2 kV. En optimerad halv-SJ struktur valdes ut för att genomföra ytterligare TCAD simuleringsstudier om effekterna av JFET bredd, pelartjocklek, samt laddningsobalans mellan n- och p- pelarna. I den här studien simulerades även komponentstrukturer för 6.5 kV och 10 kV spärrspänningsklasser; även dessa resultat diskuteras i rapporten.

Silicon Carbide as a wide-bandgap semiconductor has several physical and electrical advantages over Silicon for high voltage and high frequency applications. SiC as a MOSFET device has a lot of great characteristics like lower on-resistance and low input capacitances. However, due to its high switching capabilities, SiC MOSFET-based converter circuits experience higher dv/dt and di/dt transients and are therefore more susceptible to parasitic elements. This thesis investigates the interaction of the parasitic gate inductance and resistance on the switching behaviour of SiC DMOSFET (planar) and UMOSFET (trench). To examine this, a double pulse test (DPT) setup was utilised both in simulation and experimentally. The influence of the gate inductance and resistance on the oscillation behaviour in the VGS during the miller period was found to be dependent on the condition of the upper device. Furthermore, the upper device was discovered to have a high impact on the oscillations in the VGS via its source inductance. The gate inductance showed a mixed impact on IDS and VDS overshoot, with IDS overshoot reducing with increasing gate inductance and the reverse case for VDS. The gate resistance, however, showed a consistent impact on both IDS and VDS overshoot, with both reducing with increasing gate resistance. These results ultimately point to the impact of di/dt and dv/dt transients. An interesting result observed on these root causes showed that in the DPT arrangement used, lower test current levels may have a more significant impact on the oscillations in the VGS than higher test current when varying the test currents, with 20 A having the highest impact on the oscillations in simulations and 15 A having the highest impact in experimental verification. On the switching energy, the gate inductance was not shown to have a significant impact on switching losses while the gate resistance had a much more significant impact on the switching losses. / Kiselkarbid som halvledare med brett bandgap har flera fysiska och elektriska fördelar jämfört med kisel för högspännings- och högfrekvensapplikationer. SiC som en MOSFET-enhet har många fantastiska egenskaper som lägre resistans och låga ingångskapacitanser. Men på grund av dess höga omkopplingsförmåga upplever SiC MOSFET-baserade omvandlarkretsar högre dv/dt och di/dt transienter och är därför mer mottagliga för parasitiska element. Denna avhandling undersöker interaktionen mellan gate-drivkretsens parasitära induktans och resistans på kopplingsbeteendet på SiC DMOSFET (plan) och UMOSFET (trench). För att undersöka detta användes en dubbelpulstest (DPT) mätuppställning både i simulering och experimentellt. Inverkan av grindinduktansen och motståndet på svängningsbeteendet i VGS under Millerperioden visade sig vara beroende av den övre anordningens tillstånd. Vidare upptäcktes att den övre anordningen hade en hög inverkan på svängningarna i VGS via dess parasitiska induktans. Gate-induktansen visade en blandad inverkan på IDS- och VDS-översvängning, med IDS-översvängning som minskade med ökande gateinduktans och det omvända fallet för VDS. Gatemotståndet visade dock en konsekvent inverkan på både IDS- och VDS-överskridningar, med båda minskande med ökande gatemotstånd. Dessa resultat pekar slutligen på inverkan av di/dt- och dv/dt-transienter. Ett intressant resultat som observerats på dessa grundorsaker visade att i det använda DPT-arrangemanget kan lägre testströmnivåer ha mer signifikant inverkan på svängningarna i VGS än högre testström vid variation av testströmmarna, med 20 A som har den högsta inverkan på svängningarna i simuleringar och 15 A som har störst effekt vid experimentell verifiering. På omkopplingsenergin visades inte grindinduktansen ha någon signifikant inverkan på omkopplingsförlusterna medan grindresistansen hade mycket mer betydande inverkan på omkopplingsförlusterna.

Organic coatings are extensively used as protective coatings in several industries including the automotive and aircraft industries. The last few years have witnessed an increased interest in improving not only the mechanical properties but also the corrosion protection properties of organic coatings. Among the currently investigated methods of improving the performance of organic coatings is the incorporation of additives in the organic paint matrix. Vapor grown carbon nanofibers (VGCNFs) are a class of carbon fibers that are produced by catalytic dehydrogenation of a hydrocarbon at high temperatures. Depending on the method of synthesis and the post-treatment processes, the diameter of the VGCNFs is normally in the 10-300 nm range. The small size, light weight, high aspect ratio, and unique physical, thermal, mechanical, and electrical properties of VGCNF make it an ideal reinforcing filler in polymer matrix nanocomposites to enhance the mechanical properties of the pure polymeric material in high performance applications in several industries such as the automotive, aircraft, battery, sensors, catalysis, electronics, and sports industries. The main objective of the current investigation was to study the corrosion protection offered by the incorporation of VGCNFs into a commercial alkyd paint matrix applied to the surface of mild steel coupons. The corrosion protection was investigated by immersing samples in air saturated 3% NaCl solution (artificial seawater). The samples were studied by electrochemical impedance spectroscopy (EIS) along with other measurements, including electrochemical (open circuit potential, cyclic voltammetry), chemical (salt spray test), electrical conductivity, and surface analysis (SEM, AFM, optical profilometry, and nanoindentation). The study involved the investigation of the effect of the weight percent (wt %) of the VGCNF as well as the coating film thickness on the corrosion protection performance of the coated steel samples when exposed to the corrosive electrolyte. By way of contrast, the EIS behavior of steel coupons coated with a paint coating incorporating different weight percents of powdered silicon carbide (SiC) particles was also studied. The EIS spectra were used to calculated and graph several corrosion parameters for the investigated systems. At the end, the studied coatings were ranked in order of their anticorrosive properties.

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Silicon Carbide (SiC), owing to its large bandgap, has proved itself to be a very viable semiconductor material for the development of extreme temperature electronics. Moreover, its electrical properties like critical field (Ecrit) and saturation velocity (vsat) are superior as compared to the commercially abundant Silicon, thus making it a better alternative for RF and high power applications. The in-house SiC BJT process at KTH has matured a lot over the years and recently developed devices and circuits have shown to work at temperatures exceeding 500˚C. However, the functional reliability of more complex circuits requires the use of simulators and device models to describe the behavior of constituent devices. SPICE Gummel Poon (SGP) is one such model that describes the behavior of the BJT devices. It is simpler as compared to the other models because of its relatively small number of parameters. A simple semi-empirical DC compact model has been successfully developed for low voltage applications SiC BJTs. The model is based on a temperature dependent SiC-SGP model. Studies over the temperature dependences for the SGP parameters have been performed. The SGP parameters have been extracted and some have been optimized over a wide temperature range and they have been compared with the measured data. The accuracy of the developed compact model based on these parameters has been proven by comparing it with the measured data as well. A fairly accurate performance at the required working conditions and correlation with the measured results of the SiC compact model has been achieved.

KTH is funding a project whose goal is to send a satellite into space. This project is called MIST (Miniature Student Satellite) which is assembled by a team of students at KTH. On the satellite there are experiments that are invented by other teams, in two of those experiments a power supply is required. This thesis is a technical investigation on how to design the power supply to both of those experiments, which are called SiC and Piezo LEGS. Piezo LEGS will investigate how their nanosized motors will behave and function in a space environment. SiC will investigate how their silicone carbide transistors will be affected by the space environment. A team made of four other students was selected to produce SiC experiments and a PCB in which this work is included. A literature study was done to get a better understanding of how power supplies work and to know how to select a good power supply. When the power supplies were selected they were simulated to meet the requirements. The next step was to do a Printed Circuit Board(PCB) for the SiC experiment and Piezo LEGS to be able to test the power supplies functionality in the physical world. Both of the converters reached the required output and characteristics working on their respective PCB. More time is needed for long time testing and optimization on the PCB layouts. / MIST (Miniature Student Satellite) är ett av KTH subventionerat projekt vilket har som mål att skicka upp en satellit i rymden. Projektet kommer omfatta flera olika experiment. Piezo LEGS ska undersöka en motors funktionalitet i rymdmiljö. SiC ska undersöka hur Silicon carbide halvledare och transistorer påverkas av rymdmiljön. Båda experimenten kräver varsin strömförsörjning för att fungera. Detta projekt ska undersöka kraven på strömförsörjning samt testa prototypen av ett kretskort för densamma. Först genomfördes en förstudie av de två typer av regulatorer som vanligtvis används som strömförsörjning, den linjära regulatorn och switch-mode regulatorn för att förklara olika strömförsörjningsteknologier, samt ta reda på de olika miljökraven. Baserat på förstudiens resultat erhölls kunskap för hur tester ska tas fram för funktionalitet av regulatorerna så att de når kraven för MIST för att sedan kunna producera de båda regulatorerna. Målet är att resultatet av simuleringarna på strömförsörjningen ska stämma överens med utfallet av kretskorten som produceras. Mätningar genomfördes på prototyp kretskort som visade att simuleringarna var korrekta och gav strömförsörjningen rätt resultat på kretskorten. Några av funktionerna på regulatorerna hann ej testas på grund av tidsbrist och mycket framtida arbete kvarstår.

The contribution describes the construction of a CVD system, the deposition of thin molybdenum disulphide layers using this system and the analysis of the samples produced. The deposition of thin molybdenum disulphide layers and an intercalation of the silicon carbide substrate used were demonstrated and the measurement results obtained by atomic force microscopy and photoelectron spectroscopy were further discussed.